[go: up one dir, main page]

TWI436470B - 封裝製程及封裝結構 - Google Patents

封裝製程及封裝結構 Download PDF

Info

Publication number
TWI436470B
TWI436470B TW098133269A TW98133269A TWI436470B TW I436470 B TWI436470 B TW I436470B TW 098133269 A TW098133269 A TW 098133269A TW 98133269 A TW98133269 A TW 98133269A TW I436470 B TWI436470 B TW I436470B
Authority
TW
Taiwan
Prior art keywords
encapsulant
semiconductor component
semiconductor
package structure
circuit substrate
Prior art date
Application number
TW098133269A
Other languages
English (en)
Other versions
TW201112385A (en
Inventor
沈啟智
陳仁川
潘彥良
Original Assignee
日月光半導體製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日月光半導體製造股份有限公司 filed Critical 日月光半導體製造股份有限公司
Priority to TW098133269A priority Critical patent/TWI436470B/zh
Priority to US12/711,870 priority patent/US8618645B2/en
Publication of TW201112385A publication Critical patent/TW201112385A/zh
Priority to US14/087,454 priority patent/US9698120B2/en
Application granted granted Critical
Publication of TWI436470B publication Critical patent/TWI436470B/zh
Priority to US15/620,692 priority patent/US11222866B2/en
Priority to US17/573,593 priority patent/US12266632B2/en
Priority to US19/097,838 priority patent/US20250259967A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

封裝製程及封裝結構
本發明是有關於一種封裝製程及封裝結構，且特別是有關於一種將大晶片配置於小晶片上的封裝製程及封裝結構。
在現今的資訊社會中，使用者均是追求高速度、高品質、多功能性的電子產品。就產品外觀而言，電子產品的設計是朝向輕、薄、短、小的趨勢邁進。因此，電子封裝技術發展出諸如堆疊式晶片封裝等多晶片封裝技術。
堆疊式晶片封裝是利用垂直堆疊的方式將多個晶片封裝於同一封裝結構中，如此可提升封裝密度以使封裝體小型化，且可利用立體堆疊的方式縮短晶片之間的訊號傳輸的路徑長度，以提升晶片之間訊號傳輸的速度，並可將不同功能的晶片組合於同一封裝體中。
習知的堆疊式晶片封裝的製作方法是先將多個晶片覆晶接合至一晶圓上，然後沿這些晶片之間的間隙切割晶圓，以形成多個晶片堆疊結構，之後再將晶片堆疊結構配置於一線路板上並於線路板上形成一封裝膠體，以保護晶片堆疊結構。
由於習知的堆疊式晶片封裝的製作方法是藉由切割晶圓的方式來形成多個晶片堆疊結構，因此，在晶片堆疊結構中，由切割晶圓所形成的晶片的尺寸勢必大於覆晶接合至晶圓上的晶片的尺寸。因此，習知的堆疊式晶片封裝的製作方法只能形成將小尺寸晶片配置於大尺寸晶片上的封裝結構。
此外，習知技術為減少堆疊式晶片封裝的整體厚度，會在將晶片覆晶接合至晶圓上之前，先研磨晶圓，以減少晶圓的厚 度。然而，目前覆晶接合技術仍有製程能力上的極限值，因此，當所使用的晶圓厚度小於其製程能力之極限值時，在進行覆晶接合的過程中，容易發生破片的情形，以致於製程良率降低。此外，厚度小的晶圓在切割製程中容易破裂，以致於製程良率降低。
本發明提供一種封裝製程，可製作由各種尺寸的晶片相互堆疊而成的封裝結構，且製程良率高。
本發明提供一種封裝結構，其將大尺寸晶片配置於小尺寸晶片上。
為具體描述本發明之內容，在此提出一種封裝製程如下所述。首先，提供一承載板，承載板上配置有一黏著層。接著，將多個第一半導體元件配置於黏著層上，且第一半導體元件彼此分離並分別透過黏著層固定於承載板上。然後，於承載板上形成一第一封裝膠體，第一封裝膠體覆蓋第一半導體元件的側壁並填滿第一半導體元件之間的間隙，以使第一半導體元件與第一封裝膠體形成一晶片陣列板。之後，將多個第二半導體元件分別覆晶接合至第一半導體元件上。接著，於晶片陣列板上形成一第二封裝膠體，第二封裝膠體至少覆蓋第二半導體元件的側壁並填滿第二半導體元件之間的間隙。然後，分離晶片陣列板與黏著層。之後，沿著第二半導體元件之間的間隙切割第二封裝膠體與第一封裝膠體，以形成多個晶片封裝單元。
在本發明之一實施例中，上述之第一半導體元件具有多個直通矽晶穿孔結構，且封裝製程更包括在形成晶片陣列板之後，研磨晶片陣列板，以薄化晶片陣列板並露出第一半導體元 件的直通矽晶穿孔結構的端面。
在本發明之一實施例中，上述之研磨晶片陣列板的方法包括研磨晶片陣列板直到晶片陣列板的厚度實質上小於或等於4密爾。
在本發明之一實施例中，上述之在將第二半導體元件分別覆晶接合至第一半導體元件之後，第二半導體元件於承載板上的投影面積大於第一半導體元件於承載板上的投影面積。
在本發明之一實施例中，上述之封裝製程更包括在形成晶片陣列板之後，在第一半導體元件上分別形成多個彼此分離的第一底膠，其中各第一底膠覆蓋對應的第一半導體元件以及第一封裝膠體之圍繞對應的第一半導體元件的部分，且在將第二半導體元件分別覆晶接合至第一半導體元件上時，各第二半導體元件的多個導電凸塊通過對應的第一底膠而與對應的第一半導體元件接合。
在本發明之一實施例中，上述之第二封裝膠體暴露出各第二半導體元件之遠離對應的第一半導體元件的一頂面。
在本發明之一實施例中，上述之第二封裝膠體覆蓋各第二半導體元件之遠離對應的第一半導體元件的一頂面。
在本發明之一實施例中，上述之封裝製程更包括將晶片封裝單元配置於一線路基板上，以使第一半導體元件電性與結構性連接線路基板。
在本發明之一實施例中，上述之封裝製程更包括在線路基板上形成一第二底膠，以使第二底膠位於晶片封裝單元的第一半導體元件與線路基板之間並包覆第一半導體元件的多個導電凸塊。
在本發明之一實施例中，上述之封裝製程更包括在線路基 板上形成一第三封裝膠體，第三封裝膠體至少覆蓋晶片封裝單元的側壁。
在本發明之一實施例中，上述之第二封裝膠體與第三封裝膠體共同暴露出晶片封裝單元的第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之第三封裝膠體覆蓋晶片封裝單元的第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之封裝製程更包括於線路基板之遠離晶片封裝單元的一表面上形成多個銲球，且銲球與線路基板電性連接。
為具體描述本發明之內容，在此提出一種封裝結構包括一第一半導體元件、一第一封裝膠體、一第二半導體元件以及一第二封裝膠體。第一封裝膠體包覆第一半導體元件的側壁。第二半導體元件配置於第一半導體元件與部分第一封裝膠體上，且第二半導體元件的尺寸大於第一半導體元件的尺寸。第二封裝膠體至少覆蓋第二半導體元件的側壁以及第一封裝膠體，其中第一封裝膠體與第二封裝膠體為各自成型。
在本發明之一實施例中，上述之第一封裝膠體的側壁切齊於第二封裝膠體的側壁。
在本發明之一實施例中，上述之第一封裝膠體之朝向第二半導體元件的一第一頂面切齊於第一半導體元件之朝向第二半導體元件的一第二頂面。
在本發明之一實施例中，上述之第一封裝膠體的厚度實質上等於第一半導體元件的厚度。
在本發明之一實施例中，上述之第二半導體元件具有位於第二半導體元件與第一半導體元件之間的多個導電凸塊，且封 裝結構更包括一底膠，其配置於第二半導體元件與第一半導體元件之間以及第二半導體元件與第一封裝膠體之間，以包覆第二半導體元件的導電凸塊。
在本發明之一實施例中，上述之第一半導體元件的厚度實質上小於或等於4密爾。
在本發明之一實施例中，上述之第一半導體元件的厚度實質上為2密爾。
在本發明之一實施例中，上述之第二封裝膠體更覆蓋第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之第二封裝膠體暴露出第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之第一半導體元件之遠離第二半導體元件的一底面上配置有多個導電凸塊。
在本發明之一實施例中，上述之封裝結構更包括一線路基板，第一半導體元件配置於線路基板上，且導電凸塊位於第一半導體元件與線路基板之間。
在本發明之一實施例中，上述之封裝結構更包括一底膠，其配置於第一半導體元件與線路基板之間，以包覆導電凸塊。
在本發明之一實施例中，上述之封裝結構更包括一第三封裝膠體，其配置於線路基板上，並至少覆蓋第一封裝膠體的側壁與第二封裝膠體的側壁。
在本發明之一實施例中，上述之第二封裝膠體與第三封裝膠體暴露出第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之第三封裝膠體覆蓋第二半導體元件之遠離第一半導體元件的一頂面。
在本發明之一實施例中，上述之封裝結構更包括多個銲 球，其配置於線路基板之遠離第一半導體元件的一底面上，並與線路基板電性連接。
基於上述，本發明可製得由各種尺寸的晶片相互堆疊而成的封裝結構。此外，由於第二封裝膠體可強化厚度相當小的晶片陣列板，故可穩固地連結全部的第二半導體元件以及全部的第一半導體元件，並可在以切割的方式形成晶片封裝單元的過程中，避免晶片陣列板碎裂，從而提升製程良率。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A~圖1I繪示本發明一實施例之封裝製程的剖面圖。
首先，請參照圖1A，提供一承載板110，承載板110的形狀與大小可相似於一晶圓。承載板110上配置有一黏著層120。接著，將多個第一半導體元件130配置於黏著層120上，且這些第一半導體元件130彼此分離並分別透過黏著層120固定於承載板110上。在本實施例中，第一晶片130的多個導電凸塊132可埋於黏著層120中。
詳細而言，在本實施例中，在將第一半導體元件130配置於黏著層120上之前，可先在第一半導體元件130中形成多個高深寬比的開孔138，並在開孔138的內壁上形成一絕緣層I，然後，在各開孔138中填入一導電材料D，且絕緣層I分隔於導電材料D與開孔138的內壁之間，之後，才在各導電材料D上形成導電凸塊132。
然後，請參照圖1B，例如以印刷(printing)或是壓模(molding)的方式在承載板110上形成一第一封裝膠體140， 其中第一封裝膠體140覆蓋第一半導體元件130的側壁134並填滿第一半導體元件130之間的間隙G1，以使第一半導體元件130與第一封裝膠體140形成一晶片陣列板A。具體而言，在本實施例中，晶片陣列板A是指由第一封裝膠體140以及全部的第一半導體元件130所構成的一板狀結構。
之後，請參照圖1C，在本實施例中，可研磨晶片陣列板A，以薄化晶片陣列板A並暴露出導電材料D。在本實施例中，可研磨晶片陣列板A直到晶片陣列板A的厚度T實質上小於或等於4密爾。在本實施例中，導電材料D、絕緣層I與開孔138可構成直通矽晶穿孔(Through-Silicon Via，TSV)結構V。
由前述可知，第一半導體元件130是採用直通矽晶穿孔(Through-Silicon Via，TSV)技術來與導電凸塊132以及之後將堆疊於第一半導體元件130上的其他晶片(未繪示)電性連接。直通矽晶穿孔技術例如是在晶片或晶圓內部製作導電通道，以形成垂直的直通矽晶穿孔結構V，其可使第一半導體元件130在三維方向的堆疊密度最大化且外形尺寸最小化。因此，第一半導體元件130與之後將堆疊於第一半導體元件130上的其他晶片之間的訊號可透過直通矽晶穿孔結構V來上下傳遞，以減少晶片之間的訊號傳輸路徑長度並減少訊號延遲及功率消耗。
接著，請參照圖1D，在本實施例中，可在晶片陣列板A上以例如點膠或網板印刷的方式形成多個彼此分離的底膠150，其中各底膠150覆蓋對應的第一半導體元件130以及第一封裝膠體140之圍繞對應的第一半導體元件130的部分。詳細而言，每一個底膠150不但完全覆蓋對應的第一半導體元件130，還覆蓋第一封裝膠體140之圍繞對應的第一半導體元件 130的部分。換言之，底膠150於承載板110上的投影面積大於第一半導體元件130於承載板110上的投影面積。底膠150的材質包括非導電性接合膠(non-contact paste，NCP1)或非導電性接合膜(non-contact film，NCF1)。
然後，請參照圖1E，將多個第二半導體元件160分別覆晶接合至第一半導體元件130上，以使各第二半導體元件160的多個導電凸塊162通過對應的底膠150而與對應的第一半導體元件130的直通矽晶穿孔結構V接合。在本實施例中，第二半導體元件160於承載板110上的投影面積大於第一半導體元件130於承載板110上的投影面積。換言之，第二半導體元件160的尺寸大於第一半導體元件130的尺寸。
之後，請參照圖1F，例如以印刷或是壓模的方式在晶片陣列板A上形成一第二封裝膠體170，第二封裝膠體170可選擇性地覆蓋第二半導體元件160的側壁164以及第二半導體元件160之遠離對應的第一半導體元件130的頂面166並填滿第二半導體元件160之間的間隙G2，以保護第二半導體元件160。值得注意的是，由於第二封裝膠體170填滿第二半導體元件160之間的間隙G2，因此，第二封裝膠體170可強化厚度相當小的晶片陣列板A，以穩固地連結全部的第二半導體元件160以及全部的第一半導體元件130。此外，在其他實施例中，可藉由使部分的第二封裝膠體170填入第二半導體元件160與晶片陣列板A之間的方式，來取代形成底膠150的步驟。
然後，請參照圖1G，分離晶片陣列板A與黏著層120。之後，請同時參照圖1G與圖1H，沿著第二半導體元件160之間的間隙G2切割第二封裝膠體170與第一封裝膠體140，以形成多個晶片封裝單元C1。
由前述可知，本實施例是先將多個第一半導體元件130用第一封裝膠體140連接而成一晶片陣列板A，之後再將多個第二半導體元件160分別配置於晶片陣列板A的第一半導體元件130上並用第二封裝膠體170連接，然後切割第一封裝膠體140與第二封裝膠體170而形成多個晶片封裝單元C1。換言之，本實施例是利用第一封裝膠體140與第二封裝膠體170來固定並連接第一半導體元件130與第二半導體元件160，之後再藉由切割第一封裝膠體140與第二封裝膠體170來形成多個晶片封裝單元C1。
如此一來，本實施例不會受限於第一半導體元件130與第二半導體元件160的尺寸關係，亦即本實施例可製作第一半導體元件130的尺寸大於或等於或小於第二半導體元件160的尺寸的晶片封裝單元C1。換言之，本實施例可製得由各種尺寸的晶片相互堆疊而成的封裝結構。此外，由於第二封裝膠體170可強化厚度相當小的晶片陣列板A，故可在以切割的方式形成晶片封裝單元C1的過程中，避免晶片陣列板A碎裂，從而提升製程良率。
接著，請同時參照圖1H與圖1I，在本實施例中，可在一線路基板180(例如印刷電路板)上形成一底膠190，並可將晶片封裝單元C1配置於線路基板180上，以使第一半導體元件130可透過導電凸塊132電性與結構性連接線路基板180，並使底膠190位於晶片封裝單元C1的第一半導體元件130與線路基板180之間以包覆第一半導體元件130的導電凸塊132。
請參照圖1I，在本實施例中，例如以印刷或是壓模的方式在線路基板180上形成一第三封裝膠體M，第三封裝膠體M可覆蓋晶片封裝單元C1的側壁W以及第二半導體元件160 的頂面166。詳細而言，部分的第三封裝膠體M是位於第二封裝膠體170之覆蓋頂面166的部分上，換言之，第三封裝膠體M是間接覆蓋第二半導體元件160的頂面166。在其他未繪示的實施例中，第三封裝膠體M可覆蓋晶片封裝單元C1的側壁W並暴露出第二封裝膠體170之覆蓋頂面166的部分。
另外，在其他實施例中，可藉由使部分的第三封裝膠體M填入第一半導體元件130與線路基板180之間的方式，來取代形成底膠190的步驟。此外，為使晶片封裝單元C1可透過線路基板180電性連接至其他的電子元件，可在線路基板180之遠離晶片封裝單元C1的一底面182上形成多個銲球S，且銲球S與線路基板180電性連接。此時，已初步完成本實施例之封裝結構100。
以下將詳細介紹圖1I的封裝結構100。
請參照圖1I，本實施例之封裝結構100包括一第一半導體元件130、一第一封裝膠體140、一第二半導體元件160以及一第二封裝膠體170。在本實施例中，第一半導體元件130的厚度T2實質上小於或等於4密爾，舉例來說，第一半導體元件130的厚度T2實質上為2密爾。
第一封裝膠體140包覆第一半導體元件130的側壁134。在本實施例中，第一封裝膠體140之朝向第二半導體元件160的一頂面144可切齊於第一半導體元件130之朝向第二半導體元件160的一頂面136，且第一封裝膠體140的厚度T1實質上可等於第一半導體元件130的厚度T2。
第二半導體元件160配置於第一半導體元件130與部分第一封裝膠體140上，且第二半導體元件160的尺寸大於第一半導體元件130的尺寸。換言之，第二半導體元件160之朝向第 一半導體元件130之一底面168的面積小於第一半導體元件130的頂面136的面積。
值得注意的是，本實施例的封裝結構100是將尺寸較大的晶片配置於尺寸較小的晶片上，因此，封裝結構100可適於用在將記憶體晶片等大尺寸晶片配置於運算晶片等小尺寸晶片上的封裝結構中。此外，由於本實施例的第一半導體元件130的厚度T2較小(例如小於或等於4密爾)，故可降低封裝結構100的整體厚度。
第二封裝膠體170覆蓋第二半導體元件160的側壁164、第二半導體元件160之遠離第一半導體元件130的一頂面166以及第一封裝膠體140，其中第一封裝膠體140與第二封裝膠體170可為各自成型，且第一封裝膠體140的側壁142可切齊於第二封裝膠體170的側壁172。
在本實施例中，第二半導體元件160的底面168上配置有多個導電凸塊162，以電性連接至第一半導體元件130。為保護導電凸塊162，可在第二半導體元件160與第一半導體元件130之間以及第二半導體元件160與第一封裝膠體140之間配置一底膠150，以使底膠150包覆導電凸塊162。此外，在其他實施例中，亦可無底膠150，亦即可使部分第二封裝膠體170填充於第二半導體元件160與第一半導體元件130之間以及第二半導體元件160與第一封裝膠體140之間而毋須配置底膠150。
在本實施例中，第一半導體元件130可配置於一線路基板180上，以使第一半導體元件130的多個導電凸塊132電性連接至線路基板180。為保護導電凸塊132，可在第一半導體元件130與線路基板180之間配置一底膠190，以使底膠190包 覆導電凸塊132。
此外，在本實施例中，可在線路基板180上配置一第三封裝膠體M，第三封裝膠體M覆蓋第一封裝膠體140的側壁142、第二封裝膠體170的側壁172與第二半導體元件160之遠離第一半導體元件130的頂面166。詳細而言，部分的第三封裝膠體M是位於第二封裝膠體170之覆蓋第二半導體元件160的頂面166的部分上，換言之，第三封裝膠體M是間接覆蓋頂面166。在其他實施例中，第三封裝膠體M可以覆蓋第一封裝膠體140的側壁142以及第二封裝膠體170的側壁172，並暴露出第二封裝膠體170之覆蓋第二半導體元件160的頂面166的部分。此外，在其他實施例中，亦可無底膠190，亦即可使部分第三封裝膠體M填充於第一半導體元件130與線路基板180之間而毋須配置底膠190。
另外，線路基板180之遠離第一半導體元件130的一底面182上可配置有多個銲球S，銲球S與線路基板180電性連接，且線路基板180可透過銲球S電性連接至其他的電子元件(例如線路板)。
圖2A~圖2D繪示本發明另一實施例之封裝製程的剖面圖。
在本實施例中，可先進行圖1A~圖1E的製程，之後，請參照圖2A，於晶片陣列板A上形成一第二封裝膠體210，第二封裝膠體210可選擇性地覆蓋第二半導體元件160的側壁164並暴露出第二半導體元件160之遠離對應的第一半導體元件130的頂面166，且填滿第二半導體元件160之間的間隙G2，以保護第二半導體元件160。
然後，請參照圖2B，分離晶片陣列板A與黏著層120。 之後，請同時參照圖2B與圖2C，沿著第二半導體元件160之間的間隙G2切割第二封裝膠體170與第一封裝膠體140，以形成多個晶片封裝單元C2。接著，在本實施例中，可在一線路基板180上形成一底膠190。
接著，請同時參照圖2C與圖2D，在本實施例中，可將晶片封裝單元C2配置於線路基板180上，以使第一半導體元件130透過導電凸塊132電性與結構性連接線路基板180，並使底膠190位於晶片封裝單元C2的第一半導體元件130與線路基板180之間以包覆第一半導體元件130的導電凸塊132。
請參照圖2D，在本實施例中，可在線路基板180上形成一第三封裝膠體220，第三封裝膠體220可覆蓋晶片封裝單元C2的側壁W1並暴露出第二半導體元件160的頂面166。此時，已初步完成本實施例之封裝結構200。此外，在其他未繪示的實施例中，第三封裝膠體220可覆蓋晶片封裝單元C2的側壁W1以及第二半導體元件160的頂面166。
以下將詳細介紹圖2D的封裝結構200的結構部分。
請參照圖2D，本實施例之封裝結構200與圖1I之封裝結構100相似，兩者的差異之處在於封裝結構200的第二封裝膠體210與第三封裝膠體220共同暴露出第二半導體元件160之的頂面166。因此，封裝結構200可透過第二半導體元件160的頂面166將第一半導體元件130與第二半導體元件160於運作時所產生的熱傳導至外界環境，進而提升封裝結構200的散熱效率。
綜上所述，本發明是先利用第一封裝膠體與第二封裝膠體來固定並連接第一半導體元件與第二半導體元件，之後再藉由切割第一封裝膠體與第二封裝膠體來形成多個晶片封裝單 元。因此，本發明可製得由各種尺寸的晶片相互堆疊而成的封裝結構。此外，由於第二封裝膠體可強化厚度相當小的晶片陣列板，故可穩固地連結全部的第二半導體元件以及全部的第一半導體元件，並可在以切割的方式形成晶片封裝單元的過程中，避免晶片陣列板碎裂，從而提升製程良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200‧‧‧封裝結構
110‧‧‧承載板
120‧‧‧黏著層
130‧‧‧第一半導體元件
132‧‧‧導電凸塊
134、142、164、172、W、W1‧‧‧側壁
136、144、166‧‧‧頂面
138‧‧‧開孔
140‧‧‧第一封裝膠體
150、190‧‧‧底膠
160‧‧‧第二半導體元件
162‧‧‧導電凸塊
168、182‧‧‧底面
170、210‧‧‧第二封裝膠體
180‧‧‧線路基板
220、M‧‧‧第三封裝膠體
A‧‧‧晶片陣列板
C1、C2‧‧‧晶片封裝單元
D‧‧‧導電材料
G1、G2‧‧‧間隙
I‧‧‧絕緣層
S‧‧‧銲球
T、T1、T2‧‧‧厚度
V‧‧‧直通矽晶穿孔結構
圖1A~圖1I繪示本發明一實施例之封裝製程的剖面圖。
圖2A~圖2D繪示本發明另一實施例之封裝製程的剖面圖。
100‧‧‧封裝結構
130‧‧‧第一半導體元件
132‧‧‧導電凸塊
134、142、164、172、W‧‧‧側壁
136、144、166‧‧‧頂面
140‧‧‧第一封裝膠體
150、190‧‧‧底膠
160‧‧‧第二半導體元件
162‧‧‧導電凸塊
168、182‧‧‧底面
170‧‧‧第二封裝膠體
180‧‧‧線路基板
C1‧‧‧晶片封裝單元
M‧‧‧第三封裝膠體
S‧‧‧銲球
T1、T2‧‧‧厚度
V‧‧‧直通矽晶穿孔結構

Claims (28)

  1. 一種封裝製程，包括：提供一承載板，該承載板上配置有一黏著層；將多個第一半導體元件配置於該黏著層上，且該些第一半導體元件彼此分離並分別透過該黏著層固定於該承載板上，其中各該第一半導體元件具有多個直通矽晶穿孔結構；於該承載板上形成一第一封裝膠體，該第一封裝膠體覆蓋該些第一半導體元件的側壁並填滿該些第一半導體元件之間的間隙，以使該些第一半導體元件與該第一封裝膠體形成一晶片陣列板；在形成該晶片陣列板之後，研磨該晶片陣列板，以薄化該晶片陣列板並露出各該第一半導體元件的該些直通矽晶穿孔結構的端面；將多個第二半導體元件分別覆晶接合至該些第一半導體元件上；於該晶片陣列板上形成一第二封裝膠體，該第二封裝膠體至少覆蓋該些第二半導體元件的側壁並填滿該些第二半導體元件之間的間隙；分離該晶片陣列板與該黏著層；以及沿著該些第二半導體元件之間的間隙切割該第二封裝膠體與該第一封裝膠體，以形成多個晶片封裝單元。
  2. 如申請專利範圍第1項所述之封裝製程，其中研磨該晶片陣列板的方法包括：研磨該晶片陣列板直到該晶片陣列板的厚度實質上小於或等於4密爾。
  3. 如申請專利範圍第1項所述之封裝製程，其中在將 該些第二半導體元件分別覆晶接合至該些第一半導體元件之後，該第二半導體元件於該承載板上的投影面積大於該第一半導體元件於該承載板上的投影面積。
  4. 如申請專利範圍第1項所述之封裝製程，更包括：在形成該晶片陣列板之後，在該些第一半導體元件上分別形成多個彼此分離的第一底膠，其中各該第一底膠覆蓋對應的該第一半導體元件以及該第一封裝膠體之圍繞對應的該第一半導體元件的部分，且在將該些第二半導體元件分別覆晶接合至該些第一半導體元件上時，各該第二半導體元件的多個導電凸塊通過對應的該第一底膠而與對應的該第一半導體元件接合。
  5. 如申請專利範圍第1項所述之封裝製程，其中該第二封裝膠體暴露出各該第二半導體元件之遠離對應的該第一半導體元件的一頂面。
  6. 如申請專利範圍第1項所述之封裝製程，其中該第二封裝膠體覆蓋各該第二半導體元件之遠離對應的該第一半導體元件的一頂面。
  7. 如申請專利範圍第1項所述之封裝製程，更包括：將該晶片封裝單元配置於一線路基板上，以使該第一半導體元件電性與結構性連接該線路基板。
  8. 如申請專利範圍第7項所述之封裝製程，更包括：在該線路基板上形成一第二底膠，以使該第二底膠位於該晶片封裝單元的該第一半導體元件與該線路基板之間並包覆該第一半導體元件的多個導電凸塊。
  9. 如申請專利範圍第7項所述之封裝製程，更包括：在該線路基板上形成一第三封裝膠體，該第三封裝膠體至 少覆蓋該晶片封裝單元的側壁。
  10. 如申請專利範圍第9項所述之封裝製程，其中該第二封裝膠體與該第三封裝膠體共同暴露出該晶片封裝單元的該第二半導體元件之遠離該第一半導體元件的一頂面。
  11. 如申請專利範圍第9項所述之封裝製程，其中該第三封裝膠體覆蓋該晶片封裝單元的該第二半導體元件之遠離該第一半導體元件的一頂面。
  12. 如申請專利範圍第7項所述之封裝製程，更包括：於該線路基板之遠離該晶片封裝單元的一底面上形成多個銲球，且該些銲球與該線路基板電性連接。
  13. 一種封裝結構，包括：一第一半導體元件，其中該第一半導體元件具有多個直通矽晶穿孔結構；一第一封裝膠體，包覆該第一半導體元件的側壁；一第二半導體元件，配置於該第一半導體元件與部分該第一封裝膠體上，且該第二半導體元件的尺寸大於該第一半導體元件的尺寸；以及一第二封裝膠體，至少覆蓋該第二半導體元件的側壁以及該第一封裝膠體，其中該第一封裝膠體與該第二封裝膠體為各自成型。
  14. 如申請專利範圍第13項所述之封裝結構，其中該第一封裝膠體的側壁切齊於該第二封裝膠體的側壁。
  15. 如申請專利範圍第13項所述之封裝結構，其中該第一封裝膠體之朝向該第二半導體元件的一第一頂面切齊於該第一半導體元件之朝向該第二半導體元件的一第二頂面。
  16. 如申請專利範圍第15項所述之封裝結構，其中該第 一封裝膠體的厚度實質上等於該第一半導體元件的厚度。
  17. 如申請專利範圍第13項所述之封裝結構，其中該第二半導體元件具有位於該第二半導體元件與該第一半導體元件之間的多個導電凸塊，且該封裝結構更包括：一底膠，配置於該第二半導體元件與該第一半導體元件之間以及該第二半導體元件與該第一封裝膠體之間，以包覆該第二半導體元件的該些導電凸塊。
  18. 如申請專利範圍第13項所述之封裝結構，其中該第一半導體元件的厚度實質上小於或等於4密爾。
  19. 如申請專利範圍第18項所述之封裝結構，其中該第一半導體元件的厚度實質上為2密爾。
  20. 如申請專利範圍第13項所述之封裝結構，其中該第二封裝膠體更覆蓋該第二半導體元件之遠離該第一半導體元件的一頂面。
  21. 如申請專利範圍第13項所述之封裝結構，其中該第二封裝膠體暴露出該第二半導體元件之遠離該第一半導體元件的一頂面。
  22. 如申請專利範圍第13項所述之封裝結構，其中該第一半導體元件之遠離該第二半導體元件的一底面上配置有多個導電凸塊。
  23. 如申請專利範圍第22項所述之封裝結構，更包括：一線路基板，該第一半導體元件配置於該線路基板上，且該些導電凸塊位於該第一半導體元件與該線路基板之間。
  24. 如申請專利範圍第23項所述之封裝結構，更包括：一底膠，配置於該第一半導體元件與該線路基板之間，以包覆該些導電凸塊。
  25. 如申請專利範圍第23項所述之封裝結構，更包括：一第三封裝膠體，配置於該線路基板上，並至少覆蓋該第一封裝膠體的側壁與該第二封裝膠體的側壁。
  26. 如申請專利範圍第25項所述之封裝結構，其中該第二封裝膠體與該第三封裝膠體暴露出該第二半導體元件之遠離該第一半導體元件的一頂面。
  27. 如申請專利範圍第25項所述之封裝結構，其中該第三封裝膠體覆蓋該第二半導體元件之遠離該第一半導體元件的一頂面。
  28. 如申請專利範圍第23項所述之封裝結構，更包括：多個銲球，配置於該線路基板之遠離該第一半導體元件的一底面上，並與該線路基板電性連接。
TW098133269A 2009-09-30 2009-09-30 封裝製程及封裝結構 TWI436470B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
TW098133269A TWI436470B (zh) 2009-09-30 2009-09-30 封裝製程及封裝結構
US12/711,870 US8618645B2 (en) 2009-09-30 2010-02-24 Package process and package structure
US14/087,454 US9698120B2 (en) 2009-09-30 2013-11-22 Package process and package structure
US15/620,692 US11222866B2 (en) 2009-09-30 2017-06-12 Package process and package structure
US17/573,593 US12266632B2 (en) 2009-09-30 2022-01-11 Package process and package structure
US19/097,838 US20250259967A1 (en) 2009-09-30 2025-04-01 Package process and package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW098133269A TWI436470B (zh) 2009-09-30 2009-09-30 封裝製程及封裝結構

Publications (2)

Publication Number Publication Date
TW201112385A TW201112385A (en) 2011-04-01
TWI436470B true TWI436470B (zh) 2014-05-01

Family

ID=43779370

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098133269A TWI436470B (zh) 2009-09-30 2009-09-30 封裝製程及封裝結構

Country Status (2)

Country Link
US (5) US8618645B2 (zh)
TW (1) TWI436470B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
DE102014219126A1 (de) * 2014-09-23 2016-03-24 Continental Automotive Gmbh Anordnung mit Schaltungsträger für ein elektronisches Gerät
US9461001B1 (en) * 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
KR102698658B1 (ko) 2016-06-02 2024-08-26 엠. 테크닉 가부시키가이샤 투명재용 자외선 및/또는 근적외선 차단제 조성물
US11152274B2 (en) * 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
TWI738007B (zh) * 2019-06-19 2021-09-01 力成科技股份有限公司 半導體封裝結構及其製造方法
US12046525B2 (en) 2020-11-27 2024-07-23 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12218090B2 (en) 2020-12-25 2025-02-04 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12154884B2 (en) 2021-02-01 2024-11-26 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12500203B2 (en) 2021-02-22 2025-12-16 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US11978729B2 (en) * 2021-07-08 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having warpage control and method of forming the same
US20240113073A1 (en) * 2022-09-29 2024-04-04 Intel Corporation Side of a die that is coplanar with a side of a molding

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102479A (ja) * 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6794273B2 (en) 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
JP4983049B2 (ja) * 2005-06-24 2012-07-25 セイコーエプソン株式会社 半導体装置および電子機器
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
JP2007317822A (ja) * 2006-05-25 2007-12-06 Sony Corp 基板処理方法及び半導体装置の製造方法
KR100809696B1 (ko) * 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7692278B2 (en) * 2006-12-20 2010-04-06 Intel Corporation Stacked-die packages with silicon vias and surface activated bonding
TWI344694B (en) * 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7982298B1 (en) * 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
JP5147755B2 (ja) * 2009-02-20 2013-02-20 新光電気工業株式会社 半導体装置及びその製造方法
US20100237481A1 (en) * 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8803332B2 (en) * 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US7867821B1 (en) * 2009-09-18 2011-01-11 Stats Chippac Ltd. Integrated circuit package system with through semiconductor vias and method of manufacture thereof

Also Published As

Publication number Publication date
US12266632B2 (en) 2025-04-01
TW201112385A (en) 2011-04-01
US20170278823A1 (en) 2017-09-28
US20110074004A1 (en) 2011-03-31
US8618645B2 (en) 2013-12-31
US20140087519A1 (en) 2014-03-27
US20250259967A1 (en) 2025-08-14
US20220157775A1 (en) 2022-05-19
US11222866B2 (en) 2022-01-11
US9698120B2 (en) 2017-07-04

Similar Documents

Publication Publication Date Title
TWI436470B (zh) 封裝製程及封裝結構
TWI628778B (zh) 半導體封裝結構及其形成方法
US8258007B2 (en) Package process
US8004079B2 (en) Chip package structure and manufacturing method thereof
US8446000B2 (en) Package structure and package process
US20100327465A1 (en) Package process and package structure
US20090127688A1 (en) Package-on-package with improved joint reliability
US20060220224A1 (en) Thermally Enhanced Three-Dimensional Package and Method for Manufacturing the Same
JP2005045251A (ja) スタック半導体チップｂｇａパッケージ及びその製造方法
JP2022025048A (ja) パッケージ構造及びその形成方法
TW200933766A (en) Integrated circuit package system with flip chip
TWI416700B (zh) 晶片堆疊封裝結構及其製造方法
US20080093733A1 (en) Chip package and manufacturing method thereof
KR20220150201A (ko) 2개의 링 사이에 리벳팅 구조물을 갖는 반도체 패키지 및 이를 형성하는 방법
JP2004281920A (ja) 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP2004281919A (ja) 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
CN102044447B (zh) 封装工艺及封装结构
CN112002679A (zh) 堆叠封装结构和堆叠封装方法
CN102543970A (zh) 半导体封装件及其制造方法
CN101958253A (zh) 封装工艺及封装结构
US8012800B2 (en) Method of fabricating a stacked type chip package structure and a stacked type package structure
TWI771242B (zh) 雙晶片半導體封裝及其製備方法
CN219677250U (zh) 一种集成式芯片封装结构和电子产品
CN105932017A (zh) 一种超薄3d封装的半导体器件、其加工方法以及加工方法中的半成品
US20240274505A1 (en) Electronic package and manufacturing method thereof