TWI424536B - Three dimensional nand memory and method of making thereof - Google Patents

Description

Three-dimensional anti-memory memory and manufacturing method thereof

The present invention relates generally to the field of semiconductor devices and, more particularly, to three-dimensional anti-strings and other three-dimensional devices.

The three-dimensional vertical inverse and string are disclosed in the article entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" by IEDM Proc (2001), pp. 33-36, T. Endoh et al. However, this inverse string provides only one bit per cell. In addition, the area of action of the anti-string is formed by a relatively difficult and time consuming process involving repeated formation of sidewall spacers and portions of the substrate, which results in a generally conical shaped region shape.

According to an embodiment of the invention, a single, three-dimensional inverse and string comprises a first memory unit located above a second memory unit. The semiconductor active region of the first memory cell is epitaxially formed on the semiconductor active region of the second memory cell such that there is a semiconductor active region of the first memory cell and a semiconductor active region of the second memory cell The defined boundary.

According to another embodiment of the present invention, a cell, a three-dimensional inverse and a string comprise at least one first memory cell located above the second memory cell, wherein at least the semiconductor active region of the first memory cell comprises recrystallized Polycrystalline germanium.

According to another embodiment of the present invention, a single, three-dimensional inverse and string inclusion At least one first memory cell located above the second memory cell, wherein at least one region of the inverted string is planarized.

Embodiments of the present invention will be described below with reference to the accompanying drawings. The following description is intended to describe the exemplary embodiments of the invention, and is not intended to limit the invention.

Embodiments of the present invention provide a single, three-dimensional array of memory devices, such as an array of vertical and vertical strings. In contrast, the strings are oriented vertically such that at least one memory cell is located above another memory cell. The array allows vertical scaling of the device to provide a higher density of memory cells per unit area of germanium or other semiconductor material. This non-volatile memory in each of the preferred memory hierarchy comprising two charge collection memory unit (such as, SONOS units) per 4F ^2. Thus, a four-memory cell level configuration would have an area of 0.5 F ² per cell or a binary bit of 0.5 F ² per cell. An array can have two or more cell levels, such as two to eight levels. Therefore, the N memory cell level configuration will have an area of 4F ² /2N per cell. If necessary, each of the counter-selected transistors may also be individually integrated into each of the anti-strings above and/or below the memory cells.

A monolithic three dimensional memory array is an array of multiple memory levels formed over a single substrate, such as a semiconductor wafer (without an intervening substrate). The term "monomer" means that the layers of each level of the array are deposited directly on the layers of each of the underlying layers of the array. Instead, a two-dimensional array can be formed separately and then packaged together to form a non-single memory device. For example, the US special titled "Three Dimensional Structure Memory" in Leedy. In U.S. Patent No. 5,915,167, a memory of a non-monomer stack has been constructed by forming a memory level on a separate substrate and overlapping the memory levels. The substrate can be thinned or removed from the memory level prior to bonding, but since the memory levels are initially formed over a separate substrate, such memory is not a true single-element three-dimensional memory array.

The preferred stylization and erasure method for the inverse string is tunneling via Fowler-Nordheim ("FN"). Multi-level cell ("MLC") operations of various V _T state types or Saifon/mirror bit types are also possible.

Thus, the array contains two bits per 4F ² in each memory level and further provides scaling by vertically integrating multiple memory levels. Each charge collection memory unit can operate in a binary manner with large margins and high performance. Further efficiency is provided by the fact that the selectable transistors can be vertically integrated and one or possibly two select transistors can be omitted altogether. Selecting the vertical integration of the transistors eliminates any breaks in the regular lines and spatial patterns of the mask for each device level. There is no rule of the entire memory array and a complete periodic line and space continuity break, thereby allowing for small device features with narrow spacing formed by lithography. In contrast to prior art two-dimensional flat reversal devices, there is no need to create additional space for the end of the crossover and space.

Alternative embodiments include configurations having select gates formed in trenches in germanium wafers or other substrates, without the configuration of select gates (ie, no select gate lines and no select transistors), The configuration with only the gate bucker selection has only the configuration of the selected gate source and the configuration with both selector gates. Selecting the gate line with respect to the orientation of the source line, the bit line, and the word line Orientation can be changed in various configurations. As will be described below, even non-orthogonal orientations of the various lines with respect to each other are also possible. In some embodiments, the source lines can be replaced by a common source region that extends in two dimensions of the plane of the substrate and provides higher current draw capability at the expense of the inability to select individual source line voltages. It is also possible to change the orientation of the memory levels with respect to each other. For example, each memory level can have a word line oriented in a vertical direction with respect to the upper level and the lower level.

1A and 1B illustrate a first step in the method of fabricating the inverse string according to the first embodiment of the present invention. 1A is a plan view and FIG. 1B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 1A. Figure 1B illustrates a P-type germanium substrate 1 containing an n-type germanium layer 3 adjacent to the surface. It should be noted that the p-type and n-type regions may be reversed and a semiconductor material such as gallium arsenide other than germanium may be used. The substrate 1 and the layer 3 preferably comprise a single crystal germanium. Layer 3 can be formed by blanket ion implantation or epitaxial growth of an n-type layer on a P-type substrate. The active area and the layer 3 in the substrate 1 are separated from each other by the insulating isolation region 7. Any suitable isolation region 7, such as a LOCOS yttria or STI oxide filled trench, can be used. Preferably, the pn junction between substrate 1 and layer 3 is above the bottom of isolation region 7 (such as above the bottom of the STI trench) to enable the voltage of each active device to be independent of the other devices. The germanium layer 3 can be patterned by etching and etching a standard STI trench, performing thermal or radical inner wall isolation layer oxidation, depositing a trench fill oxide, and by any suitable planarization method such as chemical mechanical polishing (CMP). The top is planarized with a fill oxide to form an STI isolation region 7.

2A and 2B illustrate a second step in the method of making the inverse string. Figure 2A is a top view and FIG. 2B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 2A. As shown in FIG. 2B, the germanium layer 9 is epitaxially grown on the active region 5 exposed between the isolation regions 7. The active region 5 acts as a seed for the epitaxial growth of layer 9. Therefore, the grain boundary 11 in the layer 9 is formed above the isolation region 7, and in the layer 9, essentially a single crystal germanium region is formed above the active region 5.

Layer 9 contains a p-type region 15 between n-type regions 13 and 17. Layer 9 can be doped in situ by varying the dopant concentration in the precursor gas during growth. This situation forms an npn structure 13, 15, 17 that will later define the source/channel/drain regions of the vertical sidewall MOS select transistor. Other forms of ion implantation or doping of the various layers 13 to 17 are also possible but result in a more complex process flow. The n-type region 13 is in electrical contact and the n-type active region 5 in the physical contact layer 3.

3A and 3B illustrate a third step in the method of making the inverse string. 3A is a top view and FIG. 3B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 3A. As shown in Figure 3B, the epitaxial layer 9 is planarized by any suitable planarization method, such as CMP, to provide a flat upper surface.

4A and 4B illustrate a fourth step in the method of making the inverse string. 4A is a plan view and FIG. 4B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 4A. The epitaxial layer 9 is patterned into stripes 19. As used herein, the term "stripes" refers to a body having a length that is much greater than the thickness or width and that extends in one direction along the length. As will be described in more detail below, the stripes 19 in the first embodiment extend in the direction of the bit line.

The stripes 19 are formed by forming a mask over the layer 9, such as a photolithographically patterned photoresist layer, and etching portions of the layer 94 that are unmasked. Figure 5A As shown in Figure 5B, the patterning of the stripes is not necessarily automatically aligned with the active area 5 below. Preferably, but not necessarily, the strips 19 are not aligned with the active area 5 such that the strips 19 extend laterally across the active area 5 and over the isolation area 7 (as shown in Figure 5B), and/or such that the active area 5 Portions are exposed below the stripes 19 (as shown in Figure 5A).

5A and 5B illustrate a fifth step in the method of making the inverse string. 5A is a top view and FIG. 5B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 4A.

As shown in FIGS. 5A and 5B, an insulating layer such as hafnium oxide and/or another insulating layer 21 is deposited between the stripes and planarized with respect to the top surface of the stripes 19. The insulating layer 21 can be planarized by CMP or other planarization methods such as etch back.

6A to 6D illustrate a sixth step in the method of making the inverse string. 6A is a plan view and FIG. 6B is a side cross-sectional view taken along line A-A extending parallel to the word line in FIG. 6A. Figure 6C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 6A. Figure 6D is a three dimensional view of the apparatus of manufacture shown in Figures 6A-6C.

The stripe 19 and a portion of the insulating layer 21 between the strips 19 are planarized into stripes 23 extending parallel to the word line direction and perpendicular to the strips 19. The stripes 23 are formed by forming a mask (such as a photolithographic patterned photoresist layer) over the stripes 19 and the insulating layer 21 and etching the unmasked portions of the stripes 19 and 21.

The stripes 23 are composed of semiconductor pillars 25 which are spaced apart from adjacent pillars by portions of the insulating layer 21 in the word line direction. Each The pillars 25 are spaced apart from the adjacent pillars by the grooves 27 between the pillars in the direction of the bit line. Each of the pillars 25 contains a p-type conductivity semiconductor region 15 between the n-type conductivity type semiconductor regions 13, 17 in the vertical direction (i.e., with respect to the substrate 1, the region 15 is above the region 13 and in the region 17 below).

Preferably, as shown in Figure 6A, each pillar 25 has a square or rectangular cross section when viewed from the top. Thus, each pillar 25 preferably has four vertical sides.

7A to 7C illustrate the seventh step in the method of making the inverse string. 7A is a plan view and FIG. 7B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 7A. Figure 7C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 7A.

As shown in FIG. 7C, a gate insulating layer 29 is formed in the trench 27 between the pillars 25 and formed over the top surface of the pillars 25. The gate insulating layer 29 may comprise hafnium oxide, tantalum nitride or any other suitable gate insulating material. Layer 29 may contain two or more sub-layers having different compositions, if desired.

A select gate layer is then deposited over the gate insulating layer 29. One or more of any suitable gate electrode materials may be used for the select gate layer, such as polysilicon, telluride (titanium telluride, etc.), tungsten, aluminum, or a combination of sublayers of such materials.

The select gate layer is then planarized with respect to the top of the gate insulating layer 29 by any suitable planarization method such as CMP. As shown in FIG. 7C, planarization leaves a select gate in a portion of the trench 27 above the gate insulating layer 29. Extreme 31.

8A to 8C illustrate an eighth step in the method of making the inverse string. 8A is a plan view and FIG. 8B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 8A. Figure 8C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 8A.

As shown in FIG. 8C, the select gate 31 is partially etched back such that the top of the select gate is below the top of the pillar 25. The selective etching of the gate material can be selectively etched over the material of the gate insulating layer 29 to etch the gate 31.

9A through 9C illustrate the ninth step in the method of making the inverse and string. 9A is a plan view and FIG. 9B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 9A. Figure 9C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 9A.

An insulating cap layer is deposited over the recessed select gate 31 and over the gate insulating layer 29. Preferably, the cap layer comprises the same material as the gate insulating layer 29, such as hafnium oxide. The cap layer is then planarized (such as CMP planarization) to fill the trench above the select gate 31 and form an insulating cap 33 over each of the select gates 31. The top cover 33 electrically isolates the select gate from the reverse memory memory cell that will be formed above. During planarization of the cap layer, portions of the gate insulating layer 29 over the semiconductor pillars 25 are also removed to expose the top region 17 of the pillars 25.

As shown in FIG. 9A, the select gate 31 includes a portion of the select gate line that extends in the direction of the word line. Thus, the select gate line includes a stripe line located in the trench 97 (shown in Figure 6A). Each selection gate 31 charge When used for the gate electrodes of two adjacent selection transistors 35 on the left and right sides of the gate 31 in FIG. 7C.

Therefore, the ninth step completes the selection of the transistor 35 for the bottom of the string. Each selected field effect transistor 35 includes a region of action of the pillars 25 (where region 15 acts as a channel and regions 13 and 17 act as "source" and "dip" regions), acting as a gate of the gate electrode of the transistor 31 and a gate insulating layer 29 between the selection gate 31 and the pillars 25. Since each pillar 25 is located between two different selection gates 31, the left and right sides of each pillar 25 can be viewed as independent selection of the same inverse and string to be formed above the pillars 25. Transistor 35.

10A through 10C illustrate the tenth step in the method of making the inverse string. 10A is a plan view and FIG. 10B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 10A. Figure 10C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 10A.

10A through 10C illustrate a first step of forming a memory cell over the selection transistor 35. First, the surface of the exposed pillars 25 is preferably cleaned after the CMP step in Figure 9C. For example, the top surface of each of the pillars can be treated by thermal oxidation or radical oxidation (ie, to form a layer of tantalum oxide on top of the pillars), followed by wetting, smoothing the oxide Etching to remove the oxide layer along with damage that occurs during CMP and/or dry etching to prepare the germanium surface for growth of the next epitaxial layer. This damage can affect the quality of subsequent epitaxial layer growth.

Next, as shown in FIGS. 10A through 10C, the next epitaxial layer 109 is grown on the completed selected gate transistor 35. Forming the first anti-memory list The subsequent steps of the element are similar to the method steps shown in Figures 2 through 9, except that instead of forming the charge storage region in place of the gate insulating layer 29.

As shown in FIGS. 10B and 10C, the ruthenium layer 109 is epitaxially grown on the pillar action region 25 exposed between the isolation regions formed by the insulating layers 21, 29 and 33. For example, plasma assisted epitaxy (i.e., PECVD) can be used to grow the germanium layer 109 at lower temperatures, such as at 700 ° C and below, such as at about 650 ° C. Although higher temperature growth treatments can be used, low temperature PECVD treatments allow the use of lower thermal budget metals and dielectrics (ie, metals and dielectrics that cannot withstand temperatures above 700 ° C4) and provide greater control Joint depth and channel length.

The exposed box-shaped upper surface of the pillar action region 25 serves as a seed crystal for the epitaxial growth layer 109. Therefore, the grain boundary 111 in the layer 109 is formed over the isolation region 7, and the substantially single crystal germanium region in the layer 109 is formed over the active region 25. The grain growth of layer 109 rapidly increases from the underlying seed crystal 25 and forms a grain boundary 111 where the grains meet each other during the epitaxial processing. Thus, the location of the grain boundaries 111 will be where random grains meet and the grain boundaries 111 will generally not be as smooth and predictable as schematically illustrated in Figures 10A-10C. However, the grain boundaries are located in the regions that will be etched away during subsequent steps. Therefore, high levels of smoothness and predictability are not required.

Layer 109 contains a p-type region 115 between the n-type regions 113 and 117 in the vertical direction. Layer 109 may be doped in situ by varying the dopant concentration in the precursor gas during growth. This situation forms an npn structure 113, 115, 117 that will later define the source/channel/drain regions of the charge collection MOS memory device (i.e., opposite to the memory cells). Ion implantation or doping various Other forms of layers 113 through 117 are also possible but result in a more complex process flow. The n-type region 113 is in electrical contact and physically contacts the n-type active region 17 in the pillar 25.

11A through 11C illustrate an eleventh step in the method of making the inverse string. Figure 11A is a plan view and Figure 11B is a side cross-sectional view along line A-A extending parallel to the word line in Figure 11A. Figure 11C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 11A.

As shown in Figures 11B and 11C, the epitaxial layer 109 is planarized by any suitable planarization method, such as CMP, to provide a flat upper surface.

Figures 12A through 12C illustrate the twelfth step in the method of making the inverse and string. Figure 12A is a plan view and Figure 12B is a side cross-sectional view along line A-A extending parallel to the word line in Figure 12A. Figure 12C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 12A.

The epitaxial layer 109 is patterned into stripes 119. As used herein, the term "stripes" refers to a body having a length that is much greater than the thickness or width and that extends in one direction along the length. As will be described in more detail below, the stripes 119 in the first embodiment extend in the direction of the bit line.

The stripes 119 are formed by forming a mask over the layer 109, such as a photolithographic patterned photoresist layer, and etching the unmasked portions of the layer 109. As shown in Figures 12A-12C, the patterning of the stripes is not necessarily automatically aligned with the lower pillar action region 25. Preferably, but not necessarily, the strips 119 are not aligned with the active region 25 such that the strips 119 extend laterally across the active region 25 and over the isolation regions formed by the layers 21, 29 and 33 surrounding the pillars 25 (Fig. 12B). And shown in 12C), and/or to enable the active area 25 Portions are exposed below the stripes 119 (as shown in Figure 12A).

13A to 13C illustrate the thirteenth step in the method of making the inverse and the string. Figure 13A is a plan view and Figure 13B is a side cross-sectional view along line A-A extending parallel to the word line in Figure 13A. Figure 13C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 13A.

As shown in FIGS. 13A through 13B, an insulating layer such as hafnium oxide and another insulating layer 121 are deposited between the strips 119 adjacent to the exposed lateral sides of the strips 119. The layer 121 is then planarized with respect to the top surface of the stripes 119. The insulating layer 121 may be planarized by CMP or other planarization methods such as etch back.

14A through 14C illustrate the fourteenth step in the method of making the inverse and string. 14A is a plan view and FIG. 14B is a side cross-sectional view taken along line A-A extending parallel to the word line in FIG. 14A. Figure 14C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 14A.

Portions of the insulating layer 121 between the stripes 119 and the stripes 119 are patterned into stripes 123 extending parallel to the word line direction and perpendicular to the stripes 119. The stripes 123 are formed by forming a mask (such as a photolithographic patterned photoresist layer) over the stripes 119 and the insulating layer 121 and etching the unmasked portions of the stripes 119 and 121.

The stripe 123 is composed of a semiconductor pillar 125 which is spaced apart from the adjacent pillar by a portion of the insulating layer 121 in the word line direction. Each of the pillars 125 is spaced apart from the adjacent pillars by a groove 127 between the pillars in the direction of the bit line. Each of the pillars 125 includes a p-type conductivity semiconductor located between the n-type conductivity type semiconductor regions 113, 117 in the vertical direction Region 115 (i.e., region 115 is above region 113 and below region 117 with respect to substrate 1).

Preferably, as shown in Figure 14A, each pillar 125 has a square or rectangular cross section when viewed from the top. Therefore, each pillar 125 preferably has four vertical sides.

15A through 15C illustrate the fifteenth step in the method of making the inverse and string. 15A is a plan view and FIG. 15B is a side cross-sectional view along line A-A extending parallel to the word line in FIG. 15A. Figure 15C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 15A.

As shown in FIGS. 15A through 15C, a charge storage region is formed between the stripes 123. The charge storage region may comprise a dielectrically isolated floating gate or dielectric charge storage material. For example, to form a dielectric isolation floating gate, a polysilicon layer is deposited between two insulating layers such as yttria tunneling and a barrier layer. For example, a floating gate formed by a sidewall spacer can be used. The extra space occupied by the spacer float can be compensated for by programming the multi-level cell (MLC) for such devices.

To form a dielectric charge storage region, a charge storage dielectric layer is deposited between the tunneling and barrier dielectric (ie, insulating) layers. For example, the charge storage dielectric layer can comprise a tantalum nitride layer, and the tunneling and barrier layers can comprise a hafnium oxide layer to form an "ONO" charge storage region of a "SONOS" type device. Preferably, the tunneling dielectric layer is thinner than the blocking dielectric layer.

However, materials other than tantalum nitride and hafnium oxide may alternatively be used. For example, a TANOS type device can be used. As disclosed in U.S. Patent No. 6,858,899, the disclosure of which is incorporated herein by reference in its entirety A high dielectric constant insulating material of a material having a dielectric constant of 3.9 can be used in place of yttrium oxide for tunneling and/or blocking a dielectric layer. Such materials include metal oxide layers such as alumina, yttria, yttria, calcium oxide, magnesia or zirconia. The charge storage dielectric may alternatively comprise a layer of ruthenium oxynitride wherein a portion of the nitrogen in the tantalum nitride layer is replaced by oxygen. Alternatively, a metal oxide layer such as yttria, zirconia or yttria can be used as the charge storage dielectric.

In the following discussion, an ONO charge storage region will be described. However, it should be understood that a floating gate charge storage region or other combination of dielectric charge storage materials may alternatively be used.

As shown in FIGS. 15A and 15C, the tunnel dielectric layer 128, the charge storage dielectric layer 129, and the barrier dielectric layer 130 are formed in this order between the pillars 125 (ie, adjacent to the pillars). The exposed side of the trench 127 is above the top surface of the pillar 125. The tunneling and blocking dielectrics may comprise yttrium oxide, and the charge storage dielectric may comprise tantalum nitride.

A control gate layer is then deposited over the dielectric layers 128-130. One or more of any suitable gate electrode materials can be used for the control gate layer, such as polysilicon, germanide (titanium telluride, etc.), tungsten, aluminum, or a combination of sub-layers of such materials.

The control gate layer is then planarized with respect to the top of the tunneling layer 128 by any suitable planarization method, such as CMP. The planarization leaves the control gate 131 in a portion of the trench 127 above the dielectric layers 128-130.

The control gate 131 is partially etched back such that the top of the gate is below the top of the pillar 125. Selective etching of the gate material can be selectively etched over the ONO dielectric layers 128-130 to etch the gate 131.

An insulating cap layer is then deposited over the recessed control gate 131 and over the ONO dielectric. Preferably, the cap layer comprises the same material as the material of the barrier dielectric 130, such as yttrium oxide. The cap layer is then planarized (such as CMP planarization) to fill the trenches above the control gate 131 and form an insulating cap 133 over each of the select gates 131. The top cover 133 electrically isolates the control gate from the additional reverse string memory cells that will be formed above. During planarization of the cap layer, portions of the ONO dielectric layers 128-130 above the semiconductor pillars 125 are also removed to expose the top regions 117 of the pillars 125.

As shown in FIG. 15A, the control gate 131 includes a portion of a word line extending below the top cover 133 in the direction of the word line. Therefore, the word gate line includes stripe lines located in the trench 127. Each of the control gates 131 serves as a gate electrode for two adjacent memory cells 135 on the left and right sides of the gate 131 in FIG. 15C.

This situation is used to complete the memory unit 135 at the bottom of the string. Each memory cell 135 includes a region of action of the pillars 125 (where region 115 acts as a channel and regions 113 and 117 act as "source" and "dip" regions), acting as a gate electrode for the gate electrode of the transistor / Word line 131 and a charge storage region such as ONO dielectric layers 128-130 between control gate 131 and pillar 125. Since each pillar 125 is located between two different control gates 131, the left and right sides of each pillar 125 can be considered a memory unit.

Figure 16 illustrates a side cross-sectional view along the direction of the completed vertical and the bit line of the string. The second level of the memory unit 235, which is identical to the first memory unit 135, is repeated by repeating the processing steps described above with respect to Figures 10-15. The first memory unit 135 is formed to form a multi-level vertical reverse string. Additional levels of memory cells (such as two or six levels of memory cells) may be formed over the first level of memory cell 135 by repeating the processing steps described above as necessary. A plurality of bit lines 137 are then formed over the uppermost level of the memory cell. The bit line 137 contacts the pillar action area of the upper level of the memory cell. For example, the single bit line 137 shown in FIG. 16 extends perpendicular to the word lines 131, 231 of the memory cell. However, as will be described in greater detail below, bit line 137 can extend in other directions.

Further, if necessary, the upper selection transistor may be above the upper level of the memory cell below the bit line 137, using the same method as the lower selection of the gate transistor 35. An upper selection transistor is formed in addition to or instead of the lower selection gate transistor 35.

Thus, Figure 16 illustrates a vertical inverse string 100 formed vertically above the substrate. One memory unit 235 is located in the upper device level and the other memory unit 135 is located in the lower device level, the lower device level being above the substrate and below the first device level 235. Because the active regions 125 and 225 are grown in different epitaxial growth steps, there is a defined boundary between the semiconductor active regions 125 and 225. The boundary may include dislocations, grain boundaries, or lateral offsets with respect to the pillars 225 of the pillars 125 at the boundaries. In contrast, the vertical of the prior art described in IEDM Proc (2001), pages 33 to 36, T. Endoh et al., entitled ''Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell') And the string is caused by a plurality of etches in the same region of the substrate Formed by engraving steps.

Further, the cylindrical action regions of the vertical and string memory cells fabricated by the method described above have a square or rectangular cross section when viewed from the top. This scenario provides a separate face for each word line in each cell and allows two bits per cell configuration. The cylindrical action region is formed by patterning the active layer into stripes and then patterning the stripes into pillars. In contrast, the area of action of Endoh et al. has a circular cross section when viewed from the top. The active area is surrounded by a gate around one of the bits for each unit configuration.

The semiconductor active region 25 of the selected transistor 35 comprises a pillar. The semiconductor active region 125 of the lower memory cell includes pillars that are not aligned with the semiconductor active region 25 of the select transistor 35. In the non-limiting embodiment shown in FIG. 16, the active region 125 extends laterally across the semiconductor active region 25 of the select transistor 35 in at least one direction. Similarly, the pillar action region 225 extends laterally across the pillar action region 125 of the unit 135 in at least one direction such that the pillars 125 are not aligned with the pillars 225.

The semiconductor active region of the memory cell 135 is a pillar 125 comprising a first conductivity type semiconductor region 115 between the second conductivity type semiconductor regions 113, 117. The semiconductor active region of the memory cell 235 is a pillar 225 comprising a first conductivity type semiconductor region 215 between the second conductivity type semiconductor regions 213, 217. The second conductivity type semiconductor region 213 in the pillar 225 contacts the second conductivity type semiconductor region 117 in the pillar 125.

As shown in FIG. 16, in the lower memory unit 135, the first charge The storage dielectric 129A is positioned adjacent to a side of the first conductivity type semiconductor region 115 in the pillar 125, and the first control gate 131A is positioned adjacent to the first charge storage dielectric 129A. The second charge storage dielectric 129B is positioned adjacent the opposite side of the first conductivity type semiconductor region 115 in the pillar 125, and the second control gate 131B is positioned adjacent to the second charge storage dielectric 129B. A similar configuration exists in the upper memory unit 235 in which two charge storage dielectrics and two control gates are located on opposite sides of the region 215 in the pillars 225.

Figures 17A and 17B illustrate side cross-sectional views of portions of a counter transistor selected in accordance with the present invention in place of the second and third embodiments.

Fig. 17A illustrates a side cross-sectional view along the direction of the word line of the second embodiment, in which the lower selection transistor 35 is omitted. In this case, a bottom memory cell level is formed over the substrate 1.

Figure 17B illustrates a side cross-sectional view along the direction of the bit line of the third embodiment in which the selection gate 31 of the selection transistor 35 is formed in the trench in the substrate 1. In this embodiment, the p-type substrate 1 contains npn structures 13, 15, 17 which are implanted between the implanted n-type regions 13 and 17 by implanting n-type ions into the substrate 1. The p-type region of the substrate 15 is formed. Alternatively, regions 13 through 17 may be formed by epitaxial layer growth and in-situ doping during growth. Next, the trench is formed by photolithography and etching of the p-type portion of the substrate 1 via the npn structure. The trench is filled with an insulating material 20 such as yttria. The insulating material 20 is then patterned by photolithography and etching to form additional trenches in the material 20. These additional trenches are filled with a select gate material that is then planarized to form select gates 31. If the selection of the transistor is omitted 35. Alternatively, the lowermost memory unit 135 is formed in the trench.

In place of the fourth embodiment, the pillar action regions 25, 125, etc., which select the transistor and/or the memory cell, are formed of polycrystalline semiconductor material 9, 109 or the like. Therefore, an amorphous, microcrystalline or polycrystalline semiconductor layer such as a tantalum layer is formed on the underlying pillar instead of forming the epitaxial semiconductor layers 9, 109 and the like on the underlying pillar. This amorphous, microcrystalline or polycrystalline semiconductor layer is then recrystallized to form a layer of large grain polycrystalline semiconductor material such as a large grain polycrystalline germanium layer. Recrystallization can be carried out by any suitable annealing method such as thermal annealing in a furnace, laser annealing, and/or flash lamp annealing. As described above, this recrystallized layer is then patterned into pillar action regions 25, 125, and the like. The use of low temperature deposition and recrystallization of polycrystalline germanium allows for the formation of active regions over metal connections or electrodes that cannot withstand high temperatures.

Therefore, the semiconductor active region of the upper memory cell can be epitaxially formed on the semiconductor active region of the underlying memory cell, or the semiconductor active region of the first memory cell can be formed in the recrystallized polysilicon. The active region of the lowermost level of the memory cell is epitaxially formed, or the active region of the lowermost layer of the memory cell is formed by recrystallization on the semiconductor active region of the selected transistor. The active region of the selective transistor is formed epitaxially, or the active region of the selective transistor is formed by recrystallization over the substrate.

The size of the memory array in the lateral dimension is limited by the RC time constant of the word line, the select gate line, the source line, and the bit line. In contrast, the strings are oriented vertically, and the channel regions (showing P region 115, NMOS memory embodiments) are not grounded. Therefore, care must be taken to manage this floating body potential. In phase An inversion layer on the (unselected) side can be established and used to facilitate anchoring the potential of the floating P-type body during various operations such as reading, programming, and/or erasing.

Highly doped N and P regions with steep junctions can also be used to enable the floating bodies to be more strongly coupled to one another via thinner depletion regions. Another way to indicate the potential of the floating body is to leak current through its junction.

In addition, the boost of program suppression should be more efficient. However, it is possible to drive the columnar action area as opposed to boosting, thereby allowing a steeper junction.

Each memory cell and selected transistor level is fully self-aligned with itself. In other words, no separate alignment steps are required between device levels. In addition, each device level requires only two lithography steps - a first step of forming a first strip 119 and a second step of forming a strip 123. The remaining features in each device level are formed by layer deposition and planarization. Thus, at least one region or layer of the string 100 and preferably a plurality of regions or layers are planarized by CMP and/or other methods. For example, for cell 135, when semiconductor active region 125 is in the form of epitaxial layer 109, it is planarized as shown in FIGS. 11B and 11C, such that inverse string 100 is inverted with at least one other neighbor. The string insulating insulating layer 121 is planarized as shown in FIG. 13B, and the charge storage dielectric 129, the control gate 131, and the cap layer 133 are planarized as shown in FIGS. 15B and 15C. Therefore, in each of the cells 135, 235, etc., at least five layers (the tunneling and the blocking dielectric are not calculated) are planarized by CMP.

If necessary, in all lithography steps, the wafer substrate 1 can be rotated 45 ∘ The wafer notch is not at 12 o'clock, but at 1:30. In this case, then the vertical sidewall channel will be on the [100] crystal plane, providing higher channel mobility.

Each device level is not automatically aligned with the level below it. However, since the areas where the levels meet are deliberately designed to oppose the non-active source/drain regions of the chain, this situation has almost no consequences. Based on the thermal budget of the annealing associated with the various levels, the vertical dimensions of each level and the location of the PN junctions in each level can be different from the other levels. Semiconductor epitaxial growth and plasma oxidation, such as low temperature PECVD growth (such as temperatures below 700), can be used to minimize layer-to-level variations. This situation also allows for a single high temperature anneal after all memory is formed and the gate level is selected. However, separate layer-by-layer annealing or multiple annealing steps for the memory/selection level can also be used. Annealing in a hydrogen atmosphere may also be performed as necessary.

As described above, the pillars are preferably rectangular or square when viewed from the side. However, when the sidewalls of the trench are not perpendicular, the active layer such as the selected cell pillar active region portion 5 will be in the form of a truncated pyramid having a rectangular or square bottom that is larger than the top. Thus, a certain amount of misalignment will not result in a change in the contact area of the top of one of the crests with the bottom of the crest of the layer above it.

Figure 18A illustrates a circuit schematic of the array of inverse and string described above. Figure 18B illustrates a portion of the circuit diagram of Figure 18A, but with the source lines, select lines, and word lines removed for clarity. 18A and 18B illustrate at least two levels of select transistor 35 in a trench on a substrate or in a substrate and a memory cell located vertically above the select transistor 35. Each reverse string It is depicted as a single row in which each level of the memory cell is above the level of the cladding below the memory cell. For example, the intermediate vertical inverse string 100 controlled by the bit line 237 in row M includes a select transistor 35 and four memory cells 135, 235, 345, and 445 located in four levels. The selection transistor 35 is connected to the source line SL in the column N+1/2. Select transistor 35 is controlled by select gate line 31 of columns N and N+1. The lowermost memory unit 135 is composed of the word lines 131 in columns N and N+1 in the vertical level 1 (shown as WL (N+X columns, Z level) in FIG. 18A, such as for column N, level 1 The word line in the middle is WL (N, 1)) control. The other memory cells 235, 335, and 445 are controlled by word lines 231, 331, and 441 in columns N and N+1 of levels 2, 3, and 4, respectively. The upper memory unit 445 is electrically connected to the bit line 237 in the bit line row M.

Therefore, each of the vertical inverse strings includes the selection transistor 35 and the memory cells 135 to 445 are vertically disposed, and the memory cells are positioned in an overlapping manner. The word lines 131 to 431 are not parallel to the bit line 237. For example, the word line extends perpendicular to the bit line 237. However, word lines 131 through 431 extend parallel to at least one of source line 239 and select gate line 31, such as parallel to source line 239 and select gate line 31.

In an alternate embodiment, the word lines in different vertical levels may extend in different directions from each other. For example, the word line 131 in the memory cell level one may extend in a different direction (such as in the vertical direction) than the direction of the word line 231 in the memory cell level two. The word line direction can alternate between each memory cell level. For example, the word lines in levels one and three extend in one direction and the word lines in levels two and four extend in different directions. The word line directions may differ from one to ninety degrees. This configuration can be Placing the charge storage locations adjacent to different faces of the column active regions adjacent to the memory cell levels reduces coupling between device levels (for example, charges are adjacent to the north side of the pillars in levels one and three and Stored in the south and stored in the second and fourth levels adjacent to the east and west.)

In another alternative embodiment shown in Figure 19, the bit lines, word lines, and source lines are not parallel to each other. In other words, the bit line 237 is not parallel to the word lines 131 to 431, the word lines 131 to 431 are not parallel to the source line 239, and the source line 239 is not parallel to the bit line. For example, as shown in FIG. 19, word lines 131 through 431 may extend perpendicular to source line 239, while bit line 237 is diagonally opposite the word line and source line (ie, from 1 to 89 degrees) The angle, such as 30 to 60 degrees, for example 45 degrees, extends. This situation allows simultaneous programming of different multi-state V _T levels to one group memory on the same word line by increasing the source and bit lines of each of the inverted strings to provide various effective stylized/suppressed voltages. Body unit. The current from each bit line is drawn to the individually selected source line, thus reducing the amount of current supplied to a particular source line. The diagonal bit line of Figure 19 can have a narrower pitch than the bit line shown in Figures 18A and 18B.

If necessary, the configuration can be changed such that the word lines and the bit lines are perpendicular to each other and the source lines are diagonal. A source line can be formed at the top and a bit line can be formed at the bottom. This situation allows for the formation of metal and/or germanide rather than semiconductor source lines, which results in reduced current crowding due to lower resistivity source line materials. If necessary, all three types of wires may be non-perpendicular to each other and extend diagonally relative to each other. Preferably, the selection line is parallel to the word line.

As shown in Figure 19, each memory cell has all of its The memory cell has different combinations of word lines, bit lines, and source lines. For example, all of the memory cells in one column parallel to the word line direction are controlled by different bit lines and different source lines. The configuration of Figure 19 allows each memory cell in the array to be individually programmed (alternatively stylized together with each pair of adjacent cells) even when two adjacent cells share the same word line, since such neighboring cells are connected to A combination of bit lines and source lines that are different from each other. For example, two adjacent cells in the same row parallel to a source line are controlled by different bit lines. Thus, two adjacent cells in the same row are associated with the same word line and source line but different bit lines. The selection of the transistor 31 can be omitted as necessary in the configuration of Fig. 19, if necessary, due to the ability to individually program each memory cell using bit-by-bit line control for the stylized unit. However, it is preferred to program in each of the inverse strings 200 step by step, wherein the alternating levels are sequentially programmed.

In another alternative embodiment, the source line 239 may be replaced by a common source region (source plane) that extends in two dimensions of the plane of the substrate 1 (i.e., in the x-y plane). The common source region may comprise a common conductive plate in electrical contact with the pillar active regions 25 of all of the select transistors 35 of the array, such as highly doped single or polycrystalline semiconductors, germanium and/or metal plates. If the selection of the transistor is omitted, the source plate contacts the pillar 125 of the lowest memory unit 135 level. The common source plate provides higher current draw capability at the expense of the ability to relax the selection of individual source line voltages.

An alternate embodiment for MLC operation has source lines and bit lines extending in the same direction to provide for changing the entire anti-chain voltage on a bitwise basis so that the programmatic ratio is being programmed into a lower V _T state The unit is faster being programmed into a higher V _T state unit. The source line and bit line voltages of the unit being programmed into a lower V _T state will be increased to delay stylizing some of these units so that less stylized pulses will be used to program the 2D or 3D configuration The state of the entire collection.

The previous description of the embodiments of the present invention has been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. The present invention has been selected and described in order to explain the principles of the invention and the embodiments of the invention. Intended by The scope of the invention is defined by the scope of the claims and the equivalents thereof.

1‧‧‧p type copper substrate

3‧‧‧n type layer

5‧‧‧Action area

7‧‧‧Insulated isolation area/STI isolation area

9‧‧‧矽

11‧‧‧ grain boundaries

13‧‧‧n-type area/npn structure

15‧‧‧p-type area/npn structure

17‧‧‧n-type area/npn structure

19‧‧‧ stripes

20‧‧‧Insulation materials

21‧‧‧Insulation

23‧‧‧ Stripes

25‧‧‧Semiconductor column

27‧‧‧Ditch

29‧‧‧ gate insulation

31‧‧‧Selecting the gate

33‧‧‧Insulated top cover

35‧‧‧Selecting a crystal

100‧‧‧反反串

109‧‧‧ epitaxial layer

111‧‧‧ grain boundaries

113‧‧‧n-type area/npn structure

115‧‧‧p-type area/npn structure

117‧‧‧n type area/npn structure

119‧‧‧ stripes

121‧‧‧Insulation

123‧‧‧ stripes

125‧‧‧Semiconductor pillar/semiconductor active region

127‧‧‧Ditch

128‧‧‧Tunnel dielectric layer

129‧‧‧Charge storage dielectric layer

129A‧‧‧First charge storage dielectric

129B‧‧‧Second charge storage dielectric

130‧‧‧Resisting dielectric layer

131‧‧‧Control gate/word line

131A‧‧‧First Control Gate

131B‧‧‧second control gate

133‧‧‧Top cover/insulated cover

135‧‧‧First memory unit

200‧‧‧Anti-string

213‧‧‧Second conductive type semiconductor region

215‧‧‧First Conductive Type Semiconductor Region

217‧‧‧Second conductive type semiconductor region

225‧‧‧Semiconductor active area/column

231‧‧‧ word line

235‧‧‧ memory unit

237‧‧‧ bit line

239‧‧‧ source line

331‧‧‧ word line

335‧‧‧ memory unit

431‧‧‧ word line

1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A and 15A are plan views of steps of fabricating a device according to a first embodiment of the present invention.

1B, 2B, 3B, 4B, 5B, 6B, 6C, 7B, 7C, 8B, 8C, 9B, 9C, 10B, 10C, 11B, 11C, 12B, 12C, 13B, 13C, 14B, 14C, 15B and 15C A side cross-sectional view of the steps of making a device in accordance with a first embodiment of the present invention. Figure 6D is a three dimensional view of the apparatus of manufacture shown in Figure 6A.

Figure 16 is a side cross-sectional view showing the direction of the completed vertical line and the bit line of the string in the first embodiment of the present invention.

17A and 17B are side cross-sectional views showing portions of an anti-string access transistor in accordance with a second embodiment and a third embodiment of the present invention.

18A and 19 are schematic diagrams showing the circuit of the inverse and the string of the embodiment of the present invention. Figure 18B illustrates a portion of the circuit diagram of Figure 18A, but with the source lines, select lines, and word lines removed for clarity.

5‧‧‧Action area

13‧‧‧n-type area/npn structure

15‧‧‧p-type area/npn structure

17‧‧‧n-type area/npn structure

25‧‧‧Semiconductor column

31‧‧‧Selecting the gate

35‧‧‧Selecting a crystal

100‧‧‧反反串

113‧‧‧n-type area/npn structure

115‧‧‧p-type area/npn structure

117‧‧‧n type area/npn structure

125‧‧‧Semiconductor pillar/semiconductor active region

129A‧‧‧First charge storage dielectric

129B‧‧‧Second charge storage dielectric

131A‧‧‧First Control Gate

131B‧‧‧second control gate

135‧‧‧First memory unit

213‧‧‧Second conductive type semiconductor region

215‧‧‧First Conductive Type Semiconductor Region

217‧‧‧Second conductive type semiconductor region

225‧‧‧Semiconductor active area/column

231‧‧‧ word line

235‧‧‧ memory unit

237‧‧‧ bit line

Claims (18)

a three-dimensional inverse string comprising at least one first memory cell located above a second memory cell, wherein a semiconductor active region of the first memory cell is epitaxially formed in one of the second memory cells The active region is such that there is a defined boundary between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell. In the reverse of the request item 1, wherein: the reverse string is formed vertically above a substrate; the first memory unit is located in a first device level; and the second memory unit is located above the substrate And in the second device level below the first device level. The reverse string of claim 1 further includes a selection transistor under the second memory unit. The inverse of the string of claim 3, wherein: the selection transistor is located on a substrate or a trench in the substrate; and the semiconductor active region of the second memory cell is epitaxially formed on the selective transistor One of the semiconductor action areas. The inverse of the request item 4, wherein: the semiconductor active region of the selected transistor comprises a pillar having a square or rectangular cross section when viewed from above; and the semiconductor function of the second memory cell The region includes a pillar having a square or rectangular cross section when viewed from above, which is not aligned with the semiconductor active region of the selective transistor and laterally crossed The semiconductor active region of the selected transistor extends. The inverse of the string of claim 1, wherein: the semiconductor active region of the first memory cell comprises a first pillar, the first pillar comprising a first semiconductor region between the second conductivity type a conductive type semiconductor region; the semiconductor active region of the second memory cell includes a second pillar, the second pillar including a first conductivity type between the second conductivity type semiconductor regions a semiconductor region; one of the first pillars of the first conductivity type contacts a second conductivity type semiconductor region of the second pillar; and the first pillar does not overlap the second pillar The objects are aligned such that the first pillar extends transversely across the second pillar. The inverse of the string of claim 6, further comprising: a first charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the first pillar; a first control gate Positioning adjacent to the first charge storage dielectric; a second charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the second pillar; and a second A gate is controlled that is positioned adjacent to the second charge storage dielectric. A method of fabricating a single cell, a three-dimensional inverse and a string, the inverse string comprising a first memory cell located above a second memory cell, the method comprising: Growing a semiconductor active region of the second memory cell; and in a growth step different from the step of growing the semiconductor active region of the second memory cell, on the semiconductor active region of the second memory cell A semiconductor active region of the first memory cell is crystal grown. The method of claim 8, further comprising: forming the second memory unit over a substrate; epitaxially growing a first semiconductor layer on the semiconductor active region of the second memory unit; planarizing the first a semiconductor layer; the first semiconductor layer is patterned into a first semiconductor strip extending in a first direction; a first insulating layer is formed adjacent to the exposed lateral side of the first semiconductor strip; patterning The first semiconductor stripe is formed to form a first semiconductor pillar; forming a first charge storage dielectric positioned adjacent to a first exposed side of the first semiconductor pillar; forming a first control a gate adjacent to the first charge storage dielectric; forming a second charge storage dielectric positioned adjacent to a second exposed side of the first semiconductor pillar; and forming a second A gate is controlled adjacent to the second charge storage dielectric. The method of claim 9, wherein: a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell; the first semiconductor pillar includes the The semiconductor active region of the first memory cell; and the first semiconductor pillar includes a first conductivity type semiconductor region between the second conductivity type semiconductor regions. The method of claim 9, further comprising: depositing a charge storage dielectric film and a control gate layer over the first semiconductor pillar; planarizing the charge storage dielectric film and the control gate layer Exposing the first semiconductor pillar and forming the first charge storage dielectric and the second charge storage dielectric and the first control gate and the second control gate; partially etching the first control a gate and the second control gate; forming a second insulating layer over the first partially etched control gate and the second partially etched control gate; and planarizing the second insulating layer to expose the The first semiconductor pillar. The method of claim 8 further comprising forming a selective transistor on a substrate or in a trench in the substrate. The method of claim 12, further comprising: epitaxially growing a second semiconductor layer on one of the semiconductor active regions of the selective transistor; Flattening the second semiconductor layer; patterning the second semiconductor layer into a second semiconductor strip extending in a first direction; forming a third insulating layer adjacent to the exposed lateral direction of the second semiconductor stripe Forming the second semiconductor strip to form a second semiconductor pillar; forming a third charge storage dielectric positioned adjacent to a first exposed side of the second semiconductor pillar; forming a third control gate adjacent to the third charge storage dielectric; forming a fourth charge storage dielectric positioned adjacent to a second exposed side of the second semiconductor pillar; A fourth control gate is formed adjacent to the fourth charge storage dielectric. The method of claim 13, wherein: the second semiconductor pillar comprises the semiconductor active region of the second memory cell; and the second semiconductor pillar comprises a semiconductor region between the second conductivity type The first conductivity type semiconductor region. The method of claim 14, wherein the second semiconductor pillar is not aligned with a semiconductor active region of the first memory cell. The method of claim 13, wherein the step of forming the selection transistor comprises: Depositing a third semiconductor layer on a substrate or in a substrate; planarizing the third semiconductor layer; patterning the third semiconductor layer into a third semiconductor strip extending in a first direction; Forming a fourth insulating layer adjacent to the exposed lateral side of the third semiconductor strip; patterning the third semiconductor strip to form a third semiconductor pillar; forming a first gate dielectric adjacent thereto Positioning on a first exposed side of the third semiconductor pillar; forming a first select gate adjacent to the first gate dielectric; forming a second gate dielectric adjacent thereto Positioning on a second exposed side of the third semiconductor pillar; and forming a second select gate adjacent to the second gate dielectric. The method of claim 16, wherein: the third semiconductor pillar comprises the semiconductor active region of the select transistor; and the third semiconductor pillar comprises a first region between the second conductivity type semiconductor regions Conductive type semiconductor region. The method of claim 17, wherein the third semiconductor pillar is not aligned with the second semiconductor pillar.