TWI419285B - Bump structure on substrate and forming method thereof - Google Patents

Description

Bump structure on substrate and forming method thereof

The present invention relates to a method of fabricating integrated circuit components, and more particularly to a method of fabricating a bump structure in a semiconductor integrated circuit.

The existing integrated circuit is composed of a plurality of active components such as a transistor and a capacitor arranged in a lateral direction. These components are insulated from each other in the preliminary process, but in the back-end process, the components are connected by interconnects to form a functional circuit. Typical interconnect structures include lateral interconnects such as metal lines, and vertical interconnects such as vias and contacts. The upper limit of the performance and density of existing integrated circuits depends on the interconnection. Above the top of the interconnect structure, there is a corresponding bond pad on each wafer surface. The wafer can be electrically connected to the package substrate or other die via via pads. The bond pads can be applied to wire bonding or flip chip bonding.

In a flip chip package, the bumps can make electrical contact between the leadframe or substrate of the package structure and the output/input pads of the wafer. The above bump structure has, in addition to the bump itself, a bump under metallurgy layer (UBM) between the bump and the output/input pad. In the recently developed copper stud bump technique, copper stud bumps are used instead of solder bumps to connect the electronic components to the substrate. The spacing of the copper stud bumps is small, and the possibility of short-circuit bridging is low, which can reduce the capacitive load of the circuit and increase the operating frequency of the electronic components. The above description will further disclose the above subject matter.

An embodiment of the present invention provides a bump structure on a substrate, comprising a conductive composite layer on a substrate, wherein the conductive composite layer comprises a conductive protective layer on the conductive underlayer, and wherein the conductive protective layer and the conductive underlayer are deposited in the system to avoid oxidation. a conductive underlayer in which the rate of oxidation of the conductive composite layer to air or water is less than the rate of oxidation of the conductive underlayer to air or water; the dielectric layer is on the conductive composite layer; the polymer layer is on the dielectric layer; and the metal bumps, wherein the metal The bump is filled in the second opening of the photoresist layer, wherein the second opening is formed on the first opening of the polymer layer to contact the conductive protective layer of the conductive composite layer, and wherein the metal bump and the conductive protective layer are strong Engage.

Another embodiment of the present invention provides a bump structure on a substrate, including a conductive composite layer on a substrate, wherein the conductive composite layer comprises a conductive protective layer on the conductive underlayer, and wherein the conductive protective layer and the conductive underlayer are deposited in the system to avoid An oxidized conductive underlayer, wherein the rate of oxidation of the conductive composite layer to air or water is less than the rate of oxidation of the conductive underlayer to air or water; the dielectric layer is on the conductive composite layer; the polymer layer is on the dielectric layer; the metal bumps, wherein the metal The bump is filled in the second opening of the photoresist layer, wherein the second opening is formed on the first opening of the polymer layer to contact the conductive protective layer of the conductive composite layer, and wherein the first opening and the polymer layer and the photoresist layer The interfacial pad between them has a sub-bump metallurgy layer and a strong bond between the under bump metallurgy layer and the conductive protective layer.

A further embodiment of the present invention provides a method for forming a bump structure on a substrate, comprising forming a conductive composite layer on a substrate, wherein the conductive composite layer comprises a conductive protective layer and a conductive underlayer, and depositing a conductive underlayer immediately after depositing the conductive underlayer Preventing the substrate from being exposed to air or water; depositing a dielectric layer on the conductive composite layer; depositing the polymer layer on the dielectric layer; etching the dielectric layer and the polymer layer to form a first opening for defining a copper pillar bump structure Depositing a under bump metallurgy layer, wherein the under bump metallurgy layer comprises a copper seed layer; forming a photoresist pattern on the substrate, wherein the photoresist pattern has a second opening defined on the first opening; and depositing a metal pillar bump layer The under bump metallurgy layer and the metal pillar bump layer are both part of the bump structure.

It will be appreciated that the following description provides various embodiments or examples to illustrate various features of the invention. In order to simplify the description, specific embodiments, units, and combinations will be described. However, these specific examples are only intended to illustrate and not to limit the invention. In order to simplify the description, the present invention uses the same reference numerals to refer to the like elements of the different embodiments in the different figures, but the above-mentioned repeated symbols do not mean that the elements in the different embodiments have the same corresponding relationship.

1A-1D is a cross-sectional view showing a process of a copper stud bump in some embodiments of the present invention. The classification of the bumps depends on the materials used and can be divided into solder bumps, gold bumps, copper pillar bumps, or mixed metal bumps. As shown in FIG. 1A, some embodiments have bump formation regions 100 formed on a semiconductor substrate 101. The semiconductor substrate 101 is defined as a semiconductor material including, but not limited to, a substrate germanium, a semiconductor wafer, an insulating layer on-off (SOI) substrate, or a germanium substrate. Other semiconductor materials suitable for the semiconductor substrate 101 may employ Group III, Group IV, or Group V elements. The semiconductor substrate 101 may further include a plurality of insulating structures (not shown) such as a shallow trench isolation (STI) structure or a regional hafnium oxide (LOCOS) structure. The insulating structure can insulate a plurality of microelectronic components (not shown). The microelectronic component formed in the semiconductor substrate 101 may be a gold oxide half field effect transistor (MOSFET), a complementary gold oxide half (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, and a high Frequency transistors, p-channel and/or n-channel field effect transistors (PFET/NFETs), or other transistors, resistors, diodes, capacitors, inductors, fuses, or other suitable components. Different microelectronic component formation methods can include different processes such as deposition, etching, implantation, lithography, tempering, and other suitable processes. The microelectronic component can form integrated circuit components such as logic components, memory components (such as SRAM), radio frequency components, input/output (I/O) components, single-chip system (SoC) components, combinations thereof, by interconnecting wires. Or other suitable type of component.

The semiconductor substrate 101 may have an interlayer dielectric layer and a metal structure formed on the integrated circuit. The interlayer dielectric layer can be a low dielectric constant dielectric material, undoped silicate glass (USG), tantalum nitride, bismuth oxynitride, or other commonly used materials. The low dielectric constant dielectric material may have a dielectric constant (k) of less than about 3.9, or less than about 2.8. The metal lines in the metal structure may be composed of copper or a copper alloy. Methods of forming the metal structure and the interlayer dielectric layer are well known to those skilled in the art and will not be described herein.

As shown in FIG. 1A, a conductive layer 105 is formed on the semiconductor substrate 101. In some embodiments, the conductive layer 105 can be a metal pad, a post-protection interconnect (PPI) layer, or a top metal layer. The metal pad allows the I/O components to be electrically connected to the underlying interconnects and components. In some embodiments, the metal pads can reroute (rewind) the metal interconnects. In the post-protection interconnect (PPI) process, the contact pads and other conductive systems are formed on top of a protective layer (not shown) and connected to the contact regions of the integrated circuits in the semiconductor substrate 101. The PPI rewires the wiring of the integrated circuit to contact the package structure.

The material of the conductive layer 105 may include, but is not limited to, copper, aluminum, copper alloy, or other existing conductive materials. If the conductive layer 105 is composed of copper, a copper diffusion barrier layer (not mentioned) is required to surround the conductive layer 105 to prevent copper from diffusing to the element region of the semiconductor substrate 101. The material of the copper diffusion barrier layer may be titanium, titanium nitride, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

The conductive layer 105 may be formed by electrochemical plating, electroless plating, sputtering, chemical vapor deposition (CVD), or the like. If the conductive layer 105 of copper is deposited by electroplating, a copper seed layer (not shown) can be used to increase the rate and quality of copper plating. In some embodiments, the copper seed layer is deposited by sputtering or CVD. The metal interconnect under the conductive layer 105 is connected to the bump structure by a conductive layer. The conductive layer 105 can function as a transmission line and a redistribution line (RDL). Additionally, conductive layer 105 can further function as an inductive, capacitive, or other passive component. Conductive layer 105 may have a thickness of less than about 30 [mu]m, such as between about 2 [mu]m and about 25 [mu]m.

A dielectric layer 109 (also referred to as an insulating layer or a protective layer) is then formed over the semiconductor substrate 101 and the conductive layer 105. The dielectric layer 109 may be composed of a dielectric material such as tantalum nitride, tantalum carbide, niobium oxynitride, or other useful materials. The dielectric layer 109 can be formed by plasma enhanced CVD (PECVD) or other common CVD methods. In some embodiments, the dielectric layer 109 may or may not be formed. For example, since a protective layer has been deposited under the PPI layer, the dielectric layer 109 may be omitted when the conductive layer 105 is a PPI layer. After the dielectric layer 109 is patterned, the polymer layer 110 can be deposited. Next, another lithography process and another etching process are performed to pattern the polymer layer 110. As a result, the opening 120 is formed through the polymer layer 110 and the dielectric layer 109, and a portion of the conductive layer 105 is exposed to facilitate the subsequent bump process. Although both dielectric layer 109 and polymer layer 110 in FIG. 1A have slanted sidewalls, both may have substantially vertical sidewalls in other embodiments.

The polymer layer 110, as its name suggests, is composed of a polymer such as an epoxy resin, polyamidamine, bisbenzocyclobutane (BCB), polybenzoxazole (PBO), or other soft organic materials. . In certain embodiments, the polymeric layer 110 is a polyammonium layer. In certain embodiments, the polymeric layer is a PBO layer. Since the polymer layer 110 is made of a soft material, the inherent stress on the substrate can be reduced. Further, the thickness of the polymer layer 110 can be easily adjusted to several tens of micrometers.

As shown in Fig. 1B, the under bump metallurgy layer (UBM) 111 can be formed on the structure shown in Fig. 1A. In some embodiments, the UBM layer 111 comprises a copper diffusion barrier layer and a seed layer. The UBM layer 111 is formed on the exposed portion of the polymer layer 110 and the conductive layer 105, and pads the sidewalls and the bottom of the opening 120. In some embodiments, the copper diffusion barrier layer can also serve as an adhesion layer (or a bonding layer). The copper diffusion barrier layer may cover the sidewalls and the bottom of the opening 120, and may be made of tantalum nitride or other materials such as titanium nitride, tantalum, titanium, or the like. In some embodiments, the thickness of the copper diffusion barrier layer is between about 500 To 5000 between. In some embodiments, the copper diffusion barrier layer can be formed by physical vapor deposition (PVD) or sputtering. The seed layer may be a copper seed layer formed on the copper diffusion barrier layer, and may be composed of copper or a copper alloy containing one of the following metals: silver, chromium, nickel, tin, gold, or a combination thereof. In some embodiments, the thickness of the copper seed layer is between about 2000 To 8000 between. In some embodiments, the UBM layer 111 comprises a copper diffusion barrier layer composed of titanium and a seed layer composed of copper, both of which may be PVD or sputtered.

A mask layer 112 is then formed on the UBM layer 111, and the mask layer 112 is patterned to form an opening 123 to expose a portion of the UBM layer 111 to form subsequent copper pillar bumps. In some embodiments, the opening 123 is located on the opening 120. In some embodiments, the size of the opening 123 is greater than or equal to the size of the opening 120. In some embodiments, the opening 123 has a size between 5 μm and 100 μm. The mask layer 112 can be a dry film or a photoresist film. A conductive material having solder wettability can then be filled into some or all of the openings 123. In an embodiment, a metal layer 125 is formed in the opening 123 to contact the underlying UBM layer 111. The metal layer 125 is at a distance D higher than the surface of the polymer layer 110. In certain embodiments, the distance D is between about 5 [mu]m and about 100 [mu]m. In addition to copper, other highly conductive metals can also be used to fill the opening 123.

In some embodiments, the metal layer 125 is copper. In the present disclosure, the so-called copper layer substantially comprises pure elemental copper, copper containing inevitable impurities, or minor constituents of bismuth, indium, tin, zinc, manganese, chromium, titanium, lanthanum, cerium, platinum, A copper alloy of magnesium, aluminum, or zirconium. The metal layer 125 can be formed by sputtering, printing, electroplating, electroless plating, or conventional CVD. For example, electrochemical plating can be used to form the copper metal layer 125. In some embodiments, the copper metal layer 125 has a thickness greater than 30 [mu]m. In some embodiments, the copper metal layer 125 has a thickness greater than 40 [mu]m. In some embodiments, the thickness of the copper metal layer 125 (as shown in FIG. 1B) is between 40 μm and 50 μm. In some embodiments, the thickness H of the copper metal layer 125 is between 40 μm and 70 μm. In some embodiments, the thickness H of the copper metal layer 125 is between 2 μm and 150 μm.

In some embodiments, the metal layer 125 is composed of solder such as tin, tin silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-indium-indium, tin-indium, tin-gold, which has a copper content of less than 3% by weight. Tin-lead, tin-copper, tin-zinc-indium, or tin-silver-tantalum, etc. The solder metal layer 125 can be formed by sputtering, printing, electroplating, electroless plating, or conventional CVD. For example, the ESP can be used to form the solder metal layer 125. In some embodiments, the thickness of the solder metal layer 125 is greater than 30 [mu]m. In some embodiments, the thickness of the solder metal layer 125 is greater than 40 [mu]m. In some embodiments, the thickness of the solder metal layer 125 (as shown in FIG. 1B) is between 40 μm and 50 μm. In some embodiments, the thickness H of the solder metal layer 125 is between 40 μm and 70 μm. In some embodiments, the thickness H of the solder metal layer 125 is between 2 μm and 150 μm.

In some embodiments, a cap layer 126 is then formed over the upper surface of the copper metal layer 125. The cap layer 126 can serve as a barrier layer to prevent copper of the copper pillar metal layer 125 from diffusing to a bonding material such as a solder alloy. The bonding material is used to bond the semiconductor substrate 101 to the external structure. Reducing copper diffusion increases the reliability and joint strength of the package structure. The cap layer 126 can be nickel, tin, tin-lead alloy, gold, silver, palladium, indium, nickel-palladium-gold alloy, nickel-gold alloy, other suitable materials, or alloys. In some embodiments, the cap layer 126 is a nickel layer having a thickness between about 1 [mu]m and 5 [mu]m. In some embodiments, the cover layer 126 is formed by electroplating.

In some embodiments, a solder layer 127 can then be formed over the cap layer. The solder layer may or may not contain lead. In some embodiments, the solder layer 127 and the cap layer 126 can be eutectic alloys. The solder layer 127, the cap layer 126, and the copper pillar metal layer 125 formed on the conductive layer 105 may be referred to as a bump structure 135. The method of forming the solder layer 127 may be electroplating. In some embodiments, the solder layer 127 is a solder ball formed on the cap layer 126. In some embodiments, the solder layer 127 is an electroplated solder layer formed on the cap layer 126. In some implementations, such as lead-free solder systems, the solder layer 127 is tin-silver with a silver content of less than 1.6% by weight. As shown in FIG. 1B, the solder layer 127 and the cap layer 126 are formed in the openings of the mask layer (photoresist layer) 112 by electroplating.

If the composition of the metal layer 125 is solder, the cap layer 126 and the lead-free solder layer 127 may be omitted. Further, if the composition of the metal layer 125 is solder, an additional layer may be formed between the UBM layer 111 and the metal layer 125. In some embodiments, prior to forming the solder metal layer 125', a copper layer 131 and a copper diffusion barrier layer 132, such as a nickel layer, are deposited over the UBM layer, as shown in FIG. 1C. The composition of the solder metal layer 125' may or may not contain lead. The copper layer 131 can reduce the electrical resistance, and the copper diffusion barrier layer 132 can prevent the copper component in the copper layer from diffusing to the solder metal layer 125'. In addition, the copper diffusion barrier layer acts as an adhesion layer and forms a eutectic alloy with the solder. In some embodiments, the copper diffusion barrier layer 132 can be composed of nickel, tin, tin lead, gold, silver, palladium, indium, nickel palladium gold, nickel gold, other similar materials, or alloys.

In some embodiments, the copper layer 131 has a thickness of between about 1 [mu]m and about 10 [mu]m. The thickness of the copper diffusion barrier layer 132 is between about 0.5 [mu]m and about 5 [mu]m. The copper layer 131 and the copper diffusion barrier layer 132 can be deposited by different methods such as sputtering, CVD, or electroplating. The deposition method of the copper layer 131 and the diffusion barrier layer in FIG. 1C is an electroplating process. The distance between the solder metal layer 125' and the upper surface of the polymer layer 110 is D'. In certain embodiments, the distance D' is between about 5 [mu]m and about 100 [mu]m. The bump structure 135' of the metal post has a height H' as shown in Fig. 1C. In certain embodiments, the height H' is between about 5 [mu]m and about 100 [mu]m.

Next, as shown in FIG. 1D, the mask layer 112 shown in FIG. 1B is removed to expose a portion of the UBM layer 111 other than the metal layer 125 (and the cap layer 126 and the lead-free solder layer 127). In certain embodiments, the mask layer 112 is a dry film that can be removed by an alkaline solution. In some embodiments, the mask layer 112 is composed of photoresist, which may be acetone, N-methylpyrrolidone (NMP), dimethyl hydrazine (DMSO), 2-(aminoethoxy)ethanol, or the like. Object removal. The exposed portion of the UBM layer 111 is then removed by etching and the UBM layer under the metal layer is left to expose the polymer layer 110 other than the metal layer 125. If the composition of the metal layer 125 is copper, the remaining metal layer 125 may be referred to as a copper pillar bump layer. The process of removing the exposed UBM layer 111 can be dry etching or wet etching. In some embodiments, a short-term isotropic wet etch (flash etch) may be employed, the etchant being an ammonia-based acid solution. A pillar-shaped bump structure is formed after etching the UBM layer. The stud bumps include a metal bump 125 of a stud bump, a UBM layer 111, a cap layer (not necessary), and a lead-free solder layer 127 (not necessary). As described above, if the composition of the metal layer 125 is solder, the cap layer 126 and the lead-free solder layer 127 may be omitted. As shown in FIG. 1B, the height of the columnar structure 135 of the metal is H. In certain embodiments, the columnar structure 135 of metal has a height H between about 5 [mu]m and 100 [mu]m.

If the exposed portion of the UBM layer 111 is removed by isotropic wet etching, a portion of the UBM layer under the metal layer 125 of the copper stud bumps is etched, a so-called undercut. As previously mentioned, the UBM layer 111 of certain embodiments may be comprised of a diffusion barrier layer 111L such as a titanium layer and a seed layer 111U such as a copper layer, as shown in FIG. 1D. To remove the exposed UBM layer 111, one or more wet etch chemistries may be employed to remove the exposed seed layer 111U and the copper diffusion barrier layer 111L. As previously mentioned, in some embodiments, a short-term isotropic wet etch (flash erosion) uses an ammonia-based acid solution.

To ensure complete removal of the exposed seed layer 111U and the copper diffusion barrier layer 111L, overetching may be employed. In some embodiments, overetching with a wet etch chemistry can cause undercuts, such as the undercut region A shown in FIG. 1D. In addition to the function of avoiding copper diffusion, the copper diffusion barrier layer 111L can also function as an adhesion layer or an adhesion auxiliary layer. Since the copper diffusion barrier layer 111L is undercut, the other copper diffusion barrier layer under the metal pillar-shaped bump structure must perform more adhesive functions. As a result, the stress between the copper diffusion barrier layer 111L and the conductive layer 105 is increased, which causes the UBM layer 111 to be layered with the conductive layer 105. For example, if the composition of the conductive layer 105 is aluminum and the composition of the copper diffusion barrier layer 111L is titanium, the additional interfacial stress caused by the undercut of the copper diffusion barrier layer 111L will cause the interface between the titanium layer and the aluminum layer. Floor.

In order to solve the problem of interface delamination between the conductive layer and the adhesive barrier layer, a conductive layer 105 (such as a metal pad or PPI) and a copper diffusion barrier layer 111L (which may serve as an adhesive layer such as a titanium layer) may be added. Adhesive quality. Taking the embodiment shown in FIG. 1A-1C as an example, the process of forming the metal stud bumps may form and etch the dielectric layer 109 and the polymer layer 110 after forming the conductive layer 105, and then deposit a copper diffusion barrier. Layer (or adhesive layer) 111L. When the surface of the conductive layer 105 is exposed to air and water, its surface will thus be oxidized. For example, if the composition of the conductive layer 105 is aluminum, the surface of the conductive layer 105 will oxidize to form aluminum oxide upon exposure to air and water. After depositing the aluminum conductive layer 105 and moving it out of the vacuum deposition chamber (such as a PVD chamber), the aluminum layer surface begins to form an aluminum oxide layer. When the dielectric layer 109 and the polymer layer 110 are etched, at least a portion of the aluminum oxide layer is removed. However, the exposed aluminum surface after etching can oxidize and form an oxide layer again. If the waiting time between the deposition step of the copper diffusion barrier layer (adhesive layer) 111L and the etching step of the polymer layer 110 is too long, the surface of the aluminum conductive layer 105 will be covered with aluminum oxide. The adhesion between the aluminum oxide layer and the copper diffusion barrier layer composed of titanium is inferior to that between the aluminum layer and the copper diffusion barrier layer composed of titanium. As a result, the aluminum oxide layer is less able to bear the additional stress caused by undercutting of the copper diffusion barrier layer composed of titanium. In order to improve the adhesion quality between the conductive layer 105 (such as a metal pad or PPI) and the UBM layer 111 (such as the copper diffusion barrier layer 111L composed of titanium), a conductive protective layer may be deposited in the same system after deposition of the conductive layer. The conductive protective layer has good adhesion to the conductive layer 105 and the lower layer UBM layer 111. In some embodiments, a vacuum system for depositing conductive layer 105 can also be used to deposit protection 108 on the conductive layer, as shown in FIG. 2A. The material of the protective layer 108 is a conductive material. In some embodiments, the oxidation rate of the protective layer 108 is less than the oxidation rate of the conductive layer 105, or the oxide of the protective layer 108 has good adhesion to the UBM layer 111 (or the lower copper diffusion barrier layer 111L). If the composition of the conductive layer 105 line is copper, aluminum, copper alloy, aluminum alloy, or other existing conductive material, the protective layer 108 may be tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. For example, tantalum, tantalum nitride, titanium, or titanium nitride has a lower oxidation rate than aluminum, and the oxide of the above composition and the copper diffusion barrier layer 111L (such as tantalum, tantalum nitride, titanium, titanium nitride, Good adhesion between or a combination of the above. The protective layer can also be other suitable materials. If the conductive layer 105 is composed of copper, the protective layer 108 can function as a copper diffusion barrier layer.

On-site deposition is defined as the deposition step being carried out in the same chamber or in two separate chambers, but the transfer between the two chambers is carried out under vacuum. The deposition of the protective layer 108 on the conductive layer 105 prevents oxidation of the conductive layer 105 due to exposure to oxygen. In subsequent processes, exposure to air and water will be a conductive protective layer 108 rather than a conductive layer 105. In some embodiments, the electrically conductive protective layer 108 has an oxidation rate that is relatively less than the rate of oxidation of the electrically conductive layer 105. For example, when exposed to air or water, the rate of oxidation of titanium is less than the rate of oxidation of aluminum. In some embodiments, the adhesion of the oxide of the protective layer 108 such as titanium oxide, titanium oxynitride, cerium oxide, cerium oxynitride, or the like to the copper diffusion barrier layer 111L is higher than that of the aluminum oxide and copper diffusion barrier. The adhesion of the barrier layer 111L. The strong bonding between the protective layer 108 and the copper diffusion barrier layer 111L avoids interfacial delamination in the undercut region A of FIG. 2A due to additional stress between the two. In some embodiments, the conductive protective layer 108 can have a thickness of 1000 To 2000 between.

The process for forming the structure of Fig. 2A is substantially similar to the process for forming the structure of Fig. 1D, as shown in Figs. 1A-1D. The only difference between the two is that the structure of FIG. 2A performs an additional on-site deposition process to form the protective layer 108 immediately after deposition of the conductive layer 105.

As described above, the copper diffusion barrier layer 111L may be titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. Since the protective layer 108 and the copper diffusion barrier layer 111L are made of the same material, the copper diffusion barrier layer 111L may be omitted in order to simplify the process. However, the premise of omitting the copper diffusion barrier layer 111L is that the upper layer of the UBM layer, such as the seed layer 111U and the polymer layer 110, has good adhesion. In addition, it is necessary to take into account the copper diffusion problem of the bump structure 135 or 135' of the metal pillar and/or the seed layer 111U composed of copper.

In some embodiments, the copper diffusion barrier layer 111L in the structures of FIGS. 1D and 2A may be omitted, as shown in FIG. 2B. In the example of FIG. 2B, the metal layer 125 is made of copper. The copper stud bump structure 135 of FIG. 2B includes a copper metal layer (or copper stud bump layer) 125 and an upper UBM layer (or copper seed layer 111U). As described above, the copper seed layer 111U and the protective layer 108 have good adhesion, and the seed layer 111U may be copper or a copper alloy containing the following elements: silver, chromium, nickel, tin, gold, or the like. The combination. In addition to having good adhesion to the protective layer 108, the seed layer 111U also needs to have good adhesion to the polymer layer 110 to reduce the interfacial stress of the copper stud bump structure 135. Studies have shown that copper reacts with polyamidoamines containing melamine or triazole to form a copper sulfoxide complex, so that there is good adhesion between the two. The polyamidamine having good adhesion to copper may be poly(4,4'-oxydianhydride-1,3-aminophenoxybenzene-8-azadenine (ODPA-APB-8-) Azaadenine). Studies have also shown that plasma-treated polymers such as polyamido can increase the degree of cross-linking of polymer surfaces, thereby increasing the reactivity of copper with the surface of the polymer after plasma treatment. Thus, copper and electricity There will be no problem of adhesion between the polyamines after the slurry treatment. The crosslinked polyamidoamine can also block the diffusion of copper. In some embodiments, the plasma gas used to treat polyamidamine It may be oxygen, nitrogen, or a combination thereof. In this way, a suitable material may be selected as the polymer layer 110 to increase the adhesion between the polymer layer 110 and the copper seed layer, and the polymer layer 110 may be treated by plasma. Copper diffusion can also be avoided. With the above material selection and plasma treatment, a single copper seed layer can be used as the UBM layer 111 without an additional copper diffusion barrier layer (adhesion layer) 111L.

2C is a process 250 for forming a copper stud bump structure on a conductive layer in certain embodiments of the present invention. The structure of the 2Cth diagram omits the copper diffusion barrier layer 111L as compared with FIG. 2B. In some embodiments, the conductive layer acts as a power line or redistribution line (RDL). In some embodiments, the conductive layer is a metal pad. In other embodiments, the conductive layer is a PPI. In step 251, a conductive underlayer is deposited on the substrate. Prior to step 251, other processing steps of the substrate are performed as described in FIG. 1A, such as forming on-substrate components and interconnects. In some embodiments, the conductive underlayer has a thickness of about 1,000 To approximately 10,000 between. After depositing the conductive underlayer, step 253 is performed to deposit a conductive protective layer. In some embodiments, the conductive protective layer has a thickness of about 500 To approximately 2,000 between. As previously mentioned, the deposition step of the conductive protective layer and the conductive underlayer can be performed in the same chamber or in different chambers in the same system. If the chamber in which the conductive protective layer is deposited is different from the chamber in which the conductive underlayer is deposited, the transfer between the two needs to be carried out under vacuum to reduce or avoid exposure of the substrate to air or oxygen in the environment. After the above steps, the conductive underlayer and the conductive protective layer will form a conductive composite layer.

In some embodiments, after patterning the conductive composite layer, a dielectric material is filled into the spaces between the patterned conductive composite layers. In some embodiments, the conductive composite layer can be filled into openings in the substrate, and the conductive composite layer outside the opening will be removed, and the removal method can be one or more chemical mechanical polishing processes (CMP). After forming the conductive composite layer, step 254 will deposit a dielectric layer. In some embodiments, the thickness of the dielectric layer is between about 500 To approximately 10,000 between. As mentioned previously, the dielectric layer is also referred to as an insulating layer or a protective layer. After step 254, step 255 will pattern and etch the dielectric layer to form (define) an opening to expose the conductive composite layer beneath it.

In some embodiments, step 256 is followed to deposit a polymeric layer. The polymer layer may be composed of a softer organic material such as an epoxy resin, polyamidamine, bisbenzocyclobutane (BCB), polybenzoxazole (PBO), or the like. As mentioned earlier, the polymer layer can be bonded to copper. In certain embodiments, the composition of the polymeric material can be poly(4,4'-oxydiaphthalic anhydride-1,3-aminophenoxybenzene-8-azadenine. In certain embodiments Medium, the thickness of the polymer layer is between about 500 To approximately 10,000 between.

In some embodiments, to form a copper stud bump structure, after depositing the polymer layer, step 257 may be performed to pattern and etch the substrate, and the formed opening may expose the conductive composite layer. The polymer layer and the dielectric layer can then be etched according to the opening pattern until the protective layer is exposed. After step 257, step 258 treats the surface of the polymer layer with plasma to increase the reactivity between the surface of the polymer layer after the plasma and the subsequently deposited copper layer. As mentioned previously, the plasma treated gas can be oxygen, nitrogen, or a combination thereof.

In some embodiments, after the plasma is treated with the surface of the polymeric layer, step 259 will deposit a copper seed layer 111U. In some embodiments, the thickness of the copper seed layer is between about 100 To approximately 10,000 between. The copper seed layer directly contacts the protective layer and is beneficial for the growth of the copper stud bump structure in the subsequent steps. The copper seed layer may be deposited by PVD, CVD, atomic layer deposition (ALD), or electroless deposition. After depositing the copper seed layer in certain embodiments, step 260 patterns the substrate to form (defining) openings to facilitate deposition of copper. The photoresist used to pattern the substrate can be dry or wet. In some embodiments, the patterned opening of step 260 will be greater than the opening formed by step 257, as shown in FIG. 2B.

In step 261, a metal layer such as copper is deposited in the openings formed in steps 260 and 257. In some embodiments, the copper film can be deposited by electrochemical plating (ECP) or electroless plating. The copper film can also be formed by other deposition methods. After the step of depositing a copper layer in certain embodiments, step 262 deposits a cap layer such as nickel or other materials as previously described. In some embodiments, the method of depositing the cap layer can be ECP or electroless plating. In some embodiments, step 263 deposits a layer of solder on the cap layer. As previously mentioned, the solder layer can be lead-free or lead-containing material.

Next, step 264 is performed to remove the photoresist layer formed in step 260, and then step 265 is performed to etch (or remove) the exposed copper seed layer (the portion not covered by the copper pillar). At the end of step 265, a copper stud bump structure is formed in contact with the conductive composite layer. After step 265 of some embodiments, a reflow step 266 is performed to round up the shape of the lead-free solder layer, as shown in Figure 2D.

As shown in Fig. 1C, the composition of the metal layer 125' may be solder. Below the solder metal layer 125' is a copper layer 131 and a copper diffusion barrier layer 132 such as a nickel layer. The copper layer 131 is deposited directly on the UBM layer 111. As described above, the conductive protective layer 108 may also be deposited on the conductive underlayer 105 to form a conductive composite layer. As previously mentioned, the conductive protective layer 108 can be composed of a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. Further, in some embodiments, the use of an additional conductive protective layer can simplify the UBM layer 111 to a single copper layer (or seed layer 111U). In some embodiments, the bump structure 135' of solder composition is as shown in Figure 3A. Similar to the bump structure 135' composed of the solder shown in Fig. 1C, the bump structure of Fig. 3A differs in that an additional reflow process is performed.

In some embodiments, the process of forming the solder bump structure shown in FIG. 3A is the process 350 shown in FIG. 3B. Steps 351-360 of process 350 are similar to steps 251-260 of process 250 in Figure 2C. After forming an opening for depositing metal, step 361 deposits a copper layer 131 in the opening. In some embodiments, the copper layer is deposited by an electroplating process such as an ECP process or an electroless plating process. As described in the related description of FIG. 1C, the copper layer can reduce the resistance of the solder bumps. Subsequent step 362 will deposit a copper diffusion barrier layer. In some embodiments, the deposition method of the copper diffusion barrier layer is an electroplating process such as an ECP process or an electroless plating process. Next, step 363 is performed to deposit a metal layer on the copper diffusion barrier layer. In some embodiments, the composition of the metal layer is solder. In some embodiments, the copper layer is deposited by an electroplating process such as an ECP process or an electroless plating process. After depositing the copper layer, the photoresist layer formed in step 360 is removed, and step 365 is performed to remove the exposed copper seed layer as described above in step 265. Next, step 366 is performed to reflow the substrate, and the shape of the metal layer such as the solder layer can be adjusted. Figure 3A shows the solder bump after reflow.

In the embodiments of Figs. 1C and 3A, the solder metal layer 125' is located under the copper layer 131. In some embodiments, the copper layer 131 and the copper diffusion barrier layer 132 may be omitted. In these embodiments, the UBM layer 111 or the copper seed layer 111U may also be omitted. However, the conductive protective layer 108 on the conductive layer (or conductive underlayer) can still avoid oxidation of the conductive layer 105 while improving the adhesion of the solder metal layer 125'. In some embodiments, the cross-sectional structure of the solder bump structure 135" is as shown in FIG. 4A. The solder bump structure 135" of FIG. 4A is similar to the solder bump structure 135' of FIG. 1C and FIG. 3A. The solder bump structure 135' differs in that the solder bump structure 135" of FIG. 4A does not have the UBM layer 111, the copper layer 131, and the copper diffusion barrier layer 132. The solder metal layer 125 can be used for the surface of the semiconductor substrate 101. The filling opening 123 is formed by applying a solder paste on the semiconductor substrate 101. The solder paste may fill the opening 123. A small amount of solder paste may remain on the surface of the photoresist layer 112, but the residual amount is small. The subsequent photoresist removal process will not be affected. FIG. 4B shows the bump structure 135" of the solder after removing the photoresist layer 112 and reflowing the semiconductor substrate 101 in some embodiments.

Figure 4C shows a process 450 for forming the solder bump structure of Figure 4B in some embodiments. Steps 451-457 of Figure 4C are similar to steps 351-357 of Figure 3B and steps 251-257 of Figure 2C. In a subsequent step 460, an opening is formed in the opening formed in step 457. After step 460, a layer of solder metal is deposited over the openings formed in steps 457 and 460. In some embodiments, the solder metal layer is applied as a paste to the surface of the substrate with a very small amount of solder paste remaining on the surface of the photoresist layer. Since the method of forming the solder metal layer on the substrate is not electroplating, it is not necessary to plasma treat the polymer layer. In addition, the material selection of the polymer layer in this method is more diverse. The method can adopt a conventional polymer material which generally encapsulates a substrate. Step 464 is then performed to remove the photoresist layer, and step 465 is performed to reflow the substrate (or solder bumps).

The formation mechanism of the above metal bump structure can solve the delamination problem of the interface between the conductive layer on the substrate and the metal bump connected to the conductive layer. The conductive layer can be a metal pad, a PPI, or a top metal layer. The conductive protective layer is deposited on the conductive layer (or the conductive underlayer) via the field, the metal bump of the metal bump has good adhesion between the metallurgical layer and the conductive layer, and interface delamination can be reduced. In some embodiments, since the conductive protective layer can serve as a copper barrier layer, the copper diffusion barrier layer in the under bump metallurgy layer can be omitted. In these embodiments, a polymer having good adhesion to copper such as polyammonium amine can be used. In addition, the surface of the polymer layer may be treated with a plasma to form a copper diffusion barrier layer. In some embodiments, if the deposition method of the metal bump structure is an electroless plating process and the composition of the metal bumps is not copper, the under bump metal layer may be omitted.

A bump structure on a substrate is provided in some embodiments. The bump structure includes a conductive composite layer on the substrate, and the conductive composite layer includes a conductive protective layer on the conductive bottom layer. A conductive protective layer and a conductive underlayer are deposited in the system to avoid oxidizing the conductive underlayer. The rate of oxidation of the electrically conductive composite layer to air or water is less than the rate of oxidation of the electrically conductive substrate to air or water. The bump structure also has a dielectric layer on the conductive composite layer and a polymer layer on the dielectric layer. The bump structure further includes a metal bump, and the metal bump fills the second opening of the photoresist layer. The second opening is formed on the first opening of the polymer layer to contact the conductive protective layer of the conductive composite layer, and has strong bonding between the metal bump and the conductive protective layer.

Another embodiment provides a method of forming a bump structure on a substrate. The bump structure includes a conductive composite layer on the substrate, and the conductive composite layer includes a conductive protective layer on the conductive bottom layer. A conductive protective layer and a conductive underlayer are deposited in the system to avoid oxidizing the conductive underlayer. The rate of oxidation of the electrically conductive composite layer to air or water is less than the rate of oxidation of the electrically conductive substrate to air or water. The bump structure also has a dielectric layer on the conductive composite layer and a polymer layer on the dielectric layer. The bump structure further comprises a copper bump filling the second opening of the photoresist layer, and the second opening is formed on the first opening of the polymer layer to contact the conductive protective layer of the conductive composite layer. The interface between the first opening surface and the polymer layer and the photoresist layer is padded with an under bump metallurgy layer (UBM), and there is a strong bond between the under bump metallurgy layer and the conductive protective layer.

Yet another embodiment further provides a method for forming a bump structure on a substrate, comprising forming a conductive composite layer on the substrate, and the conductive composite layer comprises a conductive protective layer and a conductive underlayer. Depositing a conductive protective layer immediately after depositing the conductive underlayer prevents the substrate from being exposed to air or water. The method also deposits a dielectric layer on the conductive composite layer and deposits a polymer layer on the dielectric layer. In order to form a copper stud bump structure, the method further etches the dielectric layer and the polymer layer to form a first opening, and deposits a bump under metallurgy layer to define a copper stud bump structure. The under bump metallurgy layer comprises a copper seed layer. Further, a photoresist pattern is formed on the substrate, and the photoresist pattern has a second opening defined on the first opening. A metal pillar bump layer is then deposited, wherein the under bump metallurgy layer and the metal pillar bump layer are both part of the bump structure.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

A. . . Undercut area

D, D’‧‧‧The distance between the metal layer and the polymer layer

H‧‧‧metal layer thickness

100‧‧‧Bump formation area

101‧‧‧Semiconductor substrate

105‧‧‧ Conductive layer

108‧‧‧Protective layer

109‧‧‧ dielectric layer

110‧‧‧ polymer layer

111‧‧‧ under the bump metallurgy

111L‧‧‧ copper diffusion barrier

111U‧‧‧ seed layer

112‧‧‧mask layer

120, 123‧‧‧ openings

125‧‧‧metal layer

125'‧‧‧ solder metal layer

126‧‧‧ cover

127‧‧‧ solder layer

131‧‧‧ copper layer

132‧‧‧ Copper Diffusion Barrier

135, 135', 135" ‧ ‧ bump structure

250, 350, 450‧ ‧ process

251, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 351, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 451, 453, 454, 455, 456, 457, 460, 461, 464, 466 ‧ ‧ steps

1A-1D is a cross-sectional view showing a process of a copper stud bump in some embodiments of the present invention;

2A is a cross-sectional view showing a structure in which a protective layer is deposited on a conductive layer in some embodiments of the present invention;

2B is a cross-sectional view showing a structure lacking a lower UBM layer in the same region as the first and second panels according to a portion of the present invention;

2C is a flow chart showing the formation of a copper pillar structure on the conductive layer and lacking a lower UBM layer in FIG. 2B in some embodiments of the present invention;

2D is a cross-sectional view showing a structure of a substrate of FIG. 2B after a reflow process in some embodiments of the present invention;

3A is a cross-sectional view showing the structure of a solder bump on a substrate in some embodiments of the present invention;

3B is a flow chart of forming a solder bump of FIG. 3A in some embodiments of the present invention;

4A is a cross-sectional view showing the structure of a solder bump on a substrate in some embodiments of the present invention;

4B is a cross-sectional view showing a structure of a solder bump after removing the photoresist of FIG. 4A and performing a reflow process on the substrate in some embodiments of the present invention;

Fig. 4C is a flow chart showing the formation of the solder bumps of Figs. 4A and 4B in some embodiments of the present invention.

101. . . Semiconductor substrate

105. . . Conductive layer

108. . . The protective layer

109. . . Dielectric layer

110. . . Polymer layer

135"...bump structure

Claims (10)

A bump structure on a substrate, comprising: a conductive composite layer on the substrate, wherein the conductive composite layer comprises a conductive protective layer on a conductive underlayer, and wherein the conductive protective layer and the conductive underlayer are deposited in a system To avoid oxidation of the conductive underlayer, wherein the conductive composite layer has an oxidation rate to air or water that is less than an oxidation rate of the conductive underlayer to air or water; a dielectric layer is on the conductive composite layer; a polymer layer is located in the dielectric layer And a metal bump, wherein the metal bump is filled in a second opening of a photoresist layer, wherein the second opening is formed on one of the first openings of the polymer layer to contact the conductive composite layer The conductive protective layer, and wherein the metal bump and the conductive protective layer have a strong bonding and continuous interface. The bump structure on the substrate of claim 1, wherein the first opening and the interface between the polymer layer and the photoresist layer have an under bump metallurgy layer, and the under bump The metallurgical layer is part of the metal bump. The bump structure on the substrate of claim 1, wherein the conductive composite layer is a metal pad, a rear protective interconnect, or a top metal layer. A bump structure on a substrate, comprising: a conductive composite layer on the substrate, wherein the conductive composite layer comprises a conductive protective layer on a conductive underlayer, and wherein the conductive protective layer and the conductive underlayer are deposited in a system To avoid oxidation of the conductive bottom a layer, wherein the conductive composite layer has an oxidation rate to air or water that is less than an oxidation rate of the conductive substrate to air or water; a dielectric layer is on the conductive composite layer; a polymer layer is on the dielectric layer; and a metal bump, wherein the metal bump is filled in a second opening of a photoresist layer, wherein the second opening is formed on one of the first openings of the polymer layer to contact the conductive protective layer of the conductive composite layer And wherein the first opening and the interface between the polymer layer and the photoresist layer have an under bump metallurgy layer, and the under bump metallurgy layer and the conductive protective layer have a strong bonding and continuous interface . The bump structure on the substrate of claim 4, wherein the under bump metallurgy layer is a copper seed layer. A method for forming a bump structure on a substrate, comprising: forming a conductive composite layer on the substrate, wherein the conductive composite layer comprises a conductive protective layer and a conductive underlayer, and depositing the conductive protective layer immediately after depositing the conductive underlayer The substrate is exposed to air or water; a dielectric layer is deposited on the conductive composite layer; a polymer layer is deposited on the dielectric layer; and the dielectric layer and the polymer layer are etched to form a first opening. For defining a copper pillar bump structure; depositing a bump under metallurgy layer, wherein the under bump metallurgy layer comprises a copper seed layer; forming a photoresist pattern on the substrate, wherein the photoresist pattern has a a second opening is defined on the first opening; Depositing a metal pillar bump layer, wherein the under bump metallurgy layer and the metal pillar bump layer are part of the bump structure, and the under bump metallurgy layer and the conductive protective layer have strong bonding With a continuous interface. The method for forming a bump structure on a substrate according to claim 6, further comprising: after defining the second opening, performing a plasma surface treatment to treat the exposed surface of the polymer layer, wherein the electricity The surface treatment of the slurry increases the degree of crosslinking of the surface of the polymer, and increases the reactivity of the copper seed layer with the surface of the polymer after the plasma treatment, and the polymer layer formed by crosslinking forms a copper diffusion barrier layer. The method for forming a bump structure on a substrate according to claim 7, wherein the plasma surface treatment uses oxygen, nitrogen, or a combination thereof. The method for forming a bump structure on a substrate according to claim 6, wherein the conductive protective layer has a oxidation rate to air or water that is smaller than an oxidation rate of the conductive bottom layer to air or water. The method for forming a bump structure on a substrate according to claim 6, wherein the conductive protective layer reduces delamination between the metal bump structure and the conductive underlayer.