TWI418973B - Overall reset circuit, computer system with overall reset circuit and overall reset method thereof - Google Patents
Overall reset circuit, computer system with overall reset circuit and overall reset method thereof Download PDFInfo
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Description
本發明係關於一種整體重設電路、具有整體重設電路之電腦系統及其整體重設之方法,特別是一種軟體或是韌體控制之整體重設電路、具有整體重設電路之電腦系統及其整體重設之方法。The present invention relates to an overall reset circuit, a computer system having an overall reset circuit, and a method for overall resetting thereof, in particular, a software or firmware controlled overall reset circuit, a computer system having an overall reset circuit, and The overall method of resetting.
隨著科技的發展,電腦系統已經成為了一般人在日常生活中所不可或缺的裝置。而使用者在操作電腦系統上的某些特殊功能時,有時需要移除電源訊號之輸入,以使得整個電腦系統斷電。如此一來,使用者即可對電腦系統做特殊的操作或設定。上述之流程即為整體重設(Global Reset)之流程。With the development of technology, computer systems have become an indispensable device for ordinary people in their daily lives. When the user operates certain special functions on the computer system, it is sometimes necessary to remove the input of the power signal to power off the entire computer system. In this way, the user can perform special operations or settings on the computer system. The above process is the process of Global Reset.
在先前技術中,若要對電腦系統進行整體重設之流程,必須要利用手動移除電源輸入之纜線,或是調整電腦系統之電源供應器後方的開關才可以使得整個電腦系統斷電。但對於先前技術中的電腦系統,使用者都必須移動電腦系統之機殼,或是需要從複雜的線路中找到正確的電源輸入之纜線才能進行整體重設。因此,對於使用者而言會造成不方便,並且搬動電腦系統亦可能會造成電腦系統的損壞。In the prior art, in order to perform the overall reset process of the computer system, it is necessary to manually remove the power input cable or adjust the switch behind the power supply of the computer system to power off the entire computer system. However, for the computer system of the prior art, the user must move the casing of the computer system or the cable that needs to find the correct power input from the complicated circuit to perform the overall reset. Therefore, it is inconvenient for the user, and the computer system may also cause damage to the computer system.
有鑑於此,有需要發明一種整體重設之電路及具有此 電路之電腦系統,以解決先前技術的缺失。In view of this, there is a need to invent an overall reset circuit and have this The computer system of the circuit to solve the lack of prior art.
本發明之主要目的係在提供一種整體重設電路,可利用電路佈局以達成電腦系統整體重設之效果。The main object of the present invention is to provide an overall reset circuit that can utilize the circuit layout to achieve the overall reset effect of the computer system.
本發明之另一主要目的係在提供一種具有整體重設電路之電腦系統。Another primary object of the present invention is to provide a computer system having an overall reset circuit.
本發明之又一主要目的係在提供一種用於電腦系統之整體重設之方法Yet another primary object of the present invention is to provide a method for overall resetting of a computer system
為達成上述之目的,本發明之整體重設電路係用於電腦系統。電腦系統具有主機板、電源輸入裝置及控制訊號產生模組。整體重設電路包括第一開關模組、第二開關模組及電容。電源輸入裝置係輸入電源訊號至第一開關模組,以輸出系統電源訊號至主機板。第二開關模組係與第一開關模組電性連接。電容係與第一開關模組及第二開關模組電性連接。其中主機板係輸入系統電源訊號至第二開關模組。控制訊號產生模組係輸入控制訊號至第二開關模組,以控制第二開關模組利用系統電源訊號對電容進行充電。電容充電後係輸出高電位訊號至第一開關模組,以切斷第一開關模組所輸出至主機板及第二開關模組之系統電源訊號。第二開關模組被切斷系統電源訊號後,電容係進行放電,再輸出低電位訊號至第一開關模組,以控制第一開關模組恢復輸出系統電源訊號。To achieve the above objects, the overall reset circuit of the present invention is used in a computer system. The computer system has a motherboard, a power input device, and a control signal generating module. The overall reset circuit includes a first switch module, a second switch module, and a capacitor. The power input device inputs a power signal to the first switch module to output a system power signal to the motherboard. The second switch module is electrically connected to the first switch module. The capacitor is electrically connected to the first switch module and the second switch module. The motherboard is configured to input a system power signal to the second switch module. The control signal generating module inputs the control signal to the second switch module to control the second switch module to charge the capacitor by using the system power signal. After the capacitor is charged, the high-potential signal is outputted to the first switch module to cut off the system power signal outputted by the first switch module to the motherboard and the second switch module. After the second switch module is cut off from the system power signal, the capacitor system discharges, and then outputs a low potential signal to the first switch module to control the first switch module to restore the output system power signal.
本發明之具有整體重設電路之電腦系統包括主機板、整體重設電路、電源供應裝置及控制訊號產生模組。整體重設電路係設置於主機板上。整體重設電路包括切換控制模組及回復控制模組。回復控制模組係與切換控制模組電性連接。電源供應裝置係與切換控制模組電性連接,用以提供電源訊號,以經由切換控制模組輸出系統電源訊號至主機板及回復控制模組。控制訊號產生模組係與回復控制模組電性連接,用以產生控制訊號至回復控制模組,以控制切換控制模組切斷輸出至主機板及回復控制模組之系統電源訊號。回復控制模組被切斷系統電源訊號後,係自動控制切換控制模組重新導通,以恢復系統電源訊號之傳輸。The computer system with the overall reset circuit of the present invention comprises a motherboard, an overall reset circuit, a power supply device and a control signal generating module. The overall reset circuit is set on the motherboard. The overall reset circuit includes a switching control module and a reply control module. The recovery control module is electrically connected to the switching control module. The power supply device is electrically connected to the switching control module for providing a power signal for outputting the system power signal to the motherboard and the recovery control module via the switching control module. The control signal generating module is electrically connected to the reply control module for generating a control signal to the reply control module for controlling the switching control module to cut off the system power signal outputted to the motherboard and the control module. After the control module is disconnected from the system power signal, the automatic control switching control module is re-conducted to restore the transmission of the system power signal.
本發明之整體重設之方法包括以下步驟:輸入電源訊號至切換控制模組以產生系統電源訊號至回復控制模組;輸入控制訊號至回復控制模組;控制切換控制模組切斷系統電源訊號之傳輸;以及被切斷該系統電源訊號後,係自動控制切換控制模組恢復系統電源訊號之傳輸。The method for overall resetting of the present invention comprises the steps of: inputting a power signal to a switching control module to generate a system power signal to a reply control module; inputting a control signal to a reply control module; and controlling the switching control module to cut off the system power signal After the transmission of the system power signal, the automatic control switching control module restores the transmission of the system power signal.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉出本發明之具體實施例,並配合所附圖式,作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <
請先參考圖1係本發明具有整體重設電路之電腦系統之架構圖。Please refer to FIG. 1 for the architecture diagram of the computer system with the overall reset circuit of the present invention.
本發明之電腦系統1具有整體重設(Global Reset)之功能,可以提供使用者藉由軟體或是韌體控制之方式,利 用電腦系統1內之電路佈局而完全移除電源訊號之輸入。不需藉由使用者操作硬體,例如拔除電源輸入之纜線之方式,才能整體重設。The computer system 1 of the present invention has the function of Global Reset, which can provide a way for the user to control by software or firmware. The input of the power signal is completely removed by the circuit layout in the computer system 1. The overall reset is not required by the user operating the hardware, such as removing the cable from the power input.
本發明之電腦系統1包括整體重設電路10、主機板20、電源供應裝置30及控制訊號產生模組40。整體重設電路10係設置於主機板20上,並且整體重設電路10係與控制訊號產生模組40電性連接。The computer system 1 of the present invention includes an overall reset circuit 10, a motherboard 20, a power supply device 30, and a control signal generating module 40. The overall reset circuit 10 is disposed on the motherboard 20, and the overall reset circuit 10 is electrically connected to the control signal generating module 40.
電源供應裝置30用以提供一電源訊號,以經由整體重設電路10提供系統電源訊號至主機板20上之各元件。電源供應裝置30可為外部之電源供應器或是電腦系統1之電池,但本發明並不以此為限。其中電源訊號係為電腦系統1於關機狀態下,電源供應裝置30所供應之待命電源訊號;而系統電源訊號係為電腦系統1於關機狀態下,主機板20所接收之待命電源訊號,用以讓電腦系統1能順利開機。在本發明之一實施例中,電源訊號及系統電源訊號皆為5伏特之電壓訊號,但本發明並不以此為限。The power supply device 30 is configured to provide a power signal to provide system power signals to the components on the motherboard 20 via the overall reset circuit 10. The power supply device 30 can be an external power supply or a battery of the computer system 1, but the invention is not limited thereto. The power signal is the standby power signal supplied by the power supply device 30 when the computer system 1 is turned off; and the system power signal is the standby power signal received by the motherboard 20 when the computer system 1 is turned off. Let computer system 1 boot up smoothly. In an embodiment of the invention, the power signal and the system power signal are all 5 volt voltage signals, but the invention is not limited thereto.
控制訊號產生模組40用以發出控制訊號,以決定整體重設電路10是否要切斷系統電源訊號之輸出。控制訊號產生模組40可為藉由韌體控制之基本輸入輸出系統(Basic Input/Output System,BIOS)或是利用軟體架構之可程式化模組,但本發明並不以此為限。使用者可以藉由鍵盤控制軟體、作業系統或是韌體選項等方式來要求控制訊號產生模組40發出控制訊號。The control signal generating module 40 is configured to issue a control signal to determine whether the overall reset circuit 10 is to cut off the output of the system power signal. The control signal generating module 40 can be a basic input/output system (BIOS) controlled by a firmware or a programmable module using a software architecture, but the invention is not limited thereto. The user can request the control signal generating module 40 to send a control signal by means of a keyboard control software, an operating system or a firmware option.
整體重設電路10可切斷系統電源訊號之提供,並經過一段時間後再恢復系統電源訊號之傳輸。整體重設電路10 包括切換控制模組11及回復控制模組12。切換控制模組11可視為一開關,與電源供應裝置30電性連接,使得電源供應裝置30必須要經由切換控制模組11才能輸出供應給電腦系統1之系統電源訊號。此系統電源訊號會供應至主機板20以及回復控制模組12。回復控制模組12係同時與控制訊號產生模組40及切換控制模組11電性連接。控制訊號產生模組40所產生之控制訊號係藉由回復控制模組12控制切換控制模組11切斷系統電源訊號之傳輸。在回復控制模組12被切斷系統電源訊號一段時間後,可利用其內部電路自動控制切換控制模組11恢復傳輸系統電源訊號。如此一來,主機板20可以重新接收到供其待命之系統電源訊號,電腦系統1即可完成整體重設之流程。The overall reset circuit 10 can cut off the supply of the system power signal and resume the transmission of the system power signal after a period of time. Overall reset circuit 10 The switching control module 11 and the reply control module 12 are included. The switching control module 11 can be regarded as a switch, and is electrically connected to the power supply device 30, so that the power supply device 30 must output the system power signal supplied to the computer system 1 via the switching control module 11. The system power signal is supplied to the motherboard 20 and to the reply control module 12. The reply control module 12 is electrically connected to the control signal generating module 40 and the switching control module 11 at the same time. The control signal generated by the control signal generating module 40 controls the switching control module 11 to interrupt the transmission of the system power signal by the reply control module 12. After the recovery control module 12 is turned off the system power signal for a period of time, the internal circuit can automatically control the switching control module 11 to restore the transmission system power signal. In this way, the motherboard 20 can re-receive the system power signal for the standby, and the computer system 1 can complete the overall reset process.
接著請參考圖2關於本發明整體重設電路之電路圖。此處需注意的是,以下雖以圖2中所示之電子元件及電路佈局為例進行說明,但本發明之整體重設電路10並不限定僅能由圖2中所示之電子元件及其電路佈局所構成。Next, please refer to FIG. 2 for a circuit diagram of the overall reset circuit of the present invention. It should be noted here that although the electronic components and circuit layouts shown in FIG. 2 are taken as an example, the overall reset circuit 10 of the present invention is not limited to only the electronic components shown in FIG. 2 and Its circuit layout is composed.
整體重設電路10之切換控制模組11包括第一開關模組Q1,本實施例中第一開關模組Q1係為一金氧半場效電晶體(MOSFET),但本發明並不以此為限。第一開關模組Q1具有源極S、汲極D及閘極G。電源供應裝置30係與第一開關模組Q1之源極S電性連接,並且第一開關模組Q1之汲極D再與主機板20電性連接,以輸出供主機板20待命之系統電源訊號。閘極G係用以控制源極S與汲極D是否導通。The switching control module 11 of the overall reset circuit 10 includes a first switch module Q1. In this embodiment, the first switch module Q1 is a metal oxide half field effect transistor (MOSFET), but the present invention does not limit. The first switch module Q1 has a source S, a drain D, and a gate G. The power supply device 30 is electrically connected to the source S of the first switch module Q1, and the drain D of the first switch module Q1 is electrically connected to the motherboard 20 to output a system power supply for the motherboard 20 to stand by. Signal. The gate G is used to control whether the source S and the drain D are turned on.
回復控制模組12包括第二開關模組Q2及複數之電容 C1、C2及複數之電阻R1、R2,其中部分之電容及電阻係用以調整此電路之穩定度。由於並非本發明之重點所在,故在此不再贅述其作用。在本實施例中第二開關模組Q2係為一雙載子接面電晶體(BJT),但本發明並不以此為限。第二開關模組Q2具有集極E、射極C及基極B。其中基極B係與控制訊號產生模組40電性連接,可以藉由控制訊號改變其電位高低,以決定集極E與射極C是否導通。射極C係與主機板20電性連接,以接收經由主機板20所傳輸之系統電源訊號。集極E係與電容C1及第一開關模組Q1之閘極G電性連接,以藉由電容C1之充放電控制閘極G之電位高低。如此一來,即可決定第一開關模組Q1是否輸出供主機板20待命之系統電源訊號。The recovery control module 12 includes a second switch module Q2 and a plurality of capacitors C1, C2 and a plurality of resistors R1, R2, part of which is used to adjust the stability of the circuit. Since it is not the focus of the present invention, its function will not be described herein. In the embodiment, the second switch module Q2 is a double carrier junction transistor (BJT), but the invention is not limited thereto. The second switch module Q2 has a collector E, an emitter C and a base B. The base B is electrically connected to the control signal generating module 40, and the potential of the collector can be changed by the control signal to determine whether the collector E and the emitter C are turned on. The emitter C is electrically connected to the motherboard 20 to receive the system power signal transmitted via the motherboard 20. The collector E is electrically connected to the capacitor C1 and the gate G of the first switching module Q1 to control the potential of the gate G by the charge and discharge of the capacitor C1. In this way, it can be determined whether the first switch module Q1 outputs a system power signal for the motherboard 20 to stand by.
接著請參考圖3關於本發明整體重設之方法之步驟流程圖。此處需注意的是,以下雖以圖2中所示之電子元件及電路佈局為例說明本發明之整體重設之方法,但本發明並不限定需利用圖2中所示之電子元件及電路佈局以達成本發明之整體重設之方法。Next, please refer to FIG. 3 for a flow chart of the steps of the method for overall resetting of the present invention. It should be noted that the following describes the overall resetting method of the present invention by taking the electronic components and circuit layout shown in FIG. 2 as an example. However, the present invention is not limited to the use of the electronic components shown in FIG. The circuit layout is to achieve a method of overall resetting of the present invention.
本發明之整體重設之方法首先會進行步驟301:輸入電源訊號至切換控制模組以產生系統電源訊號至回復控制模組。The method for overall resetting of the present invention first performs step 301: inputting a power signal to the switching control module to generate a system power signal to the reply control module.
首先電源供應裝置30會輸入電源訊號至第一開關模組Q1之源極S。而第一開關模組Q1之閘極G係經由電阻R1而接地,因此在初始狀態下閘極G係為低電位,而使得源極S與汲極D導通。因此當電源供應裝置30輸入電源訊號至源極S後,汲極D係輸出系統電源訊號到主機板20 以作為主機板之待命電源。此時第二開關模組Q2之基極B係為高電位,因此第二開關模組Q2並不動作。First, the power supply device 30 inputs a power signal to the source S of the first switch module Q1. The gate G of the first switching module Q1 is grounded via the resistor R1. Therefore, in the initial state, the gate G is at a low potential, and the source S and the drain D are turned on. Therefore, when the power supply device 30 inputs the power signal to the source S, the drain D system outputs the system power signal to the motherboard 20 As a standby power supply for the motherboard. At this time, the base B of the second switch module Q2 is at a high potential, so the second switch module Q2 does not operate.
其次進行步驟302:輸入控制訊號至回復控制模組之第二開關模組。Next, proceed to step 302: input a control signal to the second switch module of the reply control module.
當使用者欲將電腦系統1進行整體重設之流程時,係藉由控制訊號產生模組40在電腦系統1關機前輸入控制訊號至回復控制模組12之第二開關模組Q2。其中使用者可以藉由鍵盤控制軟體、作業系統或是韌體選項來要求控制訊號產生模組40發出控制訊號,但本發明並不以上述的方法為限。When the user wants to perform the overall reset process of the computer system 1, the control signal generating module 40 inputs the control signal to the second switch module Q2 of the reply control module 12 before the computer system 1 is turned off. The user can request the control signal generating module 40 to send a control signal by using a keyboard control software, an operating system or a firmware option, but the present invention is not limited to the above method.
此控制訊號即可控制第二開關模組Q2進行步驟303:控制第二開關模組利用系統電源訊號對電容進行充電。The control signal can control the second switch module Q2 to perform step 303: controlling the second switch module to charge the capacitor by using the system power signal.
當控制訊號產生模組40傳送控制訊號到回復控制模組12後,第二開關模組Q2之基極B係被控制訊號拉成低電位,而使得集極E與射極C導通,同時將系統電源訊號傳輸至電容C1。如此一來,電容C1即可利用系統電源訊號而開始充電。After the control signal generating module 40 transmits the control signal to the reply control module 12, the base B of the second switch module Q2 is pulled to a low potential by the control signal, so that the collector E and the emitter C are turned on, and at the same time The system power signal is transmitted to capacitor C1. In this way, the capacitor C1 can start charging by using the system power signal.
接著進行步驟304:控制切換控制模組切斷系統電源訊號之傳輸。Then proceed to step 304: control the switching control module to cut off the transmission of the system power signal.
在電容C1充電到達高電位後,第一開關模組Q1之閘極G亦同樣到達高電位,而切斷源極S與汲極D之導通。如此一來,即可控制切換控制模組11切斷電源訊號之輸入,使得主機板20無法接收系統電源訊號,而完全失去電源。After the capacitor C1 is charged to a high potential, the gate G of the first switching module Q1 also reaches a high potential, and the source S and the drain D are turned off. In this way, the switching control module 11 can be controlled to cut off the input of the power signal, so that the motherboard 20 cannot receive the system power signal and completely loses power.
被切斷系統電源訊號後,回復控制模組12之第二開關模組Q2立即進行步驟305:自動控制電容進行放電。After the system power signal is cut off, the second switch module Q2 of the recovery control module 12 immediately proceeds to step 305: automatically controlling the capacitor to discharge.
在第一開關模組Q1之源極S與汲極D被切斷導通後,系統電源訊號即無法傳送到主機板20,因此第二開關模組Q2亦無法接收到系統電源訊號。在此情況之下,電容C1因無法再接收到系統電源訊號之輸入,所以會對電阻R1慢慢放電而降至低電位。After the source S and the drain D of the first switch module Q1 are cut off and turned on, the system power signal cannot be transmitted to the motherboard 20, so the second switch module Q2 cannot receive the system power signal. In this case, since the capacitor C1 can no longer receive the input of the system power signal, the resistor R1 is slowly discharged to a low potential.
最後進行步驟306:控制切換控制模組恢復輸出系統電源訊號。Finally, step 306 is executed to control the switching control module to resume the output system power signal.
在電容C1降至低電位時,閘極G亦同時降至低電位,而使得源極S與汲極D導通。因此第一開關模組Q1即可重新傳輸系統電源訊號至主機板20。When the capacitor C1 falls to a low potential, the gate G also drops to a low potential at the same time, so that the source S and the drain D are turned on. Therefore, the first switch module Q1 can retransmit the system power signal to the motherboard 20.
並且此時第二開關模組Q2之基極B係與步驟301相同,會回復至高電位。因此在重新傳輸系統電源訊號後,第二開關模組Q2並不導通,所以電容C1不會再次充電。At this time, the base B of the second switch module Q2 is the same as step 301, and returns to a high potential. Therefore, after the system power signal is retransmitted, the second switch module Q2 is not turned on, so the capacitor C1 is not charged again.
如此一來,主機板20可以重新接收到供其待命之系統電源訊號,電腦系統1即可完成整體重設之流程。In this way, the motherboard 20 can re-receive the system power signal for the standby, and the computer system 1 can complete the overall reset process.
此處需注意的是,本發明之整體重設之方法並不以上述之步驟次序為限,只要能達成本發明之目的,上述之步驟次序亦可加以改變。It is to be noted that the method of the overall resetting of the present invention is not limited to the order of the above steps, and the order of the above steps may be changed as long as the object of the present invention can be achieved.
藉由上述的方法及電路,使用者即可方便地對電腦系統1進行整體重設,可解決先前技術的缺失。With the above method and circuit, the user can conveniently reset the computer system 1 as a whole, which can solve the lack of the prior art.
綜上所陳,本發明無論就目的、手段及功效,在在均顯示其迥異於習知技術之特徵,懇請 貴審查委員明察, 早日賜准專利,俾嘉惠社會,實感德便。惟應注意的是,上述諸多實施例僅係為了便於說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。In summary, the present invention, regardless of its purpose, means, and efficacy, is intrinsically distinguished from the characteristics of the prior art, and is requested to be reviewed by the review committee. As soon as the patents were granted, the company was in a good position. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.
1‧‧‧電腦系統1‧‧‧ computer system
10‧‧‧整體重設電路10‧‧‧Overtalation reset circuit
11‧‧‧切換控制模組11‧‧‧Switching control module
12‧‧‧回復控制模組12‧‧‧Response control module
20‧‧‧主機板20‧‧‧ motherboard
30‧‧‧電源供應裝置30‧‧‧Power supply unit
40‧‧‧控制訊號產生模組40‧‧‧Control signal generation module
Q1‧‧‧第一開關模組Q1‧‧‧First switch module
S‧‧‧源極S‧‧‧ source
D‧‧‧汲極D‧‧‧汲
G‧‧‧閘極G‧‧‧ gate
Q2‧‧‧第二開關模組Q2‧‧‧Second switch module
E‧‧‧集極E‧‧‧集极
C‧‧‧射極C‧‧‧射极
B‧‧‧基極B‧‧‧ base
C1、C2‧‧‧電容C1, C2‧‧‧ capacitor
R1、R2、R3‧‧‧電阻R1, R2, R3‧‧‧ resistance
圖1係本發明具有整體重設電路之電腦系統之架構圖。1 is a block diagram of a computer system having an overall reset circuit of the present invention.
圖2係本發明整體重設電路之電路圖。2 is a circuit diagram of the overall reset circuit of the present invention.
圖3係本發明整體重設之方法之步驟流程圖。3 is a flow chart showing the steps of the method of overall resetting of the present invention.
1‧‧‧電腦系統1‧‧‧ computer system
10‧‧‧整體重設電路10‧‧‧Overtalation reset circuit
11‧‧‧切換控制模組11‧‧‧Switching control module
12‧‧‧回復控制模組12‧‧‧Response control module
20‧‧‧主機板20‧‧‧ motherboard
30‧‧‧電源供應裝置30‧‧‧Power supply unit
40‧‧‧控制訊號產生模組40‧‧‧Control signal generation module
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99108021A TWI418973B (en) | 2010-03-18 | 2010-03-18 | Overall reset circuit, computer system with overall reset circuit and overall reset method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99108021A TWI418973B (en) | 2010-03-18 | 2010-03-18 | Overall reset circuit, computer system with overall reset circuit and overall reset method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201133212A TW201133212A (en) | 2011-10-01 |
| TWI418973B true TWI418973B (en) | 2013-12-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW99108021A TWI418973B (en) | 2010-03-18 | 2010-03-18 | Overall reset circuit, computer system with overall reset circuit and overall reset method thereof |
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| TW (1) | TWI418973B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW526409B (en) * | 1998-12-07 | 2003-04-01 | Koninkl Philips Electronics Nv | Reset-out circuit with feedback capability |
| US20080307240A1 (en) * | 2007-06-08 | 2008-12-11 | Texas Instruments Incorporated | Power management electronic circuits, systems, and methods and processes of manufacture |
| TW200912624A (en) * | 2007-09-06 | 2009-03-16 | Inventec Corp | Power switch device |
| TW200951702A (en) * | 2008-06-13 | 2009-12-16 | Hon Hai Prec Ind Co Ltd | Control circuit for power supply |
-
2010
- 2010-03-18 TW TW99108021A patent/TWI418973B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW526409B (en) * | 1998-12-07 | 2003-04-01 | Koninkl Philips Electronics Nv | Reset-out circuit with feedback capability |
| US20080307240A1 (en) * | 2007-06-08 | 2008-12-11 | Texas Instruments Incorporated | Power management electronic circuits, systems, and methods and processes of manufacture |
| TW200912624A (en) * | 2007-09-06 | 2009-03-16 | Inventec Corp | Power switch device |
| TW200951702A (en) * | 2008-06-13 | 2009-12-16 | Hon Hai Prec Ind Co Ltd | Control circuit for power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201133212A (en) | 2011-10-01 |
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