TWI418067B - A crystal oscillator with a layout structure for miniaturized dimensions - Google Patents
A crystal oscillator with a layout structure for miniaturized dimensions Download PDFInfo
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- H—ELECTRICITY
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Description
本發明係有關一種壓電裝置,特別是有關一種振盪器壓電裝置。The present invention relates to a piezoelectric device, and more particularly to an oscillator piezoelectric device.
利用石英晶體壓電元件作為振盪器是目前精確性和穩定性最佳的振盪器,國際電工委員會(IEC)將石英晶體壓電元件振盪器分為4類:石英時脈晶體振盪器(Simple Package Crystal Oscillator,SPXO)、電壓控制石英晶體振盪器(Voltage Controlled Crystal Oscillator,VCXO)、溫度補償石英晶體振盪器(Temperature Compensated Crystal Oscillator,TCXO)、恆溫槽控制石英晶體振盪器(Oven Controlled Crystal Oscillator,OCXO),隨著電子產業的蓬勃發展,電子產品進入多功能、高性能及輕巧化的研發方向,封裝技術為了滿足半導體晶片高積集度以及微型化的封裝要求,過去的線路佈局方式已不敷使用,過去習知之振盪器線路佈局方式,可參閱第1A圖至第1D圖,第1A圖及第1B圖以說明習知之振盪器圖案化線路示意圖及電性接點示意圖,第1C圖及第1D圖以說明尺寸微型化之振盪器圖案化線路示意圖及電性接點示意圖。如第1A圖及第1B圖所示,習知晶體振盪器10之線路佈局,由於在過去晶體振盪集成電路12及平台14面積尺寸較大,在平台14之材料強度可允許之壁厚下,可有較大之凹槽空間,故可具有較大使用之佈局空間,在平台14之製程能力不造成複數圖案化線路16彼此之間短路的情況下,圖案化線路16得以進行佈局電性接點18在晶體振盪集成電路12周圍,而在壓電元件進行測試的製程過程當中,所需圖案化電性單元17也會具有足夠的接觸面積,因此壓電元件在測試製程過程中可達到一定的良率。接續如第1C圖及第1D圖所示,當晶體振盪器10之尺寸再進一步微型化的發展之下,以習知技藝下設計的電性接點18採取佈局在晶體振盪集成電路12的周圍,因為凹槽空間之侷限,以及平台14之製程能力限制,將使得壓電元件製程中必要之圖案化電性單元17的接觸面積變得非常地狹小,而圖案化電性單元17接觸面積狹小,進而造成壓電元件在測試製程有難以進行測試的困境而產生測試上的良率不佳之缺失。因此,如何提高封裝基板在有限空間裡之佈線密度以達到微型化的需求,並取得圖案化電性單元之面積最大化即為本發明之欲研究改善之方向所在。The use of quartz crystal piezoelectric elements as oscillators is currently the best oscillator for accuracy and stability. The International Electrotechnical Commission (IEC) classifies quartz crystal piezoelectric element oscillators into four categories: quartz clock crystal oscillators (Simple Package) Crystal Oscillator, SPXO), Voltage Controlled Crystal Oscillator (VCXO), Temperature Compensated Crystal Oscillator (TCXO), Oven Controlled Crystal Oscillator (OCXO) With the booming development of the electronics industry, electronic products have entered the direction of multi-functional, high-performance and lightweight research and development. In order to meet the high integration of semiconductor wafers and miniaturized packaging requirements, the past layout of the circuit is insufficient. For the conventional oscillator circuit layout, refer to FIG. 1A to FIG. 1D, FIG. 1A and FIG. 1B to illustrate a schematic diagram of a conventional oscillator patterned circuit and an electrical contact diagram, FIG. 1C and FIG. 1D diagram to illustrate the schematic diagram of the patterned circuit of the miniaturized oscillator and the schematic diagram of the electrical contacts. As shown in FIG. 1A and FIG. 1B, the circuit layout of the conventional crystal oscillator 10 is due to the fact that in the past, the crystal oscillation integrated circuit 12 and the platform 14 have a large area, and the wall thickness of the substrate 14 is allowed to be allowed. There may be a large groove space, so that the layout space of the larger use can be used. In the case where the process capability of the platform 14 does not cause the plurality of patterned lines 16 to be short-circuited with each other, the patterned circuit 16 can be electrically connected. Point 18 is around the crystal oscillation integrated circuit 12, and during the process of testing the piezoelectric element, the required patterned electrical unit 17 also has a sufficient contact area, so that the piezoelectric element can reach a certain level during the test process. Yield. As shown in FIG. 1C and FIG. 1D, when the size of the crystal oscillator 10 is further miniaturized, the electrical contacts 18 designed by the prior art are arranged around the crystal oscillation integrated circuit 12. Because of the limitation of the groove space and the limitation of the process capability of the platform 14, the contact area of the patterned patterned electrical unit 17 in the piezoelectric element process is made very narrow, and the contact area of the patterned electrical unit 17 is small. This in turn causes the piezoelectric component to have a difficult test in the test process and the lack of good yield on the test. Therefore, how to increase the wiring density of the package substrate in a limited space to achieve miniaturization, and to maximize the area of the patterned electrical unit is the direction of the research and improvement of the present invention.
有鑑於此,本發明係針對上述之問題,提出一種針對微型化尺寸設有佈局結構之晶體振盪器,以解決石英時脈晶體振盪器、可程式化石英晶體振盪器、電壓控制石英晶體振盪器及溫度補償晶體振盪器因過去習知技藝線路佈局難以微型化之缺失。In view of the above, the present invention is directed to the above problem, and proposes a crystal oscillator having a layout structure for miniaturization size to solve a quartz clock crystal oscillator, a programmable quartz crystal oscillator, and a voltage controlled quartz crystal oscillator. And the temperature-compensated crystal oscillator is difficult to miniaturize due to the conventional circuit line layout.
本發明之主要目的係在提供一種針對微型化尺寸設有佈局結構之晶體振盪器,利用每一第一圖案化線路之電性接點以及晶體振盪集成電路所相連接之電性導通接點於第一凹槽之中心對稱集中,因此能在有限之平台的空間裡,得以提高線路佈局之靈活性,以解決過去習知晶體振盪器因微型化所造成封裝製程上的所造成低良率之缺失。The main object of the present invention is to provide a crystal oscillator having a layout structure for a miniaturized size, using an electrical contact of each of the first patterned lines and an electrical conduction contact connected to the crystal oscillation integrated circuit. The center of the first groove is symmetrically concentrated, so that the flexibility of the layout of the circuit can be improved in a limited space of the platform, so as to solve the low yield of the conventional crystal oscillator caused by miniaturization. Missing.
本發明之另一目的係在提供一種針對微型化尺寸設有佈局結構之晶體振盪器,利用電性接點以及電性導通接點由外向第一凹槽之中心對稱集中,且使電性接點位於晶體振盪集成電路下方處,因此第一凹槽可騰讓出足夠的佈局空間,可使至少二圖案化電性單元之圖案可擴張至最大化,因此本發明得以解決過去習知在微型化尺寸之有限空間下,因為必須預留壓電元件製程中必要測試腳位,無法提供晶體振盪器在測試製程過程中所必要接觸腳位能具有足夠的接觸面積,而造成測試製程上的良率不佳。Another object of the present invention is to provide a crystal oscillator having a layout structure for a miniaturized size, wherein the electrical contact and the electrical conduction contact are symmetrically concentrated from the center of the outward first groove, and the electrical connection is made. The point is located below the crystal oscillation integrated circuit, so that the first groove can allow sufficient layout space to maximize the pattern of at least two patterned electrical units, so the present invention is solved in the past. In the limited space of the size, because the necessary test pins must be reserved in the process of the piezoelectric component, it is impossible to provide the crystal oscillator with sufficient contact area during the test process, which results in a good test process. The rate is not good.
本發明之再一目的係在提供一種針對微型化尺寸設有佈局結構之晶體振盪器,晶體振盪集成電路之腳位透過覆晶封裝與平台上的圖案化線路接合,因此透過晶體振盪集成電路腳位之間的相對位置縮短,得以具有較高的量產實現性,微型化將更能帶來成本下降,此微型化之佈局結構,將使得製程之可實現性大增但依舊可持續晶體振盪集成電路之尺寸下降以取得成本優勢。相對降低覆晶封裝的平台之平行度要求,進而降低平台之規格要求與成本。A further object of the present invention is to provide a crystal oscillator having a layout structure for a miniaturized size. The pin of the crystal oscillation integrated circuit is bonded to the patterned line on the platform through the flip chip package, thereby oscillating the integrated circuit through the crystal. The relative position between the bits is shortened, which enables higher mass production realization, and miniaturization will bring lower cost. This miniaturized layout structure will greatly increase the achievability of the process but still sustain crystal oscillation. The size of the integrated circuit is reduced to achieve cost advantages. Relatively reduce the parallelism requirement of the platform of the flip chip package, thereby reducing the specification requirements and cost of the platform.
為達上述之目的,本發明提供一種針對微型化尺寸設有佈局結構之晶體振盪器,至少包括:具有第一凹槽及第二凹槽之平台,複數內部引線,佈局在平台內部,晶體振盪集成電路,設置於第一凹槽近中央位置上,晶體振盪集成電路電性連接內部引線,以及複數第一圖案化線路,佈局於第一凹槽,電性連接內部引線,其中,每一第一圖案化線路具有一電性接點,電性接點由外向第一凹槽之中心對稱集中,且使電性接點位於晶體振盪集成電路下方處。In order to achieve the above object, the present invention provides a crystal oscillator having a layout structure for a miniaturized size, comprising at least: a platform having a first groove and a second groove, a plurality of internal leads, arranged inside the platform, and crystal oscillation The integrated circuit is disposed at a near central position of the first recess, the crystal oscillation integrated circuit is electrically connected to the inner lead, and the plurality of first patterned lines are disposed in the first recess, electrically connected to the inner lead, wherein each A patterned circuit has an electrical contact, and the electrical contacts are symmetrically concentrated from the center of the outwardly facing first recess, and the electrical contacts are located below the crystal oscillation integrated circuit.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
本發明係為一種針對微型化尺寸設有佈局結構之晶體振盪器,可運用在石英時脈晶體振盪器、可程式化石英晶體振盪器、電壓控制石英晶體振盪器以及溫度補償石英晶體振盪器之佈局結構,在進行線路佈局時,利用圖案化線路所具有電性接點由外往第一凹槽之中心對稱集中,且使電性接點位於晶體振盪集成電路下方處,因此能在有限之平台的空間裡,得以提高線路佈局之靈活性,因此第一凹槽可騰讓出足夠的佈局空間,可使至少二圖案化電性單元之的圖案可擴張至最大化,而增加晶體振盪器在進行測試壓電元件所須之圖案面積,進而提高晶體振盪器之測試良率。利用本發明可使得振盪器不再受困於過去所採用電性接點佈局在晶體振盪集成電路周圍而造成佈線空間不足,使得晶體振盪器之圖案化線路難以微型化之窘境。The invention relates to a crystal oscillator with a layout structure for miniaturization, which can be applied to a quartz clock crystal oscillator, a programmable quartz crystal oscillator, a voltage controlled quartz crystal oscillator and a temperature compensated quartz crystal oscillator. The layout structure, when the circuit layout is performed, the electrical contacts of the patterned circuit are symmetrically concentrated from the outside to the center of the first groove, and the electrical contacts are located below the crystal oscillation integrated circuit, so In the space of the platform, the flexibility of the layout of the circuit can be improved, so that the first groove can allow sufficient layout space, and the pattern of at least two patterned electrical units can be expanded to maximize the crystal oscillator. The area of the pattern required to test the piezoelectric element is increased, thereby improving the test yield of the crystal oscillator. By using the invention, the oscillator can no longer be trapped in the environment where the electrical contact arrangement used in the past is arranged around the crystal oscillation integrated circuit, resulting in insufficient wiring space, making the patterned circuit of the crystal oscillator difficult to miniaturize.
本發明之實施方式,首先,同時參閱第2圖、第3A圖及第3B圖,以說明本發明之晶體振盪器立體圖、圖案化線路示意圖及電性接點示意圖,如第2圖所示,本發明提出一種設有佈局結構之晶體振盪器20,至少包括:可以選用陶瓷材質以進行製作之平台22,平台22具有第一凹槽23,第一凹槽23上設有複數第一圖案化線路24,在此的第一圖案化線路之實施態樣可使用鈦、鋁、金、鎳、銅、銀、鉑、鋨、鋰、鉻、銫或鎢之單層與多層金屬結構材質予以施作;如第3A圖及第3B圖所示,其中每一個第一圖案化線路24皆具有一個電性接點26,電性接點26由外往第一凹槽23之中心對稱集中,且使電性接點26位於晶體振盪集成電路28下方處,在複數圖案化線路24當中設有至少二圖案化電性單元30,圖案化電性單元30之一端係為電性接點26,電性圖案化單元30於另一端係為可進行測試之圖案,由於電性接點26由外往第一凹槽23之中心對稱集中,因此第一凹槽23可騰讓出有足夠的佈局面積,可使得圖案化電性單元30另一端之圖案面積擴張至最大化,因此,透過此線路佈局方式將可提高晶體振盪器之測試良率,其中在此電性接點26可使用為電性接觸墊(land)、凸塊焊墊(bump pad)或打線焊墊(wire bonding pad)等封裝方法進行構裝,其中凸塊焊墊可以是金凸塊(Au Bump)或是錫凸塊(Solder Bump),而第一圖案化線路24之圖案於此實施方式及圖式上的說明是以形成一凸形狀進行解釋,但第一圖案化線路24之圖案形狀並非為限制條件,亦可呈現其他如複數多邊形,甚至至多可成為一圓形。另外,本發明所揭露之複數第一圖案化線路24所具有的電性接點26之技術特徵,在此實施方式是以六個第一圖案化線路24即具有以六個電性接點26做為舉例說明,然而,實施方式若是改以四個電性接點或是六個以上電性接點之設有佈局結構之晶體振盪器(圖未示),其實施方式之技術特徵亦同於實施方式所記載:將每一個第一圖案化線路24之電性接點26由外往第一凹槽23之中心點對稱集中,且使電性接點26位於於晶體振盪集成電路28之下方處,複數第一圖案化線路24皆至少有二圖案化電性單元30,圖案化電性單元30之一端係為電性接點26,於另一端之圖案可擴張至最大化,至於其他結構之部份,在此則不再贅述。Embodiments of the present invention firstly refer to FIG. 2, FIG. 3A, and FIG. 3B to illustrate a perspective view of a crystal oscillator, a schematic circuit diagram, and an electrical contact diagram of the present invention, as shown in FIG. The present invention provides a crystal oscillator 20 having a layout structure, which comprises at least a platform 22 which can be made of a ceramic material, the platform 22 has a first recess 23, and the first recess 23 is provided with a plurality of first patterns. The circuit 24, the first patterned circuit embodiment can be applied by using a single layer and a plurality of metal structures of titanium, aluminum, gold, nickel, copper, silver, platinum, rhodium, lithium, chromium, lanthanum or tungsten. As shown in FIG. 3A and FIG. 3B , each of the first patterned lines 24 has an electrical contact 26 , and the electrical contacts 26 are symmetrically concentrated from the outside to the center of the first recess 23 , and The electrical contact 26 is disposed below the crystal oscillation integrated circuit 28, and at least two patterned electrical units 30 are disposed in the plurality of patterned circuits 24, and one end of the patterned electrical unit 30 is an electrical contact 26, and the electrical The patterning unit 30 is testable at the other end. The pattern, since the electrical contacts 26 are symmetrically concentrated from the outside to the center of the first groove 23, the first groove 23 can allow sufficient layout area to make the pattern area of the other end of the patterned electrical unit 30 Expanding to maximize, therefore, the test pattern of the crystal oscillator can be improved by this line layout, wherein the electrical contact 26 can be used as an electrical contact pad or a bump pad. Or a packaging method such as a wire bonding pad, wherein the bump pad may be a gold bump or a solder bump, and the pattern of the first patterned line 24 is The description of the embodiment and the drawings is explained by forming a convex shape, but the pattern shape of the first patterned line 24 is not a limitation, and may be other such as a plurality of polygons, or even at most a circle. In addition, the technical features of the electrical contacts 26 of the plurality of first patterned lines 24 disclosed in the present invention are in this embodiment with six first patterned lines 24 having six electrical contacts 26 . For example, if the embodiment is a crystal oscillator (not shown) having a layout structure with four electrical contacts or six or more electrical contacts, the technical features of the embodiments are the same. As described in the embodiment, the electrical contacts 26 of each of the first patterned lines 24 are symmetrically concentrated from the center of the first recess 23, and the electrical contacts 26 are located at the crystal oscillation integrated circuit 28. Below, the plurality of first patterned lines 24 have at least two patterned electrical units 30, one end of the patterned electrical unit 30 is an electrical contact 26, and the pattern at the other end can be expanded to maximize, as for other Part of the structure will not be described here.
同時參閱第4圖、第5A圖及第5B圖,以說明本發明之晶體振盪器主要元件剖視圖、底視立體分解圖及上視立體分解圖,如第4圖所示,本發明之設有佈局結構之晶體振盪器20所採用的平台22係為具有第一凹槽23及第二凹槽33之雙凹槽結構,複數內部引線34佈局在平台22內部,以及利用可為石英時脈晶體振盪器控制晶片、可程式化石英晶體振盪器控制晶片、電壓控制石英晶體振盪器控制晶片或是溫度補償石英晶體振盪器控制晶片其中之一類型的晶體振盪集成電路28,設置於第一凹槽23接近中央位置上;如第5A圖所示,晶體振盪集成電路28具有複數電性導通接點35透過交連元件36可電性連接至電性接點26,而在此的交連元件36可使用為電性接觸墊(land)、凸塊焊墊(bump pad)或打線焊墊(wire bonding pad)等封裝方法進行構裝,其中凸塊焊墊可以是金凸塊(Au Bump)或是錫凸塊(Solder Bump);如第5B圖所示,本發明設有至少二第二圖案化線路37,佈局於第二凹槽33,其中第二凹槽33上可使用具有高導電性之導電銀膠以製作成第一耦合元件38及第二耦合元件40,本發明可使用石英晶片做為壓電元件41,設置於該第二凹槽33中,並且可利用物理氣相沉積或化學氣相沉積或濺鍍之製造方式進行沉積第一塗層電極42及第二塗層電極44於壓電元件41上,隨後,如第4圖、第5A圖及第5B圖所示,第二圖案化線路37透過內部引線34可電性連接圖案化電性單元30、第一耦合元件38及第一塗層電極42,另一第二圖案化線路37’同樣透過內部引線34可電性連接另一個圖案化電性單元30、第二耦合元件40及第二塗層電極44,因此壓電元件41得以產生壓電效應,並透過至少二圖案化電性單元30進行測試,完成壓電元件41之製程測試,其中在此的第二圖案化線路、第一塗層電極及第二塗層電極之實施態樣可使用鈦、鋁、金、鎳、銅、銀、鉑、鋨、鋰、鉻、銫或鎢之單層與多層金屬結構材質;如第4圖及第5A圖所示,本發明可使用底膠46可固定並強化晶體振盪集成電路28接合強度於第一凹槽23上,並且可保護第一凹槽23、晶體振盪集成電路28、電性導通接點35及該交連元件36,如第4圖及第5A圖所示,本發明設有複數導通電極48,設置於平台22之表面50上,以電性連接內部引線34並電性連接一外部電路(圖未示),因此,晶體振盪集成電路28可藉由外部電路(圖未示)取得一外部電壓源與石英時脈晶體振盪器、可程式化石英晶體振盪器、電壓控制石英晶體振盪器或溫度補償石英晶體振盪器之不同類型之晶體振盪器20形成振盪迴路,透過內部引線34電性連接壓電元件41可驅動並進行控制壓電元件41產生頻率信號或是可使溫度補償石英晶體振盪器進行補償壓電元件41之溫度效應,並使壓電元件41產生壓電效應而得到一參考頻率並且透過導通電極48可輸出一參考頻率至外部電路(圖未示),另,在此之導通電極48之實施態樣可使用鈦、鋁、金、鎳、銅、銀、鉑、鋨、鋰、鉻、銫或鎢之單層與多層金屬結構材質予以施作;最後如第5B圖所示,本發明可利用可為金屬材質之封裝板52,設置於平台22之金屬表面56上,可進行密封第二凹槽33以及屏蔽電磁干擾(ElectroMagnetic Interference,EMI)。4, 5A, and 5B, in order to explain the main components of the crystal oscillator of the present invention, a bottom perspective exploded view and a top perspective exploded view, as shown in FIG. 4, the present invention is provided. The platform 22 used in the crystal oscillator 20 of the layout structure is a double groove structure having a first groove 23 and a second groove 33. The plurality of inner leads 34 are arranged inside the platform 22, and the quartz clock crystal can be utilized. An oscillator control chip, a programmable quartz crystal oscillator control chip, a voltage controlled quartz crystal oscillator control chip, or a temperature compensated quartz crystal oscillator control chip, one of the types of crystal oscillation integrated circuits 28, disposed in the first groove 23 is close to the central position; as shown in FIG. 5A, the crystal oscillation integrated circuit 28 has a plurality of electrically conductive contacts 35 electrically connected to the electrical contacts 26 through the interconnecting elements 36, and the interconnecting elements 36 can be used therein. For mounting methods such as electrical contact pads, bump pads, or wire bonding pads, the bump pads can be gold bumps or tin bumps. Bump (Solder Bump); as shown in FIG. 5B, the present invention is provided with at least two second patterned lines 37 disposed in the second recess 33, wherein the second recess 33 can be made of conductive silver paste with high conductivity. As the first coupling element 38 and the second coupling element 40, the present invention can use a quartz wafer as the piezoelectric element 41, is disposed in the second groove 33, and can utilize physical vapor deposition or chemical vapor deposition or sputtering. The plating method is performed to deposit the first coating electrode 42 and the second coating electrode 44 on the piezoelectric element 41, and then, as shown in FIGS. 4, 5A and 5B, the second patterned line 37 is transmitted. The inner lead 34 is electrically connected to the patterned electrical unit 30, the first coupling element 38 and the first coating electrode 42, and the other second patterned line 37' is also electrically connected to another patterned electric through the inner lead 34. The piezoelectric element 41 is subjected to a piezoelectric effect and is tested by at least two patterned electrical units 30 to complete the process test of the piezoelectric element 41. Wherein the second patterned line, the first coated electrode And the second coating electrode can be used as a single layer and a plurality of metal structure materials of titanium, aluminum, gold, nickel, copper, silver, platinum, rhodium, lithium, chromium, lanthanum or tungsten; as shown in FIG. 4 and As shown in FIG. 5A, the primer 46 can be used to fix and strengthen the bonding strength of the crystal oscillation integrated circuit 28 on the first recess 23, and can protect the first recess 23, the crystal oscillation integrated circuit 28, and the electrical connection. Point 35 and the interconnecting component 36. As shown in FIG. 4 and FIG. 5A, the present invention is provided with a plurality of conductive electrodes 48 disposed on the surface 50 of the platform 22 to electrically connect the internal leads 34 and electrically connect an external portion. The circuit (not shown), therefore, the crystal oscillator integrated circuit 28 can obtain an external voltage source and a quartz clock crystal oscillator, a programmable quartz crystal oscillator, and a voltage controlled quartz crystal oscillation by an external circuit (not shown). Different types of crystal oscillators 20 of the temperature compensated quartz crystal oscillator form an oscillating circuit, and the piezoelectric element 41 is electrically connected through the inner lead 34 to drive and control the piezoelectric element 41 to generate a frequency signal or to make a temperature compensated quartz. Crystal oscillator The row compensates the temperature effect of the piezoelectric element 41, and the piezoelectric element 41 generates a piezoelectric effect to obtain a reference frequency and transmits a reference frequency to the external circuit (not shown) through the conduction electrode 48, and further, is turned on here. The embodiment of the electrode 48 can be applied by using a single layer and a multi-layer metal structure material of titanium, aluminum, gold, nickel, copper, silver, platinum, rhodium, lithium, chromium, lanthanum or tungsten; finally, as shown in FIG. 5B The present invention can be provided on the metal surface 56 of the platform 22 by using a metal-clad package board 52, which can seal the second recess 33 and shield electromagnetic interference (EMI).
參閱第6A圖及第6B圖以說明本發明之晶體振盪器增設金屬環立體分解圖及增設金屬環剖視圖,如圖所示,在平台22之金屬表面56上利用封裝板52即可達到屏蔽電磁干擾之效果,但本發明可透過增設金屬環58,設置於金屬表面56上與封裝板52之間,再以封裝板52固接金屬表面56,以增加電磁干擾屏蔽效果與高溫封銲過程中的高溫之熱應力緩衝。6A and 6B are used to illustrate a perspective view of the metal ring of the present invention and a cross-sectional view of the additional metal ring. As shown, the shielding plate can be used on the metal surface 56 of the platform 22 to achieve shielding electromagnetic The effect of the interference, but the present invention can be disposed between the metal surface 56 and the package board 52 through the additional metal ring 58, and then the metal surface 56 is fixed by the package board 52 to increase the electromagnetic interference shielding effect and the high temperature sealing process. The high temperature thermal stress buffer.
本發明所採用之壓電元件材質係為石英晶片,其中石英晶片係為AT角度切割晶片或是音叉晶片(Tuning Fork);其中AT角度切割晶片是在各種不同種類的切割角度方式中的一種,AT角度切割的石英晶片適用在數MHz到數佰MHz的頻率範圍,是石英晶片應用範圍最廣範及使用數量最多的一種切割應用方式,也是大量生產的技術上也是很好達成的一種作業方式。The piezoelectric component used in the present invention is a quartz wafer, wherein the quartz wafer is an AT angle-cut wafer or a Tuning Fork; wherein the AT angle-cut wafer is one of various types of cutting angles. The AT angle-cut quartz wafer is suitable for the frequency range from several MHz to several 佰MHz. It is the most widely used and widely used cutting application method for quartz wafers. It is also a technically well-achieved operation method for mass production. .
惟以上所述之實施例僅為本發明之較佳實施例,藉由實施例說明本發明之特點,其目的在使熟習該技術者能暸解本發明之內容並據以實施,並非用以局限本發明實施之範圍。舉凡運用本發明申請專利範圍所述之構造、形狀、特徵及精神所為之均等變化及修飾,皆應包括於本發明申請專利之範圍內。The embodiments described above are only the preferred embodiments of the present invention, and the features of the present invention are described by the embodiments, which are intended to enable those skilled in the art to understand the present invention and The scope of the practice of the invention. Equivalent changes and modifications to the structures, shapes, features, and spirits of the present invention should be included in the scope of the present invention.
10...晶體振盪器10. . . Crystal oscillator
12...晶體振盪集成電路12. . . Crystal oscillation integrated circuit
14...平台14. . . platform
16...圖案化線路16. . . Patterned line
17...圖案化電性單元17. . . Patterned electrical unit
18...電性接點18. . . Electrical contact
20...晶體振盪器20. . . Crystal oscillator
22...平台twenty two. . . platform
23...第一凹槽twenty three. . . First groove
24...第一圖案化線路twenty four. . . First patterned line
26...電性接點26. . . Electrical contact
28...晶體振盪集成電路28. . . Crystal oscillation integrated circuit
30...圖案化電性單元30. . . Patterned electrical unit
33...第二凹槽33. . . Second groove
34...內部引線34. . . Internal lead
35...電性導通接點35. . . Electrically conductive contact
36...交連元件36. . . Interconnecting component
37...第二圖案化線路37. . . Second patterned circuit
37’...第二圖案化線路37’. . . Second patterned circuit
38...第一耦合元件38. . . First coupling element
40...第二耦合元件40. . . Second coupling element
41...壓電元件41. . . Piezoelectric element
42...第一塗層電極42. . . First coating electrode
44...第二塗層電極44. . . Second coated electrode
46...底膠46. . . Primer
48...導通電極48. . . Conduction electrode
50...表面50. . . surface
52...封裝板52. . . Package board
56...金屬表面56. . . Metal surface
58...金屬環58. . . metal ring
第1A圖為習知之晶體振盪器圖案化線路示意圖。Figure 1A is a schematic diagram of a conventional crystal oscillator patterned circuit.
第1B圖為習知之晶體振盪器電性接點示意圖。Figure 1B is a schematic diagram of a conventional crystal oscillator electrical contact.
第1C圖為尺寸微型化之晶體振盪器圖案化線路示意圖。Figure 1C is a schematic diagram of a patterned circuit of a crystal oscillator of a reduced size.
第1D圖為尺寸微型化之晶體振盪器電性接點示意圖。Figure 1D is a schematic diagram of an electrical contact of a crystal oscillator of a miniaturized size.
第2圖為本發明之晶體振盪器立體圖。Fig. 2 is a perspective view of the crystal oscillator of the present invention.
第3A圖為本發明之晶體振盪器圖案化線路示意圖。3A is a schematic diagram of a patterned circuit of a crystal oscillator of the present invention.
第3B圖為本發明之晶體振盪器電性接點示意圖。FIG. 3B is a schematic diagram of an electrical contact of the crystal oscillator of the present invention.
第4圖為本發明之晶體振盪器主要元件剖視圖。Fig. 4 is a cross-sectional view showing the main components of the crystal oscillator of the present invention.
第5A圖為本發明之晶體振盪器底視立體分解圖。Fig. 5A is a bottom perspective exploded view of the crystal oscillator of the present invention.
第5B圖為本發明之晶體振盪器上視立體分解圖。Fig. 5B is a perspective exploded view of the crystal oscillator of the present invention.
第6A圖為本發明之晶體振盪器增設金屬環立體分解圖。Fig. 6A is an exploded perspective view showing the addition of a metal ring of the crystal oscillator of the present invention.
第6B圖為本發明之晶體振盪器增設金屬環剖視圖。Fig. 6B is a cross-sectional view showing the addition of a metal ring of the crystal oscillator of the present invention.
20...晶體振盪器20. . . Crystal oscillator
22...平台twenty two. . . platform
26...電性接點26. . . Electrical contact
28...晶體振盪集成電路28. . . Crystal oscillation integrated circuit
30...圖案化電性單元30. . . Patterned electrical unit
Claims (19)
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| CN201110200064.2A CN102882488B (en) | 2011-07-15 | 2011-07-18 | Crystal oscillator with layout structure for miniaturized size |
| JP2011212822A JP5237426B2 (en) | 2011-07-15 | 2011-09-28 | Quartz crystal oscillator with ultra-small size layout structure |
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| JP2015195436A (en) * | 2014-03-31 | 2015-11-05 | 日本電波工業株式会社 | Electronic component package and piezoelectric device |
| CN106712737A (en) * | 2016-12-20 | 2017-05-24 | 广东大普通信技术有限公司 | Crystal oscillator and its production method |
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| JP4799984B2 (en) * | 2005-09-30 | 2011-10-26 | 日本電波工業株式会社 | Temperature-compensated crystal oscillator for surface mounting |
| JP2008047723A (en) * | 2006-08-17 | 2008-02-28 | Epson Toyocom Corp | Surface mounted electronic device, adjustment probe device, and method for adjusting surface mounted electronic device |
| JP5095319B2 (en) * | 2007-09-06 | 2012-12-12 | 日本電波工業株式会社 | Quartz device with monitor electrode |
| JP5210081B2 (en) * | 2008-07-31 | 2013-06-12 | 京セラクリスタルデバイス株式会社 | Piezoelectric oscillator |
| JP5210093B2 (en) * | 2008-08-30 | 2013-06-12 | 京セラクリスタルデバイス株式会社 | Piezoelectric oscillator |
| JP2010178170A (en) * | 2009-01-30 | 2010-08-12 | Kyocera Kinseki Corp | Piezoelectric oscillator |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP5237426B2 (en) | 2013-07-17 |
| TW201304219A (en) | 2013-01-16 |
| CN102882488B (en) | 2015-10-21 |
| JP2013027031A (en) | 2013-02-04 |
| CN102882488A (en) | 2013-01-16 |
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