TWI415215B - Method for fabricating shallow trench isolation - Google Patents

Abstract

A method for fabricating shallow trench isolations is provided. A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate includes a memory region and a periphery region. By using the patterned mask layer as a mask, the substrate is partially removed to form a plurality of trenches. A first liner is formed on the substrate to cover surfaces of the patterned mask layer, patterned pad layer and the trenches. After removing the first liner in the periphery region, a pull-back process is performed to the patterned mask layer, and a pull-back amount of the patterned mask layer in the periphery region is larger than a pull-back amount of the patterned mask layer in the memory region. An insulation layer is formed in the trenches to form a plurality of shallow trench isolations.

Description

Method for manufacturing shallow trench isolation structure

The present invention relates to a method of fabricating an isolation structure, and more particularly to a method of fabricating a shallow trench isolation structure.

As semiconductor technology advances, the size of components continues to shrink. Therefore, in order to prevent the occurrence of a short circuit between adjacent elements, the isolation between the elements and the elements becomes quite important. The more commonly used method today is the Shallow Trench Isolation (STI) process.

In general, the step of forming the shallow trench isolation structure includes forming a pad oxide layer and a patterned mask layer on the substrate, and then removing a portion of the substrate by using the patterned mask layer as a mask to form shallow trenches in the substrate. Then, the insulating material is filled in the shallow trench to form a shallow trench isolation structure, and the pad oxide layer and the patterned mask layer are removed by etching or the like. Wherein, the step of removing the pad oxide layer may remove a part of the shallow channel isolation structure, in particular, removing the upper corner of the shallow trench isolation structure to generate a dimple. As a result, the tunnel oxide layer or the gate oxide layer formed on the side of the shallow trench isolation structure has a problem of excessive thickness at the upper corner of the shallow trench isolation structure, so that the flash memory is The component characteristics of the body are affected.

In order to avoid the above-mentioned "corner thinning" phenomenon in the tunnel oxide layer or the gate oxide layer, one of the conventional solutions is to repair the etch damage and reduce the stress of the shallow trench after forming the shallow trench. Before the thermal oxidation process, the patterned mask layer is laterally retracted. In detail, in the formation After the shallow trench, the partially patterned mask layer is etched such that the patterned mask layer is collapsed relative to the edge of the shallow trench. Since the space left by the indentation of the patterned mask layer is subsequently filled with the insulating material for forming the shallow trench isolation structure, the insulating material of the portion can be used to delay the etching of the pad oxide layer to the shallow trench isolation structure. Damage caused by the upper corners to avoid depressions at the corners above the shallow trench isolation structure. In this way, when the tunneling oxide layer and the gate oxide layer are formed on the shallow trench isolation structure, the tunneling oxide layer and the gate oxide layer can have a thickness consistent with the main body at the corner, and there is no corner thinning phenomenon.

As the size of the memory component is increasingly reduced, the amount of shrinkage of the patterned mask layer in the memory cell region must also decrease. However, before the formation of the gate oxide layer, the peripheral region of the memory device generally receives more wet etching than the memory cell region, and limited by the operating voltage limitation, the thickness of the high voltage gate oxide layer is more difficult to reduce or The reduction is quite limited, causing the surrounding area to face the problem of insufficient shrinkage of the patterned mask layer. In other words, the corners above the shallow trench isolation structure may be recessed due to excessive exposure, so that the gate oxide layer formed on the side of the shallow trench isolation structure has an angular thinning problem and even grows in the depression. As a result, the component characteristics and reliability of the memory device are seriously deteriorated.

The present invention provides a method of fabricating a shallow trench isolation structure such that the memory component has better component characteristics.

The invention provides a method for manufacturing a shallow trench isolation structure. First of all, A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate comprises a memory cell region and a peripheral region. Next, a portion of the substrate is removed by patterning the mask layer as a mask to form a plurality of trenches. A first liner is then formed over the substrate to cover the patterned mask layer, the patterned underlayer, and the surface of the trench. Next, the first liner covering the patterned mask layer of the peripheral region, the patterned underlayer, and the surface of the trench is removed. Then, the patterned mask layer is subjected to a shrinking process such that the amount of shrinkage of the patterned mask layer in the peripheral region is greater than the amount of shrinkage of the patterned mask layer in the memory cell region. Then, an insulating layer is formed in the trench to form a plurality of shallow trench isolation structures.

In an embodiment of the invention, the first liner layer comprises an oxide layer.

In an embodiment of the invention, the material of the first liner layer comprises a high temperature oxide (HTO) or an oxide formed by tetraethosiloxane (TEOS).

In an embodiment of the invention, the first liner layer is subjected to a uniform densification process in nitrogen and at a high temperature.

In an embodiment of the invention, the step of removing the first lining covering the patterned mask layer, the patterned pad layer and the surface of the trench in the peripheral region comprises: forming a photoresist layer on the memory cell region To cover the first liner of the memory cell; and to remove the first liner of the peripheral region.

In an embodiment of the invention, the method of removing the first liner comprises a wet etching process.

In one embodiment of the invention, the shrinking process described above includes a wet etch process.

In an embodiment of the invention, before forming the first liner, A second liner is formed on the substrate to cover the patterned mask layer, the patterned underlayer, and the surface of the trench.

In an embodiment of the invention, the material of the second liner layer comprises tantalum nitride.

In an embodiment of the invention, the first liner layer is subjected to a uniform densification process in nitrogen or oxygen and at a high temperature.

In an embodiment of the present invention, when the shrinking process is performed, the patterned mask layer of the memory cell region is sequentially covered with the second liner layer and the first liner layer, and the patterned mask of the peripheral region. The layer is covered with a second liner.

Based on the above, the method of fabricating the shallow trench isolation structure of the present invention allows the patterned mask layer to have an appropriate amount of retraction in the peripheral region and the memory cell region, respectively. In this way, the depression at the upper corner of the shallow trench isolation structure can be avoided, so that the tunnel oxide layer and the gate oxide layer formed on the side of the shallow trench isolation structure can have a thickness consistent with the main body at the corner without Angle thinning phenomenon. Therefore, the memory element has better component characteristics and reliability.

The above described features and advantages of the present invention will be more apparent from the following description.

In general, since the peripheral region is usually used to form a high voltage component and a low voltage component, the peripheral oxide region is usually subjected to a larger amount of wet etching than the memory cell region before the gate oxide layer is formed, and the high voltage gate oxide layer of the peripheral region is added. The thickness is more difficult to reduce or reduce the amount is quite limited, so the problem of thinning the corner of the high-voltage gate oxide layer is also serious in the peripheral region, and the low-voltage gate oxide layer may even grow. Depression. As a result, the component characteristics and reliability of the memory element are reduced. Therefore, the present invention forms a shallow trench isolation structure for the characteristics of the peripheral region and the memory cell region of the memory device, so as to avoid problems such as thinning of the tunnel oxide layer and the gate oxide layer formed on the side of the shallow trench isolation structure. .

1A-1F are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a first embodiment of the present invention. Referring to FIG. 1A , a patterned pad layer 110 and a patterned mask layer 120 are sequentially formed on a substrate 100 . The substrate 100 includes a memory cell region 102 and a peripheral region 104 . The substrate 100 is, for example, a P-type germanium-doped substrate, an N-type germanium-based substrate, an epitaxial germanium substrate, a gallium arsenide substrate, an indium phosphide substrate, or a germanium telluride substrate. The material of the patterned underlayer 110 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method or a chemical vapor deposition method. The material of the patterned mask layer 120 is, for example, tantalum nitride, and the formation method thereof is, for example, a chemical vapor deposition method.

Referring to FIG. 1B, next, a portion of the substrate 100 is removed by patterning the mask layer 120 as a mask to form a plurality of trenches 130. In the present embodiment, the method of removing a portion of the substrate 100 is, for example, a reactive ion etching method. Then, in this embodiment, after the trench 130 is formed, a rapid thermal oxidation process (RTO) is performed on the substrate 100 and the patterned mask layer 120.

Referring to FIG. 1C, a first liner 140 is formed on the substrate 100 to cover the surface of the patterned mask layer 120, the patterned pad layer 110, and the trench 130. In other words, the first liner 140 simultaneously covers the memory cell The patterned mask layer 120, the patterned underlayer 110, and the surface of the trench 130 of the region 102 and the peripheral region 104. In the present embodiment, the first liner 140 includes, for example, an oxide layer, wherein the oxide layer is, for example, an oxide including high temperature oxide (HTO) or tetraethosiloxane (TEOS). The thickness of the first underlayer 140 is, for example, about 150 angstroms. The method of forming the first liner 140 is, for example, a low pressure chemical vapor deposition process.

In this embodiment, after the first liner layer 140 is formed, the first liner layer 140 is further subjected to a uniform densification process. In the present embodiment, the densification process is carried out, for example, under nitrogen and at a high temperature, wherein the high temperature is, for example, about 900 °C. In particular, in one embodiment, the material of the first liner 140 includes, for example, ruthenium oxide, and the densification process enables the first liner 140 to be in hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerol. The etching rate in the etching solution is as close as possible to tantalum nitride.

Referring to FIG. 1D, the first liner 140 covering the patterned mask layer 120 of the peripheral region 104, the patterned pad layer 110, and the surface of the trench 130 is removed. In detail, in this embodiment, for example, a photoresist layer 150 is formed on the memory cell region 102 to cover the first liner layer 140 of the memory cell region 102, and then the first liner of the peripheral region 104 is removed. Layer 140. As a result, since the first liner 140 located in the memory cell region 102 is covered by the photoresist layer 150 to be protected, it can be retained, and the first liner layer 140 located in the peripheral region 104 is removed. The method of removing the first underlayer 140 includes, for example, a wet etching process, such as using an etchant including Buffer Hydrofluoric Acid (BHF).

Please refer to FIG. 1E, and then the photoresist layer 150 is removed and cleaned. To remove the residue. Next, the patterned mask layer 120 is subjected to a shrinking process such that the shrinkage amount C1 of the patterned mask layer 120 of the peripheral region 104 is greater than the shrinkage amount C2 of the patterned mask layer 120 of the memory cell region 102. In the present embodiment, the shrinking process includes, for example, a wet etching process such as using an etching solution including hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerin. The patterned mask layer 120 of the memory cell region 102 is covered by the first liner layer 140, so that the patterned mask layer 120 of the memory cell region 102 is compared to the patterned mask layer 120 of the peripheral region 104. The amount of contraction C2 will be less than the amount of contraction C1 of the patterned mask layer 120 of the peripheral zone 104. In particular, the peripheral mask 104 and the patterned mask layer 120 of the memory cell region 102 can have appropriate amounts of contractions C1, C2, respectively, by controlling parameters such as the thickness of the liner and the etching time in the shrink process. Moreover, the thickness of the patterned mask layer 120 of the peripheral region 104 may be less than the thickness of the patterned mask layer 120 of the memory cell region 102.

Referring to FIG. 1F, an insulating layer is formed in the trench 130 to form a plurality of shallow trench isolation structures 170. In this embodiment, for example, the substrate 100 is first oxidized to form an oxide layer 160 on the surface of the trench 130, and then an insulating layer is formed in the trench 130 to form a shallow trench isolation structure 170. The material of the insulating layer is, for example, cerium oxide, and the forming method thereof is, for example, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or high density plasma chemical vapor deposition (HDPCVD). After the insulating layer is deposited, it is planarized by chemical mechanical polishing (CMP).

After the shallow trench isolation structure 170 is formed, the removal of the patterned mask layer 120 and the patterned pad layer 110 is continued to form in the memory cell region 102. The steps of tunneling the oxide layer and forming the floating gate and forming the gate oxide layer and the control gate in the peripheral region 104 to complete the fabrication of the memory device are well known to those of ordinary skill in the art. Do not repeat them. In particular, in general, since the peripheral region 104 is generally used to form a high voltage component and a low voltage component, before the formation of the gate oxide layer, the peripheral region generally receives more wet etching than the memory cell region, plus the peripheral region. The thickness of the high voltage gate oxide layer of 104 is relatively limited or reduced, and the problem of thinning of the high voltage gate oxide layer is also severe in the peripheral region 104.

However, in the present embodiment, the first lining layer 140 is used to make the peripheral mask 104 and the patterned mask layer 120 of the memory cell region 102 have different retractions C1 and C2 after performing the shrinking process, and the peripheral region is made. The amount of contraction C1 of the patterned mask layer 120 of 104 is greater than the amount of contraction C2 of the patterned mask layer 120 of the memory cell region 102. In this way, the space left by the indentation of the patterned mask layer 120 can be filled with the insulating material to prevent the etching liquid from removing the patterned pad layer 110 from damaging the upper corner of the shallow trench isolation structure 170, thereby avoiding subsequent The tunneling oxide layer formed on the side of the shallow trench isolation structure 170 and the gate oxide layer are thinned or formed in the recess. In detail, please refer to FIG. 4A to FIG. 4D at the same time, FIG. 4A and FIG. 4B are partial schematic views of a conventional high-voltage zone and a low-pressure zone, respectively, and FIG. 4C and FIG. 4D are respectively partial schematic views of the high-voltage zone and the low-pressure zone of the present invention. A gate oxide layer 180 and a control gate 190 have been formed on the substrate 100. As can be seen from FIG. 4C and FIG. 4D, the shallow trench isolation structure 170 formed by the method of the present embodiment is compared to the shallow trench isolation structure 170 formed by the conventional method. The upper corner 170a does not have a recess, so the gate oxide layer 180 formed on the shallow trench isolation structure 170 has a uniform thickness and does not have an angle thinning phenomenon or a problem formed in the recess. In particular, since the amount of shrinkage C1 of the patterned mask layer 120 of the peripheral region 104 is large, the gate oxide layer 180 formed on the side of the shallow trench isolation structure 170 of the peripheral region 104 can be larger than conventional techniques. The thickness is to provide good gate oxide insulation properties.

2A-2E are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a second embodiment of the present invention. Referring to FIG. 2A , a patterned pad layer 110 and a patterned mask layer 120 are sequentially formed on a substrate 100 . The substrate 100 includes a memory cell region 102 and a peripheral region 104 . Next, a portion of the substrate 100 is removed by patterning the mask layer 120 as a mask to form a plurality of trenches 130. The above steps may be referred to in the first embodiment, and are not described herein.

Referring to FIG. 2B, a second liner layer 142 is formed on the substrate 100 to cover the surface of the patterned mask layer 120, the patterned pad layer 110, and the trench 130. In the present embodiment, the second liner layer 142 includes, for example, a nitride layer, the material of which is, for example, tantalum nitride. The second liner layer 142 is formed, for example, by a low pressure chemical vapor deposition process, and the second liner layer 142 has a thickness of, for example, about 100 angstroms. In particular, in an embodiment (not shown), a thin oxide layer may be formed on the substrate 100 prior to forming the second liner layer 142, wherein the thickness of the thin oxide layer is, for example, about 10 angstroms.

Next, a first liner 140 is formed on the second liner 142. In the present embodiment, the first underlayer 140 includes, for example, an oxide layer, and examples of the material thereof Such as an oxide comprising a high temperature oxide or a tetraethoxy decane. The thickness of the first underlayer 140 is, for example, about 150 angstroms. The method of forming the first liner 140 is, for example, a low pressure chemical vapor deposition process. In this embodiment, after the first liner layer 140 is formed, the first liner layer 140 is further subjected to a uniform densification process. The densification process is carried out, for example, in nitrogen or oxygen and at elevated temperatures, wherein the elevated temperature is, for example, about 900 °C. In particular, the densification process enables the etching rate of the first liner layer 140 in the etchant of hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerol to be as close as possible to tantalum nitride. In particular, in the present embodiment, a second liner layer 142 having a material nitride formed on the substrate 100 and a first liner layer 140 having a material of ruthenium oxide are exemplified, but in another embodiment. The second liner layer 142 may also be subjected to an oxidation technique such as In Situ Steam Generation (ISSG) oxidation to form a portion of the second liner layer 142 after the second liner layer 142 having the nitride material is formed. It is converted into an oxide layer to form a first liner 140 whose material is an oxide. Or, for example, after depositing the first oxide layer on the surface of the second liner layer 142 by low pressure chemical vapor deposition, an oxidation technique such as on-site vapor generation oxidation is performed to pass the oxidizing gas through the first oxide layer to partially The second liner layer 142 is converted into a second oxide layer which is combined with the second oxide layer to form a first liner layer 140 of an oxide material. In this way, the second liner layer 142 and the first liner layer 140 as shown in FIG. 2B can also be formed.

Referring to FIG. 2C, the first liner 140 covering the patterned mask layer 120 of the peripheral region 104, the patterned pad layer 110, and the surface of the trench 130 is removed. In detail, in the embodiment, for example, a photoresist layer 150 is formed on the memory cell region 102 to cover the first liner layer of the memory cell region 102. 140. The first liner 140 of the perimeter region 104 is then removed. In this way, since the first liner 140 located in the memory cell region 102 is covered by the photoresist layer 150, it can be retained, and the first liner layer 140 located in the peripheral region 104 is removed to expose the first layer 140. Second liner 142. The method of removing the first underlayer 140 includes, for example, a wet etching process, such as using an etchant including buffered hydrofluoric acid.

Referring to FIG. 2D, the photoresist layer 150 is removed and a cleaning process is performed to remove the residue. After the photoresist layer 150 is removed, the memory cell region 102 is covered with a first liner layer 140 and a second liner layer 142, while the peripheral region 104 is only covered with a second liner layer 142.

Next, the patterned mask layer 120 is subjected to a shrinking process such that the shrinkage amount C1 of the patterned mask layer 120 of the peripheral region 104 is greater than the shrinkage amount C2 of the patterned mask layer 120 of the memory cell region 102. In the present embodiment, the shrinking process includes, for example, a wet etching process such as using an etching solution including hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerin. The second lining layer 142 is covered and protected on the patterned mask layer 120 of the peripheral region 104. The patterned lining layer 120 of the memory cell region 102 has a first lining layer 140 and a second lining layer 142. The cover protection is such that the amount of shrinkage C2 of the patterned mask layer 120 of the memory cell region 102 is less than the amount of contraction C1 of the patterned mask layer 120 of the peripheral region 104. In particular, the peripheral mask 104 and the patterned mask layer 120 of the memory cell region 102 can have appropriate amounts of retraction C1, C2 by controlling parameters such as the thickness of the liner and the etching time in the shrink process. Moreover, the thickness of the patterned mask layer 120 of the peripheral region 104 may be less than the thickness of the patterned mask layer 120 of the memory cell region 102.

Referring to FIG. 2E, an oxide layer 160 is formed in the trench 130, and then a plurality of shallow trench isolation structures 170 are formed. This step can be referred to in the first embodiment, and details are not described herein.

After forming the shallow trench isolation structure 170, the patterning mask layer 120 and the patterned pad layer 110 are removed, the tunnel oxide layer is formed in the memory cell region 102, and the floating gate is formed and the gate region is formed in the peripheral region 104. The steps of the oxide layer and the control gate are completed to complete the fabrication of the memory device, and these steps are well known to those of ordinary skill in the art, and thus will not be described herein. In particular, in general, since the peripheral region 104 is generally used to form a high voltage component and a low voltage component, before the formation of the gate oxide layer, the peripheral region generally receives more wet etching than the memory cell region, plus the peripheral region. The thickness of the high voltage gate oxide layer of 104 is relatively limited or reduced, and the problem of thinning of the high voltage gate oxide layer is also severe in the peripheral region 104.

However, in the present embodiment, the first lining layer 140 is used to make the peripheral mask 104 and the patterned mask layer 120 of the memory cell region 102 have different retractions C1 and C2 after performing the shrinking process, and the peripheral region is made. The amount of contraction C1 of the patterned mask layer 120 of 104 is greater than the amount of contraction C2 of the patterned mask layer 120 of the memory cell region 102. In this way, the space left by the indentation of the patterned mask layer 120 can be filled with the insulating material to prevent the etching liquid from removing the patterned pad layer 110 from damaging the upper corner of the shallow trench isolation structure 170, thereby avoiding subsequent The tunneling oxide layer formed on the side of the shallow trench isolation structure 170 and the gate oxide layer are thinned or formed in the recess. For example, as shown in FIG. 4C and FIG. 4D, formed by the method of the embodiment The upper corner corner 170a of the shallow trench isolation structure 170 does not generate a recess, so the gate oxide layer 180 formed on the shallow trench isolation structure 170 has a uniform thickness and does not have an angle thinning phenomenon or is formed in the recess. . In particular, since the amount of shrinkage C1 of the patterned mask layer 120 of the peripheral region 104 is large, the gate oxide layer 180 formed on the side of the shallow trench isolation structure 170 of the peripheral region 104 can be larger than conventional techniques. The thickness is to provide good gate oxide insulation properties.

In particular, in the above embodiment, the second liner layer 142 is formed directly on the substrate 100. However, in other embodiments, an oxide layer may be formed on the substrate 100, and then A second liner layer 142 of a nitride material is formed on the oxide layer. 3A to 3D are schematic cross-sectional views showing a method of manufacturing a shallow trench isolation structure according to a third embodiment of the present invention. The manufacturing process of this embodiment is substantially the same as that described in FIGS. 2A to 2E. Explain in different places. Referring to FIG. 3A, first, an oxide layer 138 is formed on the substrate 100. The formation method of the oxide layer 138 is, for example, a low pressure chemical vapor deposition method. Then, the oxide layer 138 is subjected to a uniform densification process under nitrogen and high temperature, so that the etching rate of the oxide layer 138 in the etching solution of hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerol is as close as possible to nitrogen. Phlegm. Then, a second liner layer 142 and a first liner layer 140 are formed on the oxide layer 138 in sequence. In the present embodiment, the second liner layer 142 is formed by, for example, forming a tantalum nitride layer by low pressure chemical vapor deposition. The first liner layer 140 is formed by, for example, performing an oxidation technique such as on-site vapor generation (ISSG) oxidation on the second liner layer 142 to convert a portion of the second liner layer 142 into an oxide layer to form a material. For the oxide A liner 140. As such, in this embodiment, the substrate 100 is sequentially formed with an oxide layer 138, a second liner layer 142 of a nitride material, and a first liner layer 140 of an oxide material.

Referring to FIG. 3B, the first liner layer 140 and the second liner layer 142 covering the patterned mask layer 120 of the peripheral region 104, the patterned pad layer 110, and the surface of the trench 130 are removed. In detail, in this embodiment, for example, a photoresist layer (not shown) is formed on the memory cell region 102 to cover the first liner layer 140 of the memory cell region 102, and then the peripheral region 104 is removed. The first liner 140. Then, the photoresist layer is removed and a cleaning process is performed to remove the residue. The second liner 142 of the peripheral region 104 is then removed. The method of removing the first underlayer 140 includes, for example, a wet etching process, such as using an etchant including buffered hydrofluoric acid. The method of removing the second liner layer 142 includes, for example, a wet etching process such as using an etching solution including hot phosphoric acid. After removing the first liner 140 of the peripheral region 104, removing the photoresist layer of the memory cell region 102, and removing the second liner layer 142 of the peripheral region 104, the first liner layer 140 of the memory cell region 102 is exposed. Oxide layer 138 of peripheral region 104.

Referring to FIG. 3C, the first liner 140 of the memory cell region 102 and the oxide layer 138 of the peripheral region 104 are then removed. The method of removing the first underlayer 140 and the oxide layer 138 includes, for example, a wet etching process, such as using an etchant including dilute hydrofluoric acid. In particular, in one embodiment, this step may also be omitted such that the patterned mask layer 120 of the peripheral region 104 is protected by an oxide layer 138 and the patterned mask layer 120 of the memory cell region 102. There is a cover protection of the first liner 140, the second liner 142, and the oxide layer 138.

Referring to FIG. 3D, the patterned mask layer 120 is subjected to a retracting process such that the encapsulation amount C1 of the patterned mask layer 120 of the peripheral region 104 is greater than the patterning mask layer 120 of the memory cell region 102. Shrinkage C2. In the present embodiment, the shrinking process includes, for example, a wet etching process such as using an etching solution including hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerin. Wherein, the patterned mask layer 120 is exposed compared to the peripheral region 104, and the patterned mask layer 120 of the memory cell region 102 is covered by the second liner layer 142 and the oxide layer 138, thereby protecting the memory region. The amount of contraction C2 of the patterned mask layer 120 of 102 will be less than the amount of contraction C1 of the patterned mask layer 120 of the peripheral zone 104. Moreover, the thickness of the patterned mask layer 120 of the peripheral region 104 may be less than the thickness of the patterned mask layer 120 of the memory cell region 102. In particular, the peripheral mask 104 and the patterned mask layer 120 of the memory cell region 102 can have appropriate amounts of retraction C1, C2 by controlling parameters such as the thickness of the liner and the etching time in the shrink process. After the completion of this step, a subsequent process for forming a plurality of shallow trench isolation structures can be referred to the previous embodiment, and details are not described herein.

In summary, the method for fabricating the shallow trench isolation structure of the present invention is such that the patterned mask layer has different amounts of retraction in the peripheral region and the memory cell region according to the element characteristics of the peripheral region and the memory cell region. In this way, it is possible to prevent the upper corner of the shallow trench isolation structure from being recessed due to the removal process of the patterned pad layer or the like, so that the tunnel oxide layer and the gate oxide layer which are subsequently formed on the side of the shallow trench isolation structure are at the corner It can have a thickness consistent with the main body without the phenomenon of corner thinning. Therefore, the memory element can have better element characteristics.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art does not deviate. In the spirit and scope of the present invention, the scope of protection of the present invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧The surrounding area

110‧‧‧ patterned cushion

120‧‧‧ patterned mask layer

130‧‧‧ditch

138‧‧‧Oxide layer

140‧‧‧First lining

142‧‧‧Second lining

150‧‧‧ photoresist layer

160‧‧‧Oxide layer

170‧‧‧Shallow trench isolation structure

170a‧‧‧Upturn corner

180‧‧‧ gate oxide layer

190‧‧‧Control gate

C1, C2‧‧‧ shrinkage

1A-1F are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a first embodiment of the present invention.

2A-2E are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a second embodiment of the present invention.

3A-3D are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a third embodiment of the present invention.

4A and 4B are partial schematic views of a conventional high pressure zone and a low pressure zone, respectively, and FIGS. 4C and 4D are partial schematic views of the high pressure zone and the low pressure zone of the present invention, respectively.

100‧‧‧Base

102‧‧‧ memory area

104‧‧‧The surrounding area

110‧‧‧ patterned cushion

120‧‧‧ patterned mask layer

130‧‧‧ditch

C1, C2‧‧‧ shrinkage

Claims (11)

A method for fabricating a shallow trench isolation structure includes: sequentially forming a patterned pad layer and a patterned mask layer on a substrate, wherein the substrate comprises a memory cell region and a peripheral region; and the patterned mask layer a mask, removing a portion of the substrate to form a plurality of trenches; forming a first liner on the substrate to cover the patterned mask layer, the patterned pad layer, and surfaces of the trenches; Covering the patterned mask layer of the peripheral region, the patterned pad layer, and the first liner layer of the surface of the trench; performing a shrinking process on the patterned mask layer to make the pattern of the peripheral region The shrinkage amount of the mask layer is greater than the shrinkage amount of the patterned mask layer of the memory cell region; and an insulating layer is formed in the trenches to form a plurality of shallow trench isolation structures. The method of fabricating a shallow trench isolation structure according to claim 1, wherein the first liner layer comprises an oxide layer. The method for manufacturing a shallow trench isolation structure according to claim 2, wherein the material of the first liner comprises a high temperature oxide or an oxide formed of tetraethoxysilane. The method for manufacturing a shallow trench isolation structure according to claim 1, further comprising performing a uniform densification process on the first liner in nitrogen and at a high temperature. The method for manufacturing a shallow trench isolation structure according to claim 1, wherein the patterned liner layer covering the peripheral region, the patterned pad layer, and the first liner layer of the surface of the trench are removed. The method includes: forming a photoresist layer on the memory cell region to cover the first liner layer of the memory cell region; and removing the first liner layer of the peripheral region. The method of fabricating a shallow trench isolation structure according to claim 5, wherein the method of removing the first liner comprises a wet etching process. The method of manufacturing the shallow trench isolation structure of claim 1, wherein the shrinking process comprises a wet etching process. The method for manufacturing a shallow trench isolation structure according to claim 1, further comprising forming a second liner on the substrate to cover the patterned mask layer before forming the first liner layer, Patterning the mat and the surfaces of the trenches. The method for manufacturing a shallow trench isolation structure according to claim 8, wherein the material of the second liner comprises tantalum nitride. The method for manufacturing a shallow trench isolation structure according to claim 8, further comprising performing a uniform densification process on the first liner in nitrogen or oxygen and at a high temperature. The method for manufacturing a shallow trench isolation structure according to claim 8 is characterized in that, in the shrinking process, the patterned mask layer of the memory cell region is sequentially covered with the second liner layer and the first layer A liner layer and the patterned mask layer of the peripheral region are covered with the second liner layer.