TWI410974B - Multi-state memory having data recovery after program fail - Google Patents

Description

Complex state memory with data recovery after programming failure

The present invention generally relates to non-volatile semiconductor memories such as electronic erasable programmable read only memory (EEPROM) and flash EEPROM, and in particular to methods for constructing fast pass write or other multiphase programming techniques. .

Solid-state memory capable of non-volatile storage of charge (especially in the form of EEPROM and flash EEPROM packaged in small form factor cards) has recently become a mobile and handheld device (especially for information electrical equipment and consumer electronics). Preferred storage device. Unlike RAM (random access memory), which is also a solid-state memory, the flash memory system is non-volatile, so that even after it is powered off, it retains its stored data. Although costly, flash memory is being used more and more in mass storage applications. Conventional mass storage devices based on rotating magnetic media such as hard disk drives and floppy disks are not suitable for use in mobile and handheld environments. This is because it tends to be a large hard disk drive that is prone to mechanical failure and has long waiting times and high power requirements. These undesirable attributes make disk-based storage devices impractical in most mobile and portable applications. On the other hand, since the flash memory in the form of a buried card and a removable card has the characteristics of small size, low power consumption, high speed, and high reliability, it is ideally suited for use in mobile and handheld environments.

EEPROM and electronically programmable read-only memory (EPROM) are non-volatile memories that can be erased and can be written or "programmed" into new data in their memory cells. Both utilize floating (unconnected) conductive gates in the field effect transistor structure between the source and drain regions, above the channel region in the semiconductor substrate. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge remaining on the floating gate. That is, for a charge that is positioned on the floating gate, there is a corresponding voltage (proximity) that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain regions.

The floating gate can fix a range of charges and can therefore be programmed to any threshold voltage level within the threshold voltage window. The threshold voltage window is defined by the minimum and maximum threshold levels of the device, which in turn correspond to the range of charges that can be programmed onto the floating gate. The threshold window usually depends on the characteristics, operating conditions and history of the memory device. In principle, each distinct, analyzable threshold voltage level range within the window can be used to represent the determined memory state of the cell.

A transistor used as a memory cell is typically programmed into a "programmed" state by one of two mechanisms. In "hot electron injection", the high voltage applied to the drain causes electrons to accelerate through the substrate channel region. At the same time, the high voltage applied to the control gate pulls the hot electrons through the thin gate dielectric onto the floating gate. In "tunneling injection", a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.

The memory device can be erased by several mechanisms. For EPROMs, the memory is largely erased by removing the charge from the floating gate using ultraviolet radiation. For EEPROM, by applying a high voltage to the substrate relative to the control gate, the electrons in the floating gate are induced to tunnel through the thin oxide to the substrate channel region (ie, Fowler-Nordheim tunneling) In addition to the memory unit. Typically, the EEPROM can be erased with one byte followed by one byte. For flash EEPROM, all of the memory can be erased at the same time or one or more blocks can be erased at one time. One block can be composed of 512 bytes or more of the memory. .

Example of a non-volatile memory unit

The memory device typically includes one or more memory chips mountable on the card. Each memory chip contains a memory cell array supported by surrounding circuitry such as a decoder and erase, write and read circuitry. More complex memory devices also have controllers that perform intelligent and higher level memory operations and engagement. There are many non-volatile solid state memory devices that are still commercially successful today. These memory devices can utilize different types of memory cells, each type having one or more charge storage elements.

Figures 1A through 1E schematically illustrate different examples of non-volatile memory cells.

Figure 1A schematically illustrates a non-volatile memory in the form of an EEPROM cell having a floating gate for storing charge. Electronically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides for electrically loading charge to its floating gate and electrically removing charge from its floating gate when an appropriate voltage is applied. There is no need to expose to UV radiation. Examples of such units and methods of making such units are provided in U.S. Patent No. 5,595,924.

FIG. 1B schematically illustrates a flash EEPROM cell having a select gate and a control or steering gate. The memory cell 10 has a "split channel" 12 between the source 14 and the drain 16 diffusion region. A unit is effectively formed by two transistors T1 and T2 connected in series. T1 is used as a memory transistor having a floating gate 20 and a control gate 30. The floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the channel portion of T1 depends on the voltage on the control gate 30 and the amount of charge that is present on the floating gate 20. T2 is used as the selection transistor with the selected gate 40. When T2 is turned on by selecting the voltage at the gate 40, it allows the current in the channel portion of T1 to pass between the source and the drain. The transistor is selected to provide a switch along the source-drain channel in a manner independent of the voltage at the control gate. One advantage is that it can be used to disconnect those cells that are still conducting when the control gate voltage is zero (due to the charge depletion (positive) at their floating gate). Another advantage is that it allows for easier implementation of source side injection programming.

A simple embodiment of a split channel memory cell is where the select gate and control gate are connected to the same word line as indicated by the dashed line shown in Figure 1B. This is accomplished by having the charge storage element (floating gate) on one portion of the channel and the control gate structure (which is part of the word line) on the other channel portion and the charge storage element. This effectively forms a cell having two transistors in series, one of which (memory transistor) has a combination of the amount of charge on the charge storage element and the voltage on the word line of the amount of control current (which can flow through its channel portion), And the other (selective transistor) has only the word line that acts as its gate. Examples of such units, their use in a memory system, and methods of making the same are provided in U.S. Patent Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053.

One of the modified embodiment of the split channel unit shown in FIG. 1B is when the select gate and the control gate are independent and are not connected by dashed lines therebetween. One embodiment has a row of control gates in a cell array that is connected to a control (or steering) line that is perpendicular to the word line. The effect is that the word line does not need to perform both functions simultaneously when reading or programming the selected cell. These two functions are: (1) acting as the gate of the selection transistor, requiring an appropriate voltage to turn the selection transistor on and off, and (2) via an electric field coupled between the word line and the charge storage element (capacitance) ) to drive the voltage of the charge storage element to the desired level. It is often difficult to perform these two functions in an optimal manner using a single voltage. In the case of separately controlling the control gate and the selection gate, the word line only needs to perform the function (1), and the added control line performs the function (2). This capability allows for a design in which the programming voltage is adapted to the higher performance programming of the target material. The use of independent control (or steering) gates in flash EEPROM arrays is described in, for example, U.S. Patent Nos. 5,313,421 and 6,222,762.

FIG. 1C schematically illustrates another flash EEPROM cell having dual floating gates and independently selecting and controlling gates. The memory cell 10 is similar to the memory cell of Figure 1B except that it effectively has three series transistors. In this type of unit, two storage elements (ie, T1-left and T1-right storage elements) are included in the channel between the source and the drain diffusion, with a selection of electricity between the two storage elements. Crystal T1. The memory transistors have floating gates 20 and 20' and control gates 30 and 30', respectively. The selection transistor T2 is controlled by the selection gate 40. At any one time, only one of the pair of memory transistors is accessed for reading or writing. When the left side of the memory cell T1- is accessed, T2 and T1-right are turned on to allow current in the channel portion of the T1-left side to pass between the source and the drain. Similarly, when the right side of the storage unit T1- is accessed, T2 and T1-left are turned on. This is achieved by having a portion of the selected gate polysilicon very close to the floating gate and applying a substantially positive voltage (eg, 20 V) to the select gate such that electrons stored in the floating gate can tunnel to the select gate polysilicon. Erase.

FIG. 1D schematically illustrates a string of memory cells organized into NAND cells. NAND cell 50 is comprised of a series of memory transistors M1, M2, ... Mn (n = 4, 8, 16 or higher) that are daisy chained by their source and drain. A pair of select transistors S1, S2 controls the connection of the memory transistor chain to the outside via the source terminal 54 and the drain terminal 56 of the NAND cell. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to the source line. Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND cell is coupled to the bit line of the memory array. Each memory transistor in the chain has a charge storage element to store a given amount of charge to represent the expected memory state. The control gate of each memory transistor provides control during read and write operations. The control gates of each of the transistors S1, S2 are selected to provide controlled access to the NAND cells via their source terminals 54 and gate terminals 56, respectively.

When the addressed memory cell in the NAND cell is read and verified during programming, the control gate is supplied with the appropriate voltage. At the same time, the remainder of the unaddressed memory transistor in NAND cell 50 is fully turned on by applying sufficient voltage across its control gate. In this manner, the source path from the source of the individual memory transistor to the source terminal 54 of the NAND cell effectively produces a conductive path, and likewise, the drain from the drain of the individual memory transistor to the gate terminal 56 of the cell is also effective to produce a conductive path. A memory device having such NAND cell structures is described in U.S. Patent Nos. 5,570,315, 5,903,495, 6,046,935.

Figure 1E schematically illustrates a non-volatile memory having a dielectric layer for storing charge. A dielectric layer is used instead of the previously described conductive floating gate elements. The use of dielectrics has been described in "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," by Eitan et al. (IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545). These memory devices that store components. The ONO dielectric layer extends through the channel between the source and the drain diffusion. The charge for one data bit is located in the dielectric layer adjacent to the drain and the charge for other data bits is in the dielectric layer adjacent to the source. For example, U.S. Patent Nos. 5,768,192 and 6,011,725 disclose non-volatile memory cells having a dielectric sandwiched between two cerium oxide layers. The complex state data storage is performed by separately reading the binary state of the space-separated charge storage region within the dielectric.

Memory array

A memory device typically includes a two-dimensional array of memory cells arranged in columns and rows and addressable by word lines and bit lines. The array can be formed according to a NOR type or NAND type architecture.

NOR array

Figure 2 illustrates an example of a NOR array of memory cells. A memory device having a NOR type architecture has been implemented by a unit of the type illustrated in FIG. 1B or FIG. 1C. Each column of memory cells is daisy-chained by its source and drain. This design is sometimes referred to as a fake ground design. Each memory cell 10 has a source 14, a drain 16, a control gate 30 and a select gate 40. The select gate of the cell in the column is connected to word line 42. The source and drain of the cell in the row are connected to selected bit lines 34 and 36, respectively. In some embodiments in which the control gates and select gates of the memory cells are independently controlled, the steering line 36 is also coupled to the control gates of the cells in the row.

Many flash EEPROM devices are implemented using a memory cell in which each memory cell is formed by its control gates and select gates connected together. In this case, there is no need to manipulate the lines and the word lines only connect all of the control gates and select gates of the cells along each column. Examples of such designs are disclosed in U.S. Patent Nos. 5,172,338 and 5,418,752. In these designs, the word line performs two main functions: column selection and supplying the control gate voltage to all cells in the column for reading or programming.

NAND array

Figure 3 illustrates an example of a NAND array of memory cells, such as shown in Figure ID. Along each row of the NAND cell, a bit line is coupled to the drain terminal 56 of each NAND cell. Along the NAND cell, the source line can connect all of its source terminals 54. Also, the control gates of the NAND cells along a column are connected to a series of corresponding word lines. The entire column of NAND cells can be addressed by turning on the pair of select transistors (see FIG. 1D) with appropriate voltages on the control gates of an entire column of NAND cells via the connected word lines. When the memory transistor in the NAND cell chain is read, the remaining memory transistors in the chain are firmly turned on via their associated word lines such that the current flowing through the chain is primarily dependent on the cell being read The stored charge level. An example of a NAND architecture array and its operation as a component of a memory system is found in U.S. Patent Nos. 5,570,315, 5,774,397 and 6,046,935.

Block erase

Programming of the charge storage memory device can only result in more charge being added to its charge storage element. Therefore, the existing charge in the charge storage element must be removed (or erased) prior to the programming operation. An erase circuit (not shown) is provided to erase one or more of the block memory cells. Non-volatile memory such as EEPROM is referred to as a "flash" EEPROM when the entire cell array or a significant group of array elements are electrically erased together (ie, in a flash). Once erased, the set of cells can then be reprogrammed. The set of cells that can be erased together can form one or more addressable erase units. An erase unit or block typically stores one or more pages of data (pages are programmed and read units), but can be programmed or read more than one page in a single operation. Each page typically stores data for one or more segments, the size of which is defined by the host system. An example is a 512-bit tuple segment, which is a user profile, followed by a standard established by the disk drive, plus a number of bits for user data and/or blocks (where user data is stored). The group's additional information is composed of information.

Read/write circuit

In a conventional two-state EEPROM cell, at least one current breakpoint level is established to divide the conductive window into two regions. When a cell is read by applying a predetermined, fixed voltage, it is resolved to a memory state by comparing its source/drain current to a breakpoint level (or reference current I _{R E F} ). If the current being read is higher than the current at the breakpoint level, the unit is determined to be in a logic state (eg, a "zero" state). On the other hand, if the current is lower than the current at the breakpoint level, the unit is determined to be in another logic state (eg, "one" state). Therefore, the two state units store digital information of one bit. An externally programmable reference current source is typically provided as part of the memory system to generate a breakpoint level current.

In order to increase the memory capacity, as semiconductor technology improves its state, flash EEPROM devices are being manufactured at ever higher densities. Another method for increasing storage capacity is to store more than two states per memory unit.

For a complex state or complex level EEPROM memory cell, the conductive window is divided into more than two regions by more than one breakpoint, so that each cell can store more than one bit of data. Thus, the information that can be stored for a given EEPROM array increases with the number of states that each cell can store. An EEPROM or flash EEPROM having a complex state or a plurality of levels of memory cells has been described in U.S. Patent No. 5,172,338.

In practice, the memory state of a cell is typically read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of the cell, the corresponding conduction current can be detected relative to the fixed reference control gate voltage. Similarly, the range of charge programmable to the floating gate defines a corresponding threshold voltage window or corresponding conductive current window.

Alternatively, it is possible to set a threshold voltage at a control gate for a given memory state in the test and to detect if the conduction current is below or above the threshold current, rather than detecting the conduction current in the divided current window. In one embodiment, the conduction current is detected relative to the threshold current by verifying the rate of discharge of the conduction current through the capacitance of the bit line.

Figure 4 illustrates the relationship between the source-drain current I _{D of} four different charges Q1 to Q4 and the control gate voltage V _{C G} for which the floating gate can be selectively stored at any one time. pole. For four solid I _D V _{C G} in the four upper curves represent the programmable floating gate memory cell of the possible charge level, these four possible charge level respectively corresponding to four possible memory states. As an example, a threshold voltage window for a certain number of cells can vary from 0.5 V to 3.5 V. In each 0.5 V interval, six memory states can be delimited by dividing the threshold window into five regions. For example, if a 2 μA reference current I _{R E F is} used as shown, the cell programmed by Q1 can be considered to be in the memory state "1" because its curve is delimited by V _{C G} = 0.5 V and 1.0 V. The I _{R E F} in the threshold window area intersects. Similarly, Q4 is in the memory state "5".

As can be seen from the above description, the more the memory cells are stored, the finer the threshold window is. This will require a higher degree of precision in programming and read operations to achieve the desired resolution.

No. 4,357,685 discloses a method of programming a 2-state EPROM in which when a cell is programmed to a given state, it is subjected to a continuous programming voltage pulse, each time adding a delta charge to the floating gate. Between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state is verified to reach the desired state. The programming pulse train used can have an increased period or amplitude.

The prior art programming circuit only applies a programming pulse to step through the threshold window from the erase or ground state until the target state is reached. In fact, in order to allow for sufficient resolution, each segmented or demarcated region will be required to traverse at least about five programming steps. This performance is acceptable for a 2-state memory unit. However, for a complex state cell, the number of steps required increases as the number of partitions increases, and therefore, programming precision or resolution must be increased. For example, a 16-state unit may, on average, require at least 40 programming pulses to program to a target state.

FIG. 5 schematically illustrates a memory device having a typical configuration in which the memory array 100 can be accessed by the read/write circuit 170 via the column decoder 130 and the row decoder 160. As described in connection with Figures 2 and 3, the memory transistors of the memory cells in memory array 100 can be addressed via a set of selected word lines and bit lines. Column decoder 130 selects one or more word lines and row decoder 160 selects one or more bit lines to apply an appropriate voltage to the individual gates of the addressed memory transistors. A read/write circuit 170 is provided to read or write (program) the memory state of the addressed memory transistor. The read/write circuit 170 includes a number of read/write modules connectable to memory elements in the array via bit lines.

FIG. 6A is a schematic block diagram of an individual read/write module 190. Basically, during reading or verification, the sense amplifier determines the current flowing through the drain of the addressed memory transistor connected via the selected location line. This current depends on the charge stored in the memory transistor and its control gate voltage. For example, in a complex state EEPROM cell, its floating gate can be charged to one of several different levels. For a 4-bit unit, it can be used to store two-dimensional data. The level detected by the sense amplifier is converted from level to bit conversion logic to a set of data bits to be stored in the data latch.

Factors affecting read/write performance and accuracy

To improve read and program performance, multiple charge storage elements or memory transistors in the array can be read or programmed in parallel. Therefore, the logical "pages" of the memory elements are read or programmed together. In existing memory architectures, a column typically contains a number of interlaced pages. All memory elements of a page will be read or programmed together. The row decoder will selectively connect each of the interleaved pages to a corresponding number of read/write modules. For example, in one embodiment, the memory array is designed to have a page size of 532 bytes (512 bytes plus 20 additional item bytes). If each row contains a drain bit line and there are two interleaved pages per column, this is equivalent to 8512 rows, with each page associated with 4256 rows. There will be 4256 sensing modules that can be connected to read or write all even bit lines or odd bit lines in parallel. In this manner, a page of 4256 bits (i.e., 532 bytes) of data in parallel is read from the page memory element or programmed into the page memory element. The read/write modules forming the read/write circuit 170 can be configured in a variety of architectures.

Referring to FIG. 5, read/write circuit 170 is organized into a set of read/write stacks 180. Each read/write stack 180 is stacked on one of the read/write modules 190. In a memory array, the line spacing is determined by occupying one of the line spacings or the size of two transistors. However, as can be seen from Figure 6A, it will be possible to use more transistors and circuit elements to construct the circuitry of the read/write module and, therefore, it will occupy a lot of space on the line. To service more than one line of the occupied line, multiple modules are stacked on top of each other.

FIG. 6B shows the read/write stack of FIG. 5 conventionally constructed from a stack of read/write modules 190. For example, the read/write module can be extended over sixteen rows, and then the read/write stack 180 with a stack of eight read/write modules can be used to serve eight rows in parallel. The read/write stack can be coupled to eight odd (1, 3, 5, 7, 9, 11, 13, 15) rows or eight even numbers (2, 4, 6, 8) in the group via a row decoder. , 10, 12, 14, 16) lines.

As mentioned above, conventional memory devices improve read/write operations by operating simultaneously on all even or all odd bit lines in an overall parallel manner. This column architecture consisting of two interleaved pages will help alleviate the problem of aligning the blocks of the read/write circuits. It is also indicated by considering the control bit line to the bit line capacitance coupling. The block decoder is used to multiplex the read/write module set to even or odd pages. In this manner, as long as a set of bit lines are read or programmed, the interlace set can be grounded to minimize direct proximity coupling.

However, the interleaved page architecture is disadvantageous in at least three respects. First, it requires additional multiplexed circuits. Second, its effectiveness is slow. In order to complete the reading or programming of memory cells connected by word lines or connected in a column, two read or two programming operations are required. Third, when programming two adjacent charge storage elements at different times (such as in odd and even pages, respectively), other interference effects such as field coupling between adjacent charge storage elements at floating gate levels are not The best.

The problem of adjacent field coupling becomes more pronounced as the spacing between memory cells is closer. In a memory transistor, a charge storage element is sandwiched between the channel region and the control gate. The current flowing in the channel region is a function of the resulting electric field that is affected by the location at the control gate and the charge storage element. In the case of increasing density, memory transistors are becoming smaller and smaller. The field from adjacent charge elements then becomes a significant contributor to the resulting field of the affected unit. The adjacent field depends on the charge programmed into the charge storage element of the neighbor. Since this disturbance field changes as the neighbor's programmed state changes, it is inherently dynamic. Therefore, the affected unit can be read differently at different times depending on the changed state of the neighbors.

The conventional architecture of interlaced pages deteriorates errors caused by the coupling of adjacent floating gates. Since even-numbered pages and odd-numbered pages are programmed and read independently of each other, it is possible to program one page under a set of conditions and in a completely different set of conditions depending on the situation in which the intervening page occurs. Read back the page. The errors read will become more severe with increasing density, requiring more accurate read operations and coarser segmentation of the threshold window of complex state construction. Performance will suffer and the potential performance in the construction of complex states is limited.

U.S. Patent Publication No. US-2004-0060031-A1 discloses a high performance but small non-volatile memory device having a large read/write circuit block for parallel read and write correspondence. The memory unit block. In particular, the memory device has an architecture that minimizes redundancy in the read/write circuit blocks. By redistributing the blocks of the read/write module into blocks in the core portion of the read/write module, significant space and power savings are achieved, with the core portions of the read/write modules being parallel The operation also interacts with a much smaller group of common parts in a time-multiplexed manner. In detail, the data processing in the read/write circuit between the plurality of sense amplifiers and the data latches is performed by the shared processor.

When a programming operation fails, one or more of the cells fail to verify that they are correctly programmed to the target state, unless the data to be written is retained in a set of buffers until the programming operation is completed, otherwise it is lost. This is especially true when two or more bits are programmed into one physical unit, especially when the bits are configured as separate pages (such as an upper page/lower page configuration). When the upper page fails to program, the lower page data is also damaged. Since the lower page may have been programmed a considerable amount of time before, it may not be held in the buffer and will be lost. Again, the need to keep the target data in the buffer until the programming operation is completed results in lower pipeline computational power, higher buffering requirements, or both.

Therefore, there is a general need for high performance and high capacity non-volatile memory. In particular, small non-volatile memory is required, the programming performance of which has the ability to recover data in response to a programming failure.

In accordance with an aspect of the present invention, a method and corresponding circuitry for manipulating a multi-phase programming process in a non-volatile memory is provided. More specifically, the exemplary embodiment uses a fast pass write technique in which a single program pass is used, but since the memory cell is near its target value, the bias of the selected memory cell is changed to slow down programming. After each programming pulse, the memory is verified at the first, lower verification value, and then the second verification is performed at the second higher level. The second level is used to block selected units from further programming. The first, lower verification level is used to change the programming phase. In an exemplary embodiment, increasing the voltage level of the channel of the selected memory cell proceeds to this. The main aspect of the present invention introduces a latch associated with a read/write circuit that can be connected to each selected bit along a corresponding bit line for storing the verification result at this lower level Memory unit. In N-state memory, each memory cell selected for programming will be associated with its N+1 latch, N-latch to remember the target data and associated with the (N+1) latch for manipulation Programming phase.

The illustrative embodiments are NAND type memories, especially NAND type memories in all bit line architectures. The programmed waveform in the form of a rising ladder is applied along the selected word line. In the initial programming phase, the selected memory cell is programmed to ground by setting its corresponding bit line to ground to facilitate programming. Once a successful verification exists at the lower verification level, the bit line voltage is increased via the level of a set of bit line clamps in the exemplary embodiment, thereby allowing the channel of the selected memory cell to reach a higher voltage. Level, which slows down programming. The illustrative embodiment utilizes bit line clamps to adjust the bias level on the bit line. The read/write stack associated with each bit line has a set of data latches that can be used to manipulate the write process (where one of these latches is used to store the verify result at a lower level) And thereby manipulate the programming phase) and the latches sufficient to monitor the standard programming process.

According to other aspects of the invention, the memory can be recovered without the need to maintain a copy of the data until the writing is completed and if a programming fails. Thus, since the integrity of the maintainable data is not required to store the copy, the buffer can be released for use with other data or even excluded, thereby reducing the amount of controller space that is dedicated to data buffering. In an exemplary embodiment, the data is re-constructed by logically combining the verification data for the (failed) write process maintained in the data latch with the result of one or more read operations to reconstruct the material.

The illustrative embodiment is for a memory unit that stores complex status data in a separate upper page, lower page format, and 2-bit form. The upper page and lower page data can be replied to and then written to a new location in the memory as a separate page or a full sequence of writes. This can be done without the use of a controller by the state machine and data latches in the sense amplifier region on the memory. A process example is provided for encoding various materials to the upper and lower pages.

The additional features and advantages of the invention will be apparent from the following description of the preferred embodiments of the invention.

Figure 7A schematically illustrates a small memory device having a set of segmented read/write stacks in which an improved processor of the present invention is constructed. The memory device includes a two-dimensional array of memory cells 300, a control circuit 310, and a read/write circuit 370. Memory array 300 can be addressed by word lines via column decoder 330 and by bit lines via row decoder 360. The read/write circuit 370 is constructed as a set of partitioned read/write stacks 400 and allows blocks of parallel reading or programming of memory cells (also referred to as "pages"). In the preferred embodiment, the pages are formed from successive columns of memory cells. In another embodiment in which one of the memory cell columns is divided into a plurality of blocks or pages, a block multiplexer 350 is provided to multiplex the read/write circuit 370 to the individual blocks.

Control circuit 310 cooperates with read/write circuit 370 to perform a memory operation on memory array 300. Control circuit 310 includes state machine 312, on-chip address decoder 314, and power control module 316. State machine 312 provides wafer level control of memory operations. The on-chip address decoder 314 provides an address interface between the address used by the host or memory controller and the hardware address used by the decoders 330 and 370. Power control module 316 controls the power and voltage supplied to the word lines and bit lines during memory operation.

Figure 7B illustrates a preferred configuration of the small memory device shown in Figure 7A. Access to the memory array 300 by various peripheral circuits is constructed symmetrically on opposite sides of the array such that the access lines and circuitry on each side are reduced by half. Therefore, the column decoder is split into column decoders 330A and 330B, and the row decoder is split into row decoders 360A and 360B. In an embodiment where one of the memory cell columns is divided into a plurality of blocks, the block multiplexer 350 splits into block multiplexers 350A and 350B. Similarly, the read/write circuit is split into a read/write circuit 370A connected from the bottom to the bit line and a read/write circuit 370B connected from the top of the array 300 to the bit line. In this manner, the density of the read/write modules and thus the density of the segmented read/write stack 400 is substantially reduced by half.

Figure 8 schematically illustrates the general configuration of the base components in the read/write stack shown in Figure 7A. In accordance with the general architecture of the present invention, the read/write stack 400 includes a sense amplifier stack 212 for sensing k bit lines, and an I/O for inputting or outputting data via the I/O bus bar 231. A module 440, a data latch stack 430 for storing input or output data, a general purpose processor 500 for processing and storing data in the read/write stack 400, and a The stack bus 421 of communication. One of the stack bus controllers in the read/write circuit 370 provides control and timing signals for controlling various components in the read/write stack via line 411.

Figure 9 illustrates a preferred configuration of a read/write stack in the read/write circuit shown in Figures 7A and 7B. Each read/write stack 400 operates in parallel for a set of k bit lines. If a page has p = r * k bit lines, there will be r read/write stacks 400-1, ..., 400-r.

The entire set of divided read/write stacks 400 operating in parallel allows for parallel reading or programming of p cells along a block (or page) of a column. Therefore, there will be p read/write modules for the entire column of cells. Since each stack serves k memory cells, the total number of read/write stacks in the group is given by r=p/k. For example, if r is the number of stacks in the group, then p = r * k. An example memory array can have p = 512 bytes (512 x 8 bits), k = 8 and thus r = 512. In the preferred embodiment, the block is the operation of the entire column of cells. In another embodiment, a subset of the cells in the block series. For example, a subset of cells can be one-half of an entire column or a quarter of an entire column. A subset of the units may be a contiguous unit or each other unit or each predetermined number of units of operation.

Each read/write stack (such as 400-1) primarily contains a sense amplifier stack 212-1 through 212-k that serve segments in k memory cells in parallel. A preferred sense amplifier is disclosed in U.S. Patent Publication No. 2004-0109357-A1, the entire disclosure of which is incorporated herein by reference. It should be noted that this is only a specific embodiment, where k is the number of bits in the byte and r is the number of bytes that are grouped together. In the present invention, a specific data latch structure is provided for the present invention as long as a sufficient number of data latches, particularly a data latch for each bit storable on the cell, can be connected to the bit line The various aspects are not essential.

The stack bus controller 410 provides control and timing signals to the read/write circuit 370 via line 411. The stack bus controller itself relies on the memory controller 310 via line 311. The communication in each read/write stack 400 is implemented by interconnect stack bus 431 and is controlled by stack bus controller 410. Control line 411 provides control timing signals from stack bus controller 410 to the components of read/write stack 400-1.

In a preferred configuration, the stack bus is split into SABus 422 for communication between the general purpose processor 500 and the sense amplifier stack 212 and DBus 423 for communication between the processor and the data latch stack 430. .

The data latch stack 430 includes data latches 430-1 through 430-k for which one of the data latches of each memory cell is associated with the stack. The I/O module 440 enables the data latch to exchange data with the outside via the I/O bus 231.

The general purpose processor also includes an output 507 for outputting a status signal indicative of a memory operational state, such as an error condition. The status signal is used to drive the gate of the n-cell 550 that relies on the flag bus 509 in the Wired-Or configuration. The flag bus is preferably pre-charged by controller 310 and will be pulled down when the status signal is determined by either of the read/write stacks.

Figure 10 illustrates a modified embodiment of the general purpose processor shown in Figure 9. The general purpose processor 500 includes a processor bus, a PBUS 505 for communicating with external circuitry, input logic 510, a processor latch PLatch 520, and output logic 530.

The input logic 510 receives the data from the PBUS and outputs the data as a transformed data to the BSI node. The data is in a logical state "1", "0" or a control signal from the stack bus controller 410 via the signal line 411. One of the "Z" (floating). The set/reset latch PLatch 520 then latches the BSI, thereby generating a pair of complementary output signals MTCH and MTCH ^* .

The output logic 530 receives the MTCH and MTCH ^* signals and outputs the transformed data on the PBUS 505. The data is in a logical state "1", "0" or "Z" depending on the control signal from the stack bus controller 410 via the signal line 411. "One of the (floating).

At any time, general purpose processor 500 processes the data associated with a given memory unit. For example, FIG. 10 illustrates the condition of a memory cell coupled to bit line 1. Corresponding sense amplifier 212-1 includes a node in which sense amplifier data is present. In the preferred embodiment, the node assumes the form of the SA latch 214-1 storing the data. Similarly, the corresponding data latch 430-1 sets the input or output data associated with the memory cells coupled to bit line 1. In the preferred embodiment, the data latch 430-1 set contains sufficient data latches 434-1, ..., 434-n for storing n-bit data.

The PBUS 505 of the general purpose processor 500 is capable of accessing the SA latch 214-1 via the SBUS 422 when the transmit gate 501 is enabled by a pair of complementary signals SAP and SAN. Similarly, PBUS 505 can access data latch set 430-1 via DBUS 423 when transmit gate 502 is enabled by a pair of complementary signals DTP and DTN. Signals SAP, SAN, DTP, and DTN are clearly illustrated as part of the control signal from stack bus controller 410.

Figure 11A illustrates a preferred embodiment of the input logic of the general purpose processor shown in Figure 10. Input logic 520 receives data on PBUS 505 and has the same or reverse or floating output BSI depending on the control signal. Output BSI node mainly by the transfer gate 522 or the output stage comprises a transistor connected in series to the p 524 V _{d d} of the pull-up circuit 525 or a series to affect the surface of the n transistors 526 and 527 of the pull-down circuit. The pull-up circuit has gates to p transistors 524 and 525 that are controlled by signals PBUS and ONE, respectively. The pull-down circuit has gates to n transistors 526 and 527 controlled by signal ONEB<1> and PBUS, respectively.

Figure 11B illustrates a truth table for the input logic of Figure 11A. The logic is controlled by the PBUS and controlled by the control signals ONE, ONEB<0>, ONEB<1> from the control signals of the stack bus controller 410. Basically, three transfer modes are supported, passing (PASSTHROUGH), reverse (INVERTED), and floating (FLOATED).

In the case of the PASSTHROUGH mode in which the BSI is the same as the input data, the signal ONE is at logic "1", ONEB<0> is at "0" and ONEB<1> is at "0". This will either pull up or pull down but enable the transfer gate 522 to pass data to the output 523 on the PBUS 505. In the case of the INVERTED mode in which the BSI input data is inverted, the signal ONE is at "0", the ONEB<0> is at "1", and the ONE<1> is at "1". This will remove the gate 522. Also, when PBUS is at "0", the pull-down circuit will be de-energized and the pull-up circuit will be enabled, causing the BSI to be "1". Similarly, when PBUS is at "1", the pull-up circuit is disabled and the pull-down circuit is enabled, resulting in BSI at "0". Finally, in the FLOATED mode, the output BSI can be floated by setting the signal ONE to "1", the ONEB<0> to "1", and the ONEB<1> to "0". Although the FLOATED mode is not used in practice, it is listed for completeness.

Figure 12A illustrates a preferred embodiment of the output logic of the general purpose processor shown in Figure 10. The signal from input logic 520 at the BSI node is latched in processor latch PLatch 520. The output logic 530 receives the data MTCH and MTCH ^* from the output of the PLatch 520 and outputs it on the PBUS in the PASSTHROUGH, INVERTED or FLOATED mode depending on the control signal. In other words, the four branches act as drivers for the PBUS 505, actively pulling them to a high, low, or floating state. This is done by four branch circuits (ie, two pull-ups for the PBUS 505 and two pull-down circuits). The first pull-up circuit includes p transistors 531 and 532 connected in series to V _{d d} and is capable of pulling up PBUS when MTCH is at "0". The second pull-up circuit includes p-transistors 533 and 534 connected in series to the ground and is capable of pulling up PBUS when MTC H is at "1". Similarly, the first pull-down circuit includes n transistors 535 and 536 connected in series to V _{d d} and is capable of pulling down PBUS when MTCH is at "0". The second pull-up circuit includes n transistors 537 and 538 connected in series to the ground, and it can pull up the PBUS when the MTCH is at "1".

One feature of the present invention resides in constructing a pull-up circuit with a PMOS transistor and constructing a pull-down circuit with an NMOS transistor. Since the pulling force provided by the NMOS is much stronger than the pulling force provided by the PMOS, the pull-down will always outweigh the pull-up in any competition. In other words, the node or bus can always be preset to the pull-up or "1" state, and if necessary, it can always be toggled to the "0" state.

Figure 12B illustrates a truth table for the output logic of Figure 12A. The logic is controlled by control signals PDIR, PINV, NDIR, NINV from the input logic latched MTCH, MTCH ^* control and for the control signals from the stack bus controller 410. Four modes of operation are supported: pass (PASSTHROUGH), reverse (INVERTED), float (FLOATED), and precharge (PRECHARGE).

In FLOATED mode, go to all four branches. This is done by having the signals PINV=1, NINV=0, PDIR=1, NDIR=0 (these are also preset values). In the PASSTHROUGH mode, when MTCH=0, it will require PBUS=0. This is accomplished by energizing only the n-transistors 535 and 536, where all control signals are at their default values except for NDIR=1. When MTCH = 1, it will require PBUS = 1. This is accomplished by having only the pull-up branches with p-transistors 533 and 534, with all control signals except their PINV=0 at their default values. In the INVERTED mode, when MTCH=0, it will require PBUS=1. This is accomplished by having only the pull-up branches with p-transistors 531 and 532, with all control signals except their PDIR=0 at their default values. When MTCH = 1, it will require PBUS = 0. This is accomplished by energizing only the n-transistors 537 and 538, where all control signals are at their default values except for NINV=1. In the PRECHARGE mode, the control signal settings for PDIR=0 and PINV=0 will be enabled with p-transistor 531 and 532 pull-up branches when MTCH=1 or p-transistors 533 and 534 when MTCH=0. Pull the branch above.

Universal buried device operation is more fully developed in U.S. Patent Application Serial No. 11/026,536, issued Dec. 29, 2004, which is incorporated herein in its entirety by reference.

Fast pass writes in all bit line architectures

An important aspect of the performance of non-volatile memory is the programming speed. This section discusses ways to improve the programming performance of complex state non-volatile memory and present this portion in the content of a NAND memory with an all-bit line (ABL) architecture. In particular, the use of a scratchpad of the general purpose processor shown in FIG. 10 to construct a fast pass write is described.

The goal of programming memory is to write data quickly but accurately. In binary memory, it is only necessary to write all programmed states to a certain threshold level while leaving the unprogrammed state below a certain threshold level. In complex state memory, the situation is more complicated, because for intermediate states, the level must be written above a certain threshold but not too high, otherwise its distribution will impact the subsequent balance. This problem is aggravated as the number of states increases, can be reduced with a threshold window, or both occur.

The goal of programming memory is to write data quickly but accurately. In binary memory, it is only necessary to write all programmed states to a certain threshold level while leaving the unprogrammed state below a certain threshold level. In complex state memory, the situation is more complicated, because for intermediate states, the level must be written above a certain threshold but not too high, otherwise its distribution will impact the subsequent balance. This problem is aggravated as the number of states increases, can be reduced with a threshold window, or both occur.

One technique that tightens the state distribution is to program the same data multiple times. An example is the rough-fine programming method described in U.S. Patent No. 6,738,289, which is incorporated herein by reference. Figure 13 shows two distributions of storage elements corresponding to the same memory state in which the programming waveform PW1 using the first, lower verification level VL has been written to the cell in the first pass, resulting in a distribution 1301. The programmed waveform then resumes at the lower value of the second pass. In the second pass, the programming waveform PW2 uses the second, higher verify level VH to shift this into a distribution 1303. This allows the first pass to place the unit into a rough distribution, which is then tightened in the second pass. An example of a programming waveform is shown in FIG. The first step PW1 1401 uses a lower verify level VL, while PW2 uses a higher verify level VH. Although a small step size can be used for the second pass (PW2 1403), as described in U.S. Patent No. 6,738,289, the process is the same except for the different verification levels.

A disadvantage of this approach is that each programming sequence requires the programming waveform to go through both full steps, execute 1401 and restart at 1403. If a single step is possible, the write can be performed more quickly, allowing the distribution to be subjected to an initial programming phase based on a lower verify VL, but once this initial level is reached, the process can still be slowed down and improved using a higher verify VH The distribution. This can be accomplished via "Fast Pass Write", which uses a bit line bias to program in a single step sequence of programming waveforms. This algorithm can achieve an effect similar to that of the two-passed algorithm and is described in more detail in U.S. Patent No. 6,643,188, the disclosure of which is incorporated herein in its entirety. The programming waveform QPW 1501 is shown in Figure 15, and in the first phase, except that the verification is performed at the VL and VH levels (see Figure 18 for details), the process proceeds as if the first phase of the algorithm was used twice; however, Once verification occurs at VL instead of restarting the staircase waveform, the ladder continues, but where the bit line voltage is boosted to slow down the process as it continues until the cell is verified at VH. Note that this allows the pulses of the programmed waveform to monotonically not decrease. This is further explained with respect to Figure 16.

Figure 16 shows a portion of a NAND-type array and its peripheral circuitry in all bit line architectures. Although this is similar to the configuration shown in several of the foregoing figures, only elements related to the present discussion are provided herein, with other elements omitted to simplify the discussion. Figure 16 also clearly shows the bit line clamp 621 as being separate from the other elements of the read/write stack. U.S. Patent Application (Non-Volatile Memory and Method with Power-Saving Read and Program-Verify Operations), filed on March 16, 2005, and in particular, U.S. Patent Application Serial No. 11/015,199 (2004) The details of the word line clamps are further described in the application on the 16th of the application, which is incorporated herein by reference. It should be noted that although the present invention is mainly discussed in terms of a NAND type array using all bit line architectures, the present invention is not limited thereto. As will be seen hereinafter, the present invention relates to fast pass writes or more generally to two phase programming processes and the use of data latches for monitoring and controlling this process. Thus, although this is described in terms of a particular embodiment for illustrative purposes, it can be applied more generally.

16 shows three NAND strings 610A through 610C, with each of NAND strings 610A through 610C being connected to individual sense amplifiers SA-A through SA-C 601A-C via bit line clamps 621 along corresponding bit lines. Each sense amplifier SA 601 has a clearly indicated data latch DLS 603 that corresponds to the above SA latch 214 (e.g., Figure 10). Bit line clamp 621 is used to control the voltage level and current along the bit line of the corresponding NAND string and the different clamps in the array portion are typically controlled by voltage V _{B L C} . In each NAND string 610, the source select gate (SGS 615) and the drain select gate (SGD 611) are clearly shown and are controlled by the entire column of V _{S G D} and V _{S G S} , respectively. The column of cells (613) along word line WL 625 serves as an exemplary selected column for the following description.

A selected memory cell, such as 613A, is programmed by establishing a voltage difference between the control gate and the channel, thereby causing charge buildup on the floating gate. The programming waveform QPW 1501 of Figure 15 is applied along selected word line WL 625. Consider the situation in which the cells along WL 625 are to be programmed into strings A and B instead of string C. For the cells to be programmed, such as cells 613A and 613B in columns A and B, the channel is held low (ground) to establish the required potential difference. This is accomplished by setting the bit lines BL-A and BL-B to ground (corresponding to the programmed data, "0") by the pull-down circuit; by setting V _{B L C} =V _{S G D} = V _{d d} +V _T (where V _T is the appropriate threshold voltage) to turn on the bit line clamp 621 and the drain side selection transistor; and turn off the source side selection gate by lowering V _{S G S} . This keeps the channels in NAND-A and NAND-B grounded and the programming pulses at the gates of 613A and 613B will transfer charge to the floating gate.

For cell 613C (corresponding to erased data or blocked data "1") that will not be programmed or programmed to be suppressed, the same voltage is applied to the bit line clamp, the select gate and the word line; However, the bit line BLC on the clamp 621-C is set to V _{d d} based on the data "1" latched into the sense amplifier. Since the gate of 621-C is at V _{B L C} = V _{d d} + V _T , the transistor 621-C is effectively cut off, thereby allowing the channel of the NAND-C to float. Therefore, when a program pulse is applied to 613C, the channel is pulled up and programming is suppressed.

As described so far, this procedure is largely identical to the one that will be the first pass through two programming passes and the standard single pass programming. A verification is performed between the programming pulses. Whether a unit is programmed to correspond to the VH value of the target state. In the two pass programming algorithms, the first pass verification uses the lower VL level, and the second pass verification uses the VH level. The current technique differs from the two techniques in that both the VL and VH levels are used for verification performed between pulses and in what would happen once the unit was verified at this lower level. In the two pass technique, after the lower VL level is successfully verified, the programming waveform is restarted but the verification now uses the VH level; here, the programming waveform continues, but the bit line bias is changed and the bias is boosted to reduce Slow programming rate. (In the fast pass write change, once the second phase begins, the lower verify can be discarded, leaving only the VH verify. Similarly, on the first few pulses, the VH verification can be omitted. However, due to this increase operation The complexity and savings are relatively small, so the current embodiment will include VL and VH verification during a given write process.)

Therefore, the program that sets the bit line bias at the beginning of the programming pulse will use the program verify VH data in the data latch to set the data in the sense amplifier latch 603-i to charge the bit line BL-i. Is 0 (selected by programming) or V _{d d} (to suppress unselected cells), where the bit line clamp has been set to V _{B L C} =V _{d d} +V _T to allow the bit line charge to be unselected The full V _{d d} value on the bit line. The voltage V _{B L C} can then be moved from V _{B L C} =V _{d d} +V _T to V _{B L C} =V by the bit line clamp 621-i (where the transistor 621-i is fully turned on). _{Q P W} + V _T to increase the bit line value, where V _{Q P W is} less than V _{d d} . Once one of the cells is verified at the VL level of the target state and this result is then passed back to the sense amplifier latch 603-i, the bit line voltage level is then boosted. For a selected locating element line, this raises the bit line from ground to V _{Q P W} , thereby slowing down programming; for a suppressed bit line, these remain floating. While the unselected cells will still be program inhibited, the channels in the selected NAND string will be slightly boosted, thereby slowing down the programming rate even though the programming voltage waveform supplied along WL 625 continues to rise stepwise.

Once the bit line voltage is boosted, the second phase continues along the same programming waveform, but inter-pulse verification uses the higher VH level of the target state. Since the verification unit individually, so that the corresponding latch DLS 603 since the reversing of such unit is blocked and the bit line is raised to V _{d d.} The process continues until the entire page is written.

Figure 17 depicts the use of data latch 434-i of an exemplary all bit line architecture 430 (Figure 10) to construct this process. Figure 17 only reproduces the selected items of Figure 10 (which are configured as an exemplary topology) to simplify the discussion. These include a data latch DL0 434-0 connected to the data I/O line 231, connected to the data latch DL1 434-1 of the general purpose processor 500 via line 423, typically by line 435 and other data locks. The data latch DL2 434-2 connected to the register is coupled to the sense amplifier data latch DLS 603 of the general purpose processor 500 (corresponding to 214 of FIG. 10) via line 422.

Although only two data bits are programmed into each memory storage element, each bit line has three associated data latches. (In a more general n-bit situation, the number of data latches will be n+1). The introduction of the extra latch DL2434-2 is used to manage which phase of the two programming phases are being executed by the write algorithm. As described above, and in other incorporated documents, the data latches DL0 434-0 and DL1 434-1 are used to write two data bits into the cell based on the "standard" verification level VH: When the lower page is being programmed, only one of these latches is strictly required, but when the upper page is being programmed, one of these latches is used for the upper page and the other latches are used. The lower page was previously programmed because the programming of the upper page depends on the state of the lower page in this configuration. By introducing an additional latch DL2 434-2, a latch can be used to indicate the result of the verification at the lower VL level, according to which the first phase of the write is quickly passed (where the selected component is channeled) Keep low) Change to the second phase (where the channel level is raised to slow down programming).

In Fig. 17, the tag register 434-i is used for fast pass writing of the lower page, and the lower page is constructed similarly to the condition of the binary memory. The lower page original data is loaded along the I/O line 231 to the DL0 434-0, and the data is transferred to the DL1 434-1 for VH verification, and then transmitted to the DLS 603 (where it is used to determine the bit) Whether the line is programmed or disabled.) Latch DL2 434-2 is used for VL blocking.

Program verification may be performed between programming pulses by a waveform such as that applied to selected word line WL 625 as shown in greater detail in FIG. The waveform is boosted from ground (1801) to a first, lower verify level VL (1803) and then further boosted to a higher VH (1805). Other voltage levels on the array are typical read values as described in the literature incorporated above. This allows two program verifications to be performed continuously according to the following steps: (1) The first verification level uses a lower verification level VL (1803), where the data is subsequently transferred to the data latch DL2 434-2.

(2) The second verification is the higher verification level performed when the verification waveform is at 1805. The result of VH will be transferred to the data latch DL1 434-1. During the programming pulse, the bit line bias setting will depend on the VL and VH verification results.

(3) The VH verification result is transmitted to the SA data latch DLS 603 to charge the bit line to 0 or V _{d d} .

(4) The VL verification result in the NDL is transferred to the SA data latch DLS 603 to charge the bit line from 0 to V _{Q P W} (if the cell is verified) or to keep the bit line at 0 (if the data is in "0").

This process is described in more detail in the flow chart of Figure 19.

19 is a flow diagram of a programming/verification sequence based on a latch of a read/write stack of all of the bit line embodiments. The initial conditions of the material latch are established in steps 701 to 703, the program bias conditions are set in steps 711 to 717 and the program waveform is applied, and the phases are verified in steps 721 to 725. The ordering herein is in the order of the illustrative embodiments and the order of the many steps may be rearranged as long as the corrective bias level is established, for example, prior to causing the word line to jump. In step 701, the data is read into latch DL0 434-0 on line 231 and then the data is transferred to latch DL1 434-1 in step 702. In step 703, the data is further transferred to the latch DL2 434-2. This sets the target data for the write process, where it is conventional to use a value of "0" corresponding to programming and a value of "1" corresponding to program suppression.

The programming phase begins by setting a correction bias condition based on the latch. In step 711, the voltage to the bit line clamp line is set to the normal programming level V _{d d} +V _T of the first phase of the fast pass write, and in step 712, the latch DL0/DL1 is placed. holding the values to the latch DLS 603 of the sense amplifier, wherein "0" value (program) will result in the bit line held at ground and a value "1" (inhibition) will affect the value of bit line V _{d d.} This (step 713) is set to the voltage V _{d d} + V _T of the bit line so that clamps along the channel of the selected bit line held at ground for programming and that the channel along the floating unselected bit line to inhibit program. In step 714, from the clamp voltage _{V B L C = V d d} + V T is reduced to _{V B L C = V Q P} W + V T. In step 715, the value in DL2 434-2 is passed to sense amplifier data latch DLS 603. This will be the initial value set in DL2 during the first cycle. Once the cell is verified in VL, the reduced V _{B L C} value set in step 714 will subsequently cause the bit line level to rise from 0 to V _{Q P W in} the cell being encoded, thereby slowing down the programming rate. And transition to the second fast pass write phase.

In step 717, a programming pulse (QPW 1501, Fig. 15) is applied to the selected word line WL 625, in which the bias on the other lines has been established. The inter-pulse verification phase begins at step 721 when various bias voltages are established prior to raising the selected word line to VL. In step 722, the verify waveform of the word line rises to the lower range VL (Fig. 18, 1803), and if the cell is verified, the latch in the sense amplifier SA 601 is tripped and the value in the DLS 603 is from "0. "Switch to "1", then in step 723, the result is transmitted by the general purpose processor 500 to DL2 434-2. Then in step 724, the verification level is raised to a higher range VH (1805) and if the unit is verified, the DLS 603 is set, and then in step 725, the result is transmitted by the general purpose processor to DL1 434-1.

After completing the verification phase in steps 721 through 711, the general purpose processor 500 needs to re-establish the bias conditions in the sense amplifier data latch for subsequent pulses; of course, unless all of the cells being programmed are blocked at VH, otherwise programmed The phase is terminated. This is done by returning to step 711. In step 712, the VH verification result as indicated by the value in the current DL1 434-1 is transmitted; if the cell is verified at VH, it will be programmed to be suppressed and the sense amplifier bit changes from "0" to "1" "To make the bit line go high and to inhibit further programming. In step 715, the VL verification result as indicated by the value in DL2 434-2 is now passed to the sense amplifier data latch DLS 603; if the cell is verified in VL, then the bit line is subsequently raised in step 716. Voltage.

After the data latch is properly set, the next programming pulse is applied at step 717. Subsequently, the process continues as before; alternatively, the process can change the verification waveform in Figure 18 and, for example, by eliminating the lower verification and steps 722 and 723 once they are no longer needed.

The lower page of the upper page/lower page configuration has been previously described, wherein each memory unit stores two bits of information, one bit of information corresponding to the upper page and one bit of information corresponding to the lower page. This process will be performed similar to the process described for the first programmed page with binary status and other higher complex page configurations. The remaining discussion will also be based on a two-element, upper page/lower page embodiment per cell, as this illustrates the complex state of the situation without adding unnecessary complexity that would introduce more state storage. For complex state memory using a complex page format, it is possible to encode a page into a number of cells and one of these codes will be discussed for an exemplary upper page/lower page configuration. Further details of such different encodings, how to construct such encodings, are discussed in U.S. Patent Application Serial No. 5, filed on Mar. Its comparative advantage is hereby incorporated by reference.

The "practical coding" is first used to describe the programming of the upper page using the fast write data, where the upper page write is programmed with the B and C states, which then uses two program verify cycles. State A is programmed in the lower page operation described previously. The relationship of the distribution of the states A, B, and C is shown in FIG. The unprogrammed E distribution corresponding to the data "11" is not shown in this figure.

20 shows a first distribution 1301 and a second distribution 1303 corresponding to a lower verification VL for each state used in the first programming phase of the fast pass write and a higher verify VH used in the second phase, respectively. . Under these distributions, the "preferred" of these encoding states is provided to the upper and lower pages of the material. In this encoding, when the lower page is programmed as previously described, the state with the lower page material "0" will be programmed to the 1303-A distribution using the levels VAL and VAH in the fast pass write. The upper page is written in the B and C states.

The use of the data latches DL0 to DL2 is described with respect to FIG. 21, although FIG. 21 is similar to FIG. 17, but in which the symbols indicating the use of different latches are correspondingly changed. The sub-page data is read into DL0 434-0 as indicated by the location, DL1 434-1 is used for the upper page block data and will receive the VH verification result, and DL2 434-2 is used again to maintain the VL block data. As with the lower page write, a latch is allocated for each of the two verify levels, where DL1 is used for the actual, higher verify result and DL2 is used for the phase transition to achieve fast pass writes. Low verification results.

More specifically, the VL blockade information will be accumulated in the data latch DL2 434-2, where its initial value is again transmitted from DL1 434-1 and corresponds to the original programming material to indicate whether the cell will undergo upper page programming. In this embodiment, the fast transitions of the B and C states are the same through the written bit line bias: in a variation, additional latches can be introduced to allow the B and C states to utilize different bias levels. Also, the VL blockade information is only used for temporary storage. After passing each VL verification sense, the data for VL in data latch DL2 434-2 will change from "0" to "1". The logic is such that it will not allow the "1" value to be flipped to "0" during a given programming run.

The VH blockade is also accumulated via a number of different verification sensings. Once the bit passes the verify level of its intended program state, the data in the data latch will become "11". For example, if the B state passes the verification VBH, the data "00" in the data latch will become "11". If the C state passes the verification VCH, the data "01" in the data latch will become "11". The logic is such that it will not allow the "1" value to be flipped to "0" during a given programming run. Note that for upper page programming, VH blocking can occur based on only one data latch.

U.S. Patent Application Serial No. 11/013,125, filed on Dec. 14, 2004, describes a method in which the programming of the plurality of pages held by the same plurality of sets of state memory elements can be repeated. For example, if the data corresponding to the upper page becomes available when the lower page is written, instead of waiting for the lower page to be completed before starting to program the upper page, the write operation can be switched to where both the upper page and the lower page pass simultaneously A fully programmed sequence programmed into a solid page. Fast write-through techniques can also be applied to full sequence operations.

Figure 22 shows the use of data latches DL0 through DL2 for full sequence writes, although Figure 22 is similar to Figure 17, but with corresponding changes in the symbols indicating the use of different latches. As shown elsewhere, DL0 434-0 is used for the upper page blocking data and will receive the corresponding VH verification result, DL1 434-1 is used for the lower page blocking data and will receive the corresponding VH verification result, and DL2 434-2 is again Used to keep VL blocked data. Unlike the situation in single page programming where the initial DL2 434-2 value corresponds to the initial programming material, the initial values at the full sequence transition will account for the upper and lower page data. Therefore, instead of just loading the appropriate, single-page raw programming data into the DL2 434-2, if the latches DL0 and DL1 are both "1", then only the data is set to "1".

In an exemplary embodiment, the full sequence operation with fast pass writes can include the steps of: (1) loading the first page of data into latch DL0 434-0 and the lower page can begin programming as described above .

(2) The lower page programming data has been transferred to the latch DL1 434-1 as described above for the lower page programming, and the latch DL0 434-0 can be reset and ready to continue loading another page, so that The upper page of the same word line WL 625 is allowed to be transferred during use.

(3) After the completion of the loading of the upper page, the programming of the lower page may not be performed. In this case, according to the full sequence programming described in U.S. Patent Application Serial No. 11/013,125, the programming algorithm can be converted to simultaneously programming two bits to speed up the programming. If the upper page data is not available or otherwise cannot be loaded before the completion of the page write, the upper page will be programmed by itself as described above.

(4) Before the lower page program is converted to full sequence conversion, the lower page source data may have been blocked to "11" for the unit that verified A by programming. This data should be read at the A level to reply to its original data, since the two-quantity full sequence write requires both the lower page and the upper page data to be programmed.

(5) In this two-quantity full sequence programming algorithm, program verification of A, B, and C states can be performed simultaneously or separately. The two latches can also block the blocking process at the same time.

(6) After programming data A and B are completed, only the C state remains to be programmed so that the process is similar to binary writing. The remaining programming data can be transferred to DL1, allowing DL-0 to be reset to "1" for the next page of data to be loaded.

The previous discussion using fast write to top page programming is based on encoding states E, A, B, and C conventionally into upper and lower pages, as shown in FIG. Other codes are generally useful, as developed in U.S. Patent Application Serial No. 5, filed on Jan. 16, 2005. Two examples are shown in Figures 23 and 24, the first example of which shows "LM old" encoding, and the second example shows "LM new" encoding. In these two conditions, the dashed line indicates the distribution of the intermediate states as a result of the lower page programming, wherein the lower page writes using fast pass writes in both LM codes are performed similarly to the lower page programming described above. The upper page programming then moves the cell from the middle distribution to the final target state of the B or C distribution and programs the E distribution of the cell from the "11" state to the A distribution with the "01" data. The use of fast pass write top page writes in two LM codes is similar to the upper page program described above with respect to conventional coding, with the difference that since state B and state C are from intermediate states (dashed lines), the lower page is also Will be blocked.

For the two variants of LM coding, although the fast pass write is performed in the same manner, the verification of the switching state is such that B_new = C_old and B_old = C_new because the two bits are differently assigned to the four states. This change is implemented by the general purpose processor 500 as is the change caused by the conventional encoding. The data transfer logic via the general purpose processor 500 will depend on the encoding and therefore it will be different.

The LM code upper page programming algorithm is also similar to the full sequence fast pass write algorithm, which is similar in that the VH blockade data is updated after VH verification. For the LM old encoding, if the lower page is switched with the upper page encoding, the upper page is also the same as in the conventional encoding, in which case the upper page of the LM old encoding is identical to the full sequence programming.

Figure 25 again shows the allocation of the data latch and its LM code in a manner similar to Figure 22 and other similar figures. The lower page data is read into DL0 434-0, the data based on the VH upper page is kept in DL1 434-1, and the VL block data for controlling the phase shift of the fast write technology is again distributed to DL2. 434-2.

Since there is no additional state in the C state, this situation is similar to the binary state, and the similarity is that the important result is that the C distribution is well defined with the distribution below it, but over programming is not a major interest (at least until the state determination). Therefore, fast pass writes are preferred for the A and B states, but for the C state, fast pass writes are used and only the VH level of this state is used. (For memory with other numbers of states, these instructions apply to the highest lying state or, more specifically, the most programmed state).

For example, if all three states use fast pass writes, the programming and verification are usually simpler to construct: the same way for all three states; however, because the C state distribution can be wide and still The range is accepted, so for the C state, fast pass writes can be omitted to shorten the programming time.

As mentioned, using fast pass write (QPW) for lower states but not fast pass writes for C states can complicate the programming algorithm. For example, at a particular point in the write process, the programming pulse is followed by verify A (with QPW), verify B (with QPW), and verify C (without QPW), followed by another programming pulse. Since the fast-passing write algorithm described above uses two data transfers for the programming pulse (first data transfer to block VH and second data transfer to block VL), the first data transfer has no problem for all three states. However, in the above configuration, the second transfer will cause state C to generate a programming error. Since state C will not verify the VCL at a lower level, the DL2 434-2 data latch is not updated for this bit line. If the bit line needs to be blocked after passing the high VCH verify level of the C state, the VH blocked data latch will transmit a "1" to the SA data latch for program inhibit after the first data transfer. However, the VL data latch (DL2 434-2) will still hold the data because there is no verification result to update it. Therefore, the second data transfer will transmit "0" to the bit line DLS 603. This will cause the precharged bit line to be discharged to zero, causing this bit line to be over programmed.

To overcome this problem, when the fast pass write is not used for the C state, the algorithm is modified by updating the VL data latch (DL2 434-2) using C-verification at the high level of the VCH. Therefore, if the unit passes the verification at the C level of the VCH, both the VH and VL blocking data will become "1" and the programming will be suppressed. Also, if the A and B states complete writing and the C state is not complete, the programming algorithm can switch to standard programming without fast pass or no QPW algorithm because only the C state is left and it will only use the corresponding VH Verify the level. In this case, only a single data transfer (VH level) will be performed (the VL level is not used).

Data recovery after programming failure

In the complex state memory, a method of storing data is written to the memory in separate pages, such that (in the four state instances) each 2-bit memory cell stores one bit from the upper page and from the lower page. One yuan. The normal configuration writes the lower page data and after a while, writes to the upper page in a separate process. When the programming of the upper page fails, the data content of the lower page data is also lost. In the main aspect of the invention, both the lower page and the upper page material can be retrieved and copied to another location without having to maintain a copy of the data buffer on the controller or require additional assistance from the controller. This allows the buffer on the controller to be released for use in other materials, or to allow the number of buffers to be reduced on the controller to be reduced, which can be a valuable space. In detail, it can be implemented on the memory by the state machine in the memory control circuit (310) (312 in FIG. 7A) and the data latch in the sense amplifier region (430 in FIG. 8 and FIG. 15). The process. It should be noted that although the description is based on this particular embodiment, the aspects of the invention discussed in this section rely only on data latches DL0 434-0 and DL1 434-1 (which correspond to the exemplary embodiments) Two digits stored per unit), and DL2 434-2 is not required. As the page size used in memory systems continues to increase, the resulting improvements are even greater.

More specifically, when programming a 2-bit or more bit on a physical unit, if the write fails, the same data should be able to be programmed to another location instead of being lost. A problem that arises when two (or more) bits are configured in a separate page is that the failure to program one page will affect the data previously programmed to other pages on the same physical location. For example, in the conventional encoding (Fig. 20), the page state "0" above C is from the E state, so that if it fails to program to the C state, it can be between the E state and the C state. The information on the lower page may also be lost anywhere. The lower page information may also be lost because the lower page may have been programmed to be part of a different data set long ago.

Consider a conventional encoding example of a 2-bit configuration in two pages, as shown in Figure 26a. This figure shows an array or portion of array 700 and a number of representative word lines, where dashed lines indicate that two pages can be written together in an exemplary all bit line architecture. Pages 0 and 1 are lower pages and 2 and 3 are upper page word lines 701. (0, 1 is written on the line to indicate that it is written first, as opposed to its naming scheme). If pages 2 and 3 are subsequently programmed to have errors that exceed ECC repair capabilities, not only pages 2 and 3 need to be programmed, but pages 0 and 1 need to be reprogrammed to another location.

The lower-middle (LM) coding (Figs. 23 and 24) is designed to reduce the coupling effects of bit line to bit line and word line to word line. The page configuration is shown in Figure 26b. In this case, the upper page of the word line 701 shared with page 0, 1 is now 4, 5 instead of 2, 3. When pages 4, 5 are erroneously written and the verification fails, pages 0, 1 will also need to be corrected. Since the page number of the upper page is not continuous with the lower page on the same word line, the user will not maintain the lower page information so that the pages can be reprogrammed.

As can be seen with reference to Figure 24, the lower page of the LM is also corrupted by the upper page programming failure. This is due to the fact that the lower page is not initially programmed to the B level but to the distribution with the dotted line A level. If the lower page is initially programmed to the B verify level, the failure of the upper page will not affect the integrity of the lower page data, but the advantages of fast lower page programming will be eliminated. If the upper page data can be replied even if the upper page fails to be programmed, it will once again become a huge advantage. If the upper page programming data is still in the controller data buffer, and if the lower page is retained, it can be combined and copied to another good WL. Bad data will be used for the entire word line, and the data can be marked as bad (using the flag). However, this does not require maintenance of the data on the controller. Figure 27 shows this schematically.

Figure 27 is a schematic diagram showing the flow of data as it is received from the host and programmed into the memory array 300. Data is first received at controller 801 (typically different from control circuit 310 (Fig. 7A) on memory 811) which contains a number of cache memories 803 for buffering the data it collects and subsequently The data is transferred to the memory 811. Since the cost of the buffer memory and the space of the area are usually expensive, it is preferable not to have more than the required memory; however, this buffering is required in typical memory operations, where the controller space A significant portion can be dedicated to the buffer memory. This is especially true as the page size increases. The data is then transferred from controller 801 to memory 811 for transfer to the data latch of read/write circuit 370 from which data can be written to memory array 300.

In the previous configuration, in order to ensure data integrity in the event of a programming failure, since the replica in the latch of write circuit 370 is lost during the write process, a copy of the data needs to be maintained in the controller in buffer 803. on. In accordance with one aspect of the present invention, data can be reconstructed on memory 811 based on the remainder of the latch combined with one or more read processes without having to maintain a copy in controller 801. The reconstructed material can then be written to another location in array 300. This allows the buffer 803 to be freed for new data or for other uses, or even to allow for a reduction in the number of buffers since there is no need to maintain the same amount of data in the buffers.

This basic process is described in the U.S. Patent Application Serial No. 11/013, filed on Jan. 14, 2004, which is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety in its entirety in In the "Overlapped Programming of Upper and Lower MLC Pages" section, the application describes the ability to switch from writing only the lower page data to simultaneously writing the upper and lower page data. As described elsewhere, and as further developed below, even if there is a programming failure during the programming of subsequent state C and we need to rewrite the data, the controller does not need to transfer the new data of page n to the memory; we still have the lower part Page information, and we can reply to the upper page by simply reading the cell status using the V _{R B} threshold (see Figure 10C). In this event, the error will be reported to the controller, the received data of the lower page n+1 will be discarded, and the reply data of page n will be written to the new location pointed to by the controller.

The conventional encoding is first returned (Fig. 20), and an exemplary embodiment of the data recovery process is described when the lower page is first written and then the upper page is written.

The latch assignment in a single page programming mode is shown in FIG. In the single page programming mode in conventional encoding, latch DL0 434-0 is used to hold the lower page material to prevent sensing of the lower page before starting the upper page programming. The upper page failure condition caused by very slow bits can be handled in several ways: 1) the lower page information can be triggered in two states; 2) the information can be transferred to DL1 434-1 and then programmed to another word line; or 3) The corresponding upper page in the buffer 803 of the controller can be moved into the read/write circuit 370 and 2-bit programming (full sequence programming) can be started in the next word line.

In order to save data transfer time, it is generally preferred to reply to the upper page data after the upper page fails to be programmed.

Figure 29 shows a situation in which the lower page material is in programming and will be used as the first instance of data recovery. If the memory is to be programmed to the A state (lower page data "0"), the successful write will be verified in the A state verification level and placed somewhere in the A distribution. If the unit cannot be verified, it can be anywhere between the E-state distribution and the lower end of the A-distribution. When read with the value of readA, if it is higher than readA (even if it cannot be verified), it can still be read as A state (return "1" to the sense amplifier). If instead it is somewhere below the readA level (as shown by X), the sense amplifier will return "0" and the unit will be mistakenly read as the E state. The process is summarized in the table of Figure 30, which assumes that unprogrammed data (i.e., cannot be verified) will cause "0" to remain in the data latch, as shown in line (1). If the unit has been programmed and successfully verified, it will change to "1" in the data latch.

In FIG. 30, the top line corresponds to the lower page data to be written in the cell and it is assumed that there is a write failure such that some cells to be written as the A state are below readA, as shown in X of FIG. The data reply starts with the normal readA logic, DL1 434-1=~SA, where line (2) of Figure 30 shows the result. (This discussion assumes that DL1 434-1 maintains the data latch for programming blockade information and the symbol ~SA means the reverse data of the SA data and the "&" means the logical AND (AND). Since X is below readA, the line (2) Read 1 for both target data states. The recovered data (line (3)) is the logical sum of lines (1) and (2): DL1 434-1=~SA & DL1 434-1.

In the case where the upper page programming fails, the following programming needs to be considered for the B and C states. The reply to the upper page data uses the same logic to correct the B and C errors in the conventional code and is shown in FIG. This procedure assumes that the lower page completes the write correctly. Although the lower page will be corrupted by the upper page failure, the lower page good data is still intact because it reads the latch before the upper page is programmed. Therefore, only the upper page needs to be replied and the lower and upper pages can then be reprogrammed somewhere else.

The standard read process for the B state is provided by: normal readB: DL1 = readB = ~ SA.

The reply process will consist of the following steps: Reply to readB logic: DL1=~SA AND DL.

This equation shows that the programming data maintained in DL1 will be combined with the read data in the B state in the sense amplifier (SA). The logic is the logical sum of the reverse data from the SA (readB result) data and the remaining data in DL1. The logically combined data will be stored back to DL1.

As shown in Figure 31, this will correct B and C errors because both B and C errors that need to be treated as failed writes can place the cell anywhere between the E and C distributions. The top line of Figure 31 shows the target data status and the new line display is read into the lower page of DL0 434-0. Line (1C) indicates that the "01" state did not successfully complete programming and "0" remains in DL1. The remainder of the state has been programmed so that "1" is retained in DL1. After the B level (2C) sense word line, the result will be stored in the sense amplifier SA. Logic inversion can be performed via processor 500, as shown in FIG. Line (3C) is the result of the logical AND operation combining the SA result with the previous DL1. Line (3C) shows the correct upper page encoding for all four states.

In the two conditions shown in Figure 31, the final line (2C, 3C) produces the correct upper page data ("1" for E and A states, "0" for B and C states). Lines (1B) through (3B) show the status of the reply B bit in the case of a programming failure. The code in line (1B) is the remaining data when the B state is not programmed. "0" exists in the B state ("00" state). After the exact same procedure as for the "01" state reply logic, the B sensed result is combined with the remaining data in DL1 using a logical AND operation. The final result is stored back in DL1. Line (3B) is used for proper encoding of the top pages of all four states. This description of the reply logic can be applied to B and C in the case of programming failures. In the memory data recovery operation, the state machine does not usually understand the failure mode. Therefore, it is only feasible when a logical equation is needed to recover all possibilities in the event of a programming failure.

The following invention can also be constructed when two (or more) bits are programmed simultaneously. Even in the upper page/lower page configuration, 2-bit programming can occur as part of the lower page to full sequence conversion, such as in U.S. Patent Application Serial No. 11/013,125 ("Overlapped Programming of Upper and Lower MLC Pages"). As described, or when programming fails, the upper and lower pages are simultaneously written to the new location. The 2-bit reply logic can also be used to configure the two bits to be on the same page.

In full sequence programming, write errors can occur on the lower and upper page data. The latches of the exemplary embodiment are shown in Figure 32 to allocate and reuse conventional encodings. Both the lower page and the upper page data need to be replied, and then the failed write can be ended anywhere between the E and C distributions. As long as the data is encoded in a conventional encoding, the full sequence condition can be replied to by the same reading logic as used for a single page. Several combinations need to be checked, as shown in Figure 33. As mentioned above, the "unit data" title refers to the E, A, B, and C target states in the "upper page, lower page" format.

In the conventional encoding, the normal reading of the lower page data (readA OR~readC); that is, the reverse result of the readA result and the readC result is logical OR (OR), where readA and readC (and readB) are from Reverse data (~SA) of the data of the sense amplifier. The normal upper page reads exactly readB.

In the case of a write error, the following set of steps can be used to reply to the data. It is assumed below that the lower page data is in DL1 434-1 and the upper page data is in DL0 434-0. The upper page returns the reading again as: (i) readB; (ii) readB&DL0 → DL0; this combines the readB result with the DL0 434-0 residual data and stores the result in DL0 434-0. The lower page reply will require readA and readC replies: (i) readA; (ii) readA AND DL1 → DL1; this step combines the readA result with the remaining data of DL1 434-1 (AND logic) and stores the result in DL1 434- 1 in.

(iii) readC; (iv)~readC| DL1 |(~DL0 & DL1) → DL1.

This step combines the reverse readC result with the DL1 434-1 previous data (OR logic) and also checks if the bit is 01 and stores the result in DL1 434-1. The readC data and DL1 434-1 data here are not enough to reply to the original data. The failed C state must be confirmed by checking the DL1 434-1 and DL0 434-0 using the AND logic (~DL0 & DL1). (This is shown as step 5' in Figure 33, and is shown clearly in some cases only in some cases.)

At the end of this process, the lower page data will have been stored in DL1 434-1 (step 6) and the upper page data will have been stored in DL0 434-0 (step 4).

Figure 33 shows the results of these steps for various conditions. In each case, line 4 shows the reply to the top page and line 6 shows the page under the reply. The logical OR (OR) is expressed as | in the table (for example, readA|~readC is readA OR~readC). Where the table indicates "0/1", this indicates whether the visual unit is present and returns any result. Step 5' is only shown in the C error condition. Since the state machine usually cannot understand what type of error has occurred, the additional logic operations performed in the C error condition also apply to situations with other errors, although this operation is not required here. Therefore, all logic operations apply to all of the conditions listed in this article. For the sake of simplicity, step (5') is not clearly shown in many cases, as additional logic operations from the data listed in the table will not produce different results.

In Figure 33, various conditions are shown in an order corresponding to the three programming states of the example: when the readA process passes and then when it fails, the A state is incorrect, followed by the B state error, followed by the C state error. In the order of the steps in Fig. 33, it should be noted that various reading processes are performed in the order of states (A, B, C), and therefore, the upper page reply step belongs to the middle of the lower page reply step; that is, the step ( 1), (2), (5), and (6) correspond to steps (i) to (iv) of the lower page reply described above, respectively, wherein (3) and (4) correspond to the upper page reply (i) ) and (ii).

Assuming the status of the A state is wrong, the upper page data in DL0 will all be 1, where the remaining lower page data in DL1 has the wrong 0 in the A ("10") slot. In step (1), the readA result will be 1 for the "10" state, and when combined with the DL1 content by logic, it is directed to row (2). The lower page data reply continues readC in step (5), and then combines the results of step C and step (2) according to logic in line (6) to reply to the lower page data. The upper page material is provided in line (4), wherein step (3) is omitted because the error is assumed for the A state herein.

Assume that the condition of the B error produces an incorrect zero in the "00" slots of DL0 and DL1. In step (1), the readA visual unit ends where 1 or 0 is generated: in either case, the logic provides zero for the "00" column in row (2). In step (3), readB is continued, thereby generating 1 for "00", thereby providing a reply to the upper page material in step (4) when combined with DL0 according to logic. Returning to the lower page reply in step (5), the results of readC are obtained and combined in step (6) to provide the correct lower page material.

Assuming a C-state error, the upper page data in DL0 will have an erroneous 0 in the "01" line. Assuming that the readA operation passes, steps (1) and (2) will correctly have (1, 0, 0, 0) for the four states. However, in step (3), the viewcell is how far it is, it can end below or above the readB level and can provide 1 or 0 for the "01" column. In either case, the logic will correct this and reply to the upper page data in line (4). Returning to the lower page reply, because it is assumed that the error is in the C state, step (5) provides zero for all rows. Therefore, as mentioned above, in this case, the readC data and the DL1 434-1 data are insufficient to reply to the original data and the step (5') is used to correct this. The C state of the failure is then confirmed by checking the DL1 434-1 and DL0 434-0 using the AND logic (~DL0 & DL1), which is combined with the row (2) in step (6) to provide a page after the reply. data.

Assuming that the C state is wrong and the A state also fails (ie, the C error causes the cell to be programmed only below the A state read level), each of steps (1) through (3) provides an error for the "01" row. 1. For the upper page data, the correct data is returned in step (4) as in the case of the aforementioned C failure and A pass condition. In step (5), readC again provides 0 for all states and needs to correct readC by step (5'), providing 1 in the "01" column, then migrating it to row (6) and replying Below the page information.

Since the memory will be aware of which programming mode (upper page, lower page, or full sequence) it is operating on, the appropriate reply mode can be selected when the return programming fails. In each case, the reply process involves combining the remaining (failed) verification data in the latch with the result of one or more readings. Based on these combinations, it is then possible to use only the data latches and state machines without having to maintain a copy of the data in the buffer on the controller (or on the memory once loaded into the latch) to remember Respond to the correct information.

The procedure for "LM" encoding is now described, starting with the "LM old" encoding shown in Figure 23. In LM encoding, the page order is typically the order shown in Figure 26B, where the upper page can be programmed much later than the lower page on the same word line. Therefore, the lower page data must be read at the beginning of the upper page programming. The top page programming in LM encoding will be similar to the 2-bit programming state in conventional encoding.

In the LM old coding, the coding is similar to the conventional coding, but the lower page is exchanged with the upper page: the upper page (LM old code) = the lower page (known).

Lower page (LM old code) = upper page (known).

The upper page normal reading is therefore readA |~readC; that is, the readA result is logically ORed with the reverse readC result to form the lower page data. The normal reading of the lower page is followed by readB. Since the encoding has this similarity, the recovery method is also the same as the conventional one.

It is assumed below that the latch is allocated as the LM lower page data is in DL0 434-0 and the upper page is in DL1 434-1. The upper page replies to read: 1) readA; 2) readA AND DL1 → DL1; this step combines the readA result with the DL1 434-1 residual data (AND logic) and stores the result in DL1 434-1.

3) readC; 4) readC| DL1 | (~DL0 & DL1) → DL1; combine the reverse readC result with the previous data in DL1 434-1 (OR logic), and also check if the bit is 01 and the result Stored in DL1 434-1. Here the readC data and DL1 data are not enough to reply to the original data. The failed C state must be confirmed by checking DL1 434-1 and DL0 434-0 using AND logic (~DL0 434-0 & DL1 434-1).

The lower page replies to read: 1) readB; 2) readB & DL0 → DL0; combines the readB result with the DL0 434-0 residual data and stores the result in DL0 434-0.

This step combines the readB result with the remaining DL0 434-0 data and stores the result in DL0 434-0.

3) If the upper page of the word line is not programmed, the LM flag will be checked (indicating whether the upper page is programmed with LM code) and readA will be executed.

4) readA & DL0 → DL0.

This step combines the readA result with the remaining DL0 434-0 data and stores the result in DL0 434-0.

The "LM New" code is shown in Figure 24. In this encoding, the normal upper page reading is provided by (readA OR~readB) AND readC; that is, the readA data will be first combined with the reverse readB data using OR logic, and the combined result will be further combined with the readC result using AND logic. combination. The normal lower page reads exactly readB because, although the LM flag needs to be checked, it has the LM old code lower page: in this code, if the upper page is not programmed and only the lower page has been written to the word line, Then use readA instead.

The program again assumes that the latch is assigned to the LM lower page data in DL0 434-0 and the upper page is in DL1 434-1. The reply data of the lower page is the same as the reply data of the old code of LM and is obtained again by readB AND DL1, where DL1 refers to the remaining DL1 434-1. The response reading of the upper page corresponds to: ((readA AND DL0)OR~readB OR(~DL0 AND DL1)) AND readC AND(DL0 OR DL1).

When the data latch is reused, this last equation contains the order of operations; for example, if the result of the later operation is stored back to DL0, it should be done before the (readA AND DL0) operation (~DL0 AND DL1) operation. In other embodiments, the result of the operation (~DL0 AND DL1) may be temporarily stored in another data latch (such as DL2), which may be combined with other logic operations from the latch if necessary. The table of Figure 34 shows the various stages of the process for replying to the upper page under different conditions in the LM new encoding.

In Figure 34, some steps are not shown, especially when these steps produce unimportant results; for example, DL0 OR DL1 is not important for A errors 1 (because DL1 is 1 for all conditions) And it is not important for B error (because DL0 is 1 for all cases). In each case, the upper page's reply reading is stored in DL1 and the lower page data (read in at the beginning of the programming algorithm) is stored in DL0. Since the status of the A error, the error is reflected in the "01" column of the remaining data in the DL0. In the step (1), readA is then supplied with 1 in the "01" column, and then corrected in step (2) by ANDing with DL0. Step (4) then combines ~readB (from step (3)) with the result of step (2), and then further combines it with readC (step (5)) in step (6) to obtain correction of the upper page data. . In this case, the expressions (~DL0 AND DL1) and (DL0 OR DL1) are not explicitly calculated because they do not participate in the expression.

For the B error condition, DL0 is now 0 for the "10" column, where DL1 is again 1 for all conditions. Therefore, (DL0 OR DL1) is again 1 for all conditions and is omitted in the step. It can be done before line (1) (~DL0 AND DL1) and stored in another data latch such as DL2. The result of (~DL0 AND DL1) will be "0010", of which only "10" lines have "1". In step (1), readA may provide 1 or 0, and (1, 0, 0, 0) is provided when it is combined with DL0 in step (2). Line (3) provides ~readB, how far the viewcell is programmed and may or may not provide zero. All of the above results can be combined in row (4) with OR logic and stored back to DL0. In step (5), readC provides (1, 1, 1, 0), which will be lower than readC, since the state ends when it cannot be verified for B. Finally, using row (4) (in DL0) AND of readC provides a reply to the top page data in row (6).

Assuming the C state fails, this will provide zero in DL0 and DL1. If the row (1) operation result is stored in DL0, the initial step (DL0 OR DL1) (line 0) is executed before row (1). The logic operation (DL0 OR DL1) should be stored in another data latch such as DL2. The result of readA (here, it is the same as readA AND DL0) is in row (1), followed by ~readB in row (2). Rows (1) and (2) are then ORed in step (3). (Because DL0=DL1 here, (~DL0 AND DL1)=0 and omit it.) Since readC is 1 (row 4) in all cases, it will have the same value when AND is performed with row (3). Provide a return (5). Since DL0 = DL1 = (1, 1, 1, 0), in line (6) (DL0 OR DL1) = (1, 1, 1, 0). The lines (5) and (0) are ANDed and then the upper page is provided in the online (6). The correct upper page data is again "1010".

As already mentioned, Figure 34 only shows the upper page reply process for LM new encoding. As shown in FIG. 23 and FIG. 24, both the LM old and the LM new code have the same encoding of the lower page data, and for the LM new encoding, can be reused as described above with respect to the LM old encoding (readB AND DL1) ) to reply to the next page information.

Therefore, for all encodings, no matter which encoding is being used, the following simple rules can be used for data recovery. In each case, the logical data is used to combine the remaining verification data with the result of one or more read operations by using non-overwrite logic (which combines the remaining data in the data latch with the sensed result) ) to draw the expected target data.

As shown in Figures 23 and 24, the two LM codes initially program the lower page to a broad X distribution as described in U.S. Patent Application Serial No. 11/083,514, the disclosure of which is incorporated herein by reference. In both cases, the upper page programming failure will corrupt the previously programmed lower page data since the two encodings separate the two bits on the same physical unit into two separate logical pages. Since the lower page has been programmed a long time ago, data recovery becomes very important as this data is no longer maintained by the controller memory. Even if the lower page is programmed relatively recently, maintaining the lower page in the controller will require a lesser amount of buffer.

In conventional encoding, the blocking of the upper page write will only occur on the data latch in which the upper page programming data is stored; therefore, the lower page data is complete during the upper page programming blocking process. However, in LM encoding, the lower page is rough programmed to the intermediate X state, where the upper page write is equal to 2-bit programming because all A/B/C states need to be programmed. In this case, the two data latches DL0 and DL1 are used to store the 2-bit programming data to be blocked, where "0" is changed to "1". In this case, the lower page information may be permanently lost. To avoid this, the following mechanism can be used to keep a good copy of the lower page material for the user.

In the first embodiment, the material latch is allocated according to the following diagram as in Fig. 35. Here, DL0 434-0 is the bit data read from the array: in the LM code, the bits used for erasing and A, B, and C states will be 1, 1, 0, and 0, respectively. The DL1 434-1 will maintain the upper page programming data from the user input for current programming. The old LM codes used for erasing and bits above the A, B, and C states will be 1, 0, 0, 1, respectively.

Since the A state has a lower threshold voltage than the B and C states, a program verification A is required at the beginning of the programming algorithm, where the B programming verification begins after a number of programming pulses, as in U.S. Patent Application Serial No. 11/013,125 More detailed description. When the unit with the A data is programmed, the blocking system is temporarily stored in DL1 434-1, where "0" is inverted to "1". DL0 434-0 will not change. When the B state begins to verify, the DL0 data will also be changed for blocking. Therefore, the data in DL0 will be complete during the time period of A verification before the B state begins to be verified. In a typical system, this time is typically about 150 μs, which is used by the user to capture and toggle the lower part metadata to copy it to another location (such as buffering or using it on a memory or controller). For a latch on another physical page, it is sufficient time. For the recovery of the lower part metaprogramming data during the upper page programming failure, the LM new encoding status will be similar to the LM old encoding because the lower page is equally encoded for both encodings.

Another embodiment that can be used in LM encoding to obtain a good copy of the lower page material uses the extra latch DL2 434-2 for latching, allowing the original material to be held until the end of the write. Unlike the other embodiments in this section, since DL0, DL1, and DL2 are all used herein, the type of cache programming described in U.S. Patent Application Serial No. 11/097,590 may not be incorporated. The data latch assignments herein are shown in FIG.

As shown in Figure 36, DL2 is used for program blocking, not for fast write blocking. Therefore, if a fast pass write algorithm is also used, an additional latch DL3 will be added for QPW blocking (VL blocking). In either of these variations, using DL2 in this manner allows the lower page material to remain intact throughout the programming algorithm.

It should be noted that such methods of replying to lower pages in the LM code do not assume that the coding failure is due to slow bits. As one of the data recovery methods in the previous discussion, it also does not require reading to be executable. However, these final techniques assume that the upper page material will be held in the controller or buffered. This method of replying for the lower page can be more useful in many situations because it neither assumes any particular failure mode nor assumes that the memory unit is still readable.

For all of the foregoing embodiments, it should be noted that this is primarily described for a 2-bit status per unit. These techniques are easily extended to systems that store 3, 4 or more bits per cell for complex page format and full sequence operation. For example, for a given embodiment with respect to a 2-bit condition, the 3 and 4 bit conditions will require an additional one and two data latches, respectively.

While the invention has been described with respect to the specific embodiments thereof, it is intended that the invention

10. . . Memory unit

12. . . Split channel

14. . . Source

16. . . Bungee

20. . . Floating gate

20'. . . Floating gate

30. . . Control gate

30'. . . Control gate

34. . . Selecting location line

36. . . Selecting location line

40. . . Select gate

42. . . Word line

50. . . NAND unit

54. . . Source terminal

56. . . Bungee terminal

100. . . Memory array

130. . . Column decoder

160. . . Row decoder

170. . . Read/write circuit

180. . . Read/write stack

190. . . Read/write module

212. . . Sense amplifier stack

214. . . SA latch

231. . . I/O bus/data I/O line

300. . . Memory array/memory unit two-dimensional array

310. . . Control circuit/controller

311. . . line

312. . . state machine

314. . . On-chip address decoder

316. . . Power control module

330. . . Column decoder

330A. . . Column decoder

330B. . . Column decoder

350. . . Block multiplexer

350A. . . Block multiplexer

350B. . . Block multiplexer

360. . . Row decoder

360A. . . Row decoder

360B. . . Row decoder

370. . . Read/write circuit

370A. . . Read/write circuit

370B. . . Read/write circuit

400. . . Read/write stack

410. . . Stack bus controller

411. . . line

421. . . Stack bus

422. . . Line / SABus / SBUS

423. . . Line/DBus

430. . . Data latch stack

434. . . Data latch

435. . . line

440. . . I/O module

500. . . General purpose processor

501. . . Transfer gate

502. . . Transfer gate

505. . . PBUS

507. . . Output

509. . . Flag bus

510. . . Input logic

520. . . Processor latch

522. . . Transfer gate

523. . . Output

524. . . p transistor

525. . . p transistor

526. . . n transistor

527. . . n transistor

530. . . Output logic

531. . . p transistor

532. . . p transistor

533. . . p transistor

534. . . p transistor

535. . . n transistor

536. . . n transistor

537. . . n transistor

538. . . n transistor

550. . . n transistor

601A. . . Sense amplifier

601B. . . Sense amplifier

601C. . . Sense amplifier

603. . . Sense amplifier latch

611. . . Bungee selection gate

613A. . . Selected memory unit / gate

613B. . . Selected memory unit / gate

613C. . . Selected memory unit / gate

615. . . Source selection gate

621. . . Bit line clamp

625. . . Select word line

700. . . Array

701. . . Upper page word line

801. . . Controller

803. . . Cache memory

811. . . Memory

1301. . . distributed

1303. . . distributed

1401. . . First step PW1

1403. . . Second pass PW2

1501. . . Programming waveform QPW

1801. . . Ground

1803. . . First, lower verification level VL

1805. . . Higher VH / higher range

Figures 1A through 1E schematically illustrate different examples of non-volatile memory cells.

Figure 2 illustrates an example of a NOR array of memory cells.

FIG. 3 illustrates an example of a NAND array such as the memory cells shown in FIG. 1D.

Figure 4 illustrates the relationship between the source-drain current of four different charges Q1 to Q4 and the control gate voltage for which the floating gate can be stored at any one time.

Figure 5 schematically illustrates a typical configuration of a memory array that can be accessed by a read/write circuit via a column and row decoder.

Figure 6A is a schematic block diagram of an individual read/write module.

Figure 6B shows the conventional read/write stack of Figure 5 constructed from a stack of read/write modules.

Figure 7A schematically illustrates a small memory device having a set of segmented read/write stacks in which an improved processor of the present invention is constructed.

Figure 7B illustrates a preferred configuration of the small memory device shown in Figure 7A.

Figure 8 schematically illustrates the general configuration of the base components in the read/write stack shown in Figure 7A.

Figure 9 illustrates a preferred configuration of a read/write stack in the read/write circuit shown in Figures 7A and 7B.

Figure 10 illustrates a modified embodiment of the general purpose processor shown in Figure 9.

Figure 11A illustrates a preferred embodiment of the input logic of the general purpose processor shown in Figure 10.

Figure 11B illustrates a truth table for the input logic of Figure 11A.

Figure 12A illustrates a preferred embodiment of the output logic of the general purpose processor shown in Figure 10.

Figure 12B illustrates a truth table for the output logic of Figure 12A.

Figure 13 shows two distributions of storage elements corresponding to the same memory state of the low and high verify levels.

Figure 14 illustrates an example of a programming waveform used in a two pass write technique.

Figure 15 illustrates an example of a programming waveform used in the fast pass write technique.

Figure 16 shows a portion of a NAND-type array and its peripheral circuitry in all bit line architectures.

Figure 17 depicts the use of the data latch of Figure 10 to construct a fast pass write for the lower data page.

Figure 18 shows an exemplary verification waveform to illustrate two verification levels.

Figure 19 is a flow chart of a fast pass write algorithm.

Figure 20 shows the distribution of memory cells for conventional two page encoding.

Figure 21 depicts the use of the data latch of Figure 10 to construct a fast pass write for the upper data page in the conventional encoding.

Figure 22 depicts the use of the data latch of Figure 10 to construct a fast pass write for full sequence programming.

Figures 23 and 24 show the distribution of memory cells alternating between two pages.

Figure 25 depicts the use of the data latch of Figure 10 to construct a fast pass write for the upper data page in an alternate two page encoding.

26A and 26B show different methods of assigning upper and lower pages to word lines.

Figure 27 schematically illustrates the transfer of data from the host to the memory during the writing process.

Figure 28 shows the data latch assignment for upper page/lower page programming.

Figure 29 illustrates the failed page write process.

Figure 30 is a table showing the lower page data reply operation.

Figure 31 is a table showing the upper page material reply operation when "practical encoding" is used.

Figure 32 shows a data latch assignment for full sequence, 2-bit programming.

Figure 33 is a table showing the recovery operation when using full sequence, 2-bit programming.

Figure 34 is a table showing the data reply operation when "LM new encoding" is used.

Figures 35 and 36 show data latch assignments for replying to the lower page data in the codes of Figures 23 and 24 for both embodiments.

Claims (21)

A method of operating a non-volatile memory, comprising: performing a programming operation on one or more non-volatile memory cells to write a corresponding target data state to each of the memory cells The programming operation includes maintaining verification data in one or more of the data latches corresponding to each of the memory cells, the verification data indicating whether each of the memory cells has been written as The respective target data status; determining whether the programming operation has failed, and failing to successfully verify that one or more of the memory units are written as their target data status; and in response to determining that the programming operation has failed, executing a data In response to the operation, the data recovery operation includes: performing one or more sensing operations on the memory cells; and logically combining the results of the sensing operations with the verification data maintained in the data latches, Responding to the corresponding target data status of each of the memory units. The method of claim 1, wherein the non-volatile memory system is a component of a memory system, the memory system includes a controller and the non-volatile memory, and after the performing a programming operation, the target data is not maintained. In the controller. The method of claim 2, wherein the target data is not maintained in the memory in a manner independent of the verification data. The method of claim 1, wherein the memory cells are complex state memory cells. The method of claim 4, wherein the memory stores the plurality of status data in an upper page, lower page format, and the programming operation writes the upper page target data to the memory units. The method of claim 5, wherein the lower page material has been written to the memory cells before the programming operation writes the upper page target data to the memory cells. The method of claim 6, wherein the programming operation further comprises reading the lower page data into the data latches before writing the upper page target data to the memory cells. The method of claim 5, wherein the data reply operation replies to the lower page data and the upper page target data. The method of claim 4, wherein the method further comprises: simultaneously programming the lower page material and the upper page target data to another location in the memory after the data recovery operation. A method for use in a memory system having a non-volatile array, the non-volatile array comprising a plurality of complex state memory cells storing data as separate logical pages, the method comprising: placing a first logical page data Writing to one of the first physical pages of the array, wherein writing the first logical page comprises writing the memory unit as an intermediate data state; the second logical page to be used for each of the first physical page The data of the data is stored in a corresponding first data latch; and a programming operation is performed to write the second logical page data to the first physical page, wherein programming the second logical page includes the intermediate data state Further programming the first logical page data to write a second logical page data, the programming operation comprising: reading the first logical page material from the first physical page, each unit in the first physical page The first page of data is stored in a corresponding second data latch; the first physical page is programmed according to the contents of the first and second data latches; and the first data latch is verified The second data latch contents are copied after the data in the device and before starting to verify the data in the second data latches. The method of claim 10, further comprising: determining whether the operation for writing the second logical page data to the first physical page has failed, and failing to perform the corresponding first and the corresponding second data lock Storing the content of the memory to successfully verify one or more of the memory cells; and in response to determining that the operation to write the second logical page data to the first physical page has failed, the The copy content of the two data latches is written to a second physical page. A method for use in a memory system having a non-volatile array, the non-volatile array comprising a plurality of complex state memory cells storing data as separate logical pages, the method comprising: placing a first logical page data Writing to one of the first physical pages of the array, wherein writing to the first logical page comprises writing the memory unit as an intermediate data state; Storing data for the second logical page material of each of the first physical page in a corresponding first data latch; and performing a programming operation to write the second logical page data to the a first physical page, wherein programming the second logical page includes further programming the first logical page material from the intermediate data state, the programming operation for writing a second logical page material comprising: reading from the first physical page Taking the first logical page data, the first page data of each unit in the first physical page is stored in a corresponding second data latch and a corresponding third data latch; and according to the first And the content of the second latch programs the first physical page, and maintains a copy of the first page material of each unit in the first physical page in the corresponding third data latch. The method of claim 12, further comprising: determining whether the operation to write the second logical page data to the first physical page has failed, and not according to the corresponding first and the corresponding second data lock Storing the content of the memory to successfully verify one or more of the memory cells; and in response to determining that the operation to write the second logical page data to the first physical page has failed, the The content of the three data latches is copied to a second physical page. A non-volatile memory comprising: a memory array having a plurality of non-volatile memory cells; programming circuitry selectively connectable to the memory cells for writing respective target data states Into the memory cells; a set of data latches, one or more of which are connectable to each of the memory cells being written in a programming operation to maintain an indication of whether the corresponding memory cell has been successfully written ???a verification data of respective target data states; a sensing circuit selectively connectable to the memory cells; and a logic circuit responsive to an indication of one of the one or more memory cells failing to write operation, The results from the sensing circuit or the one or more read results of the memory cells are combined with the corresponding verification data maintained in the data latches to cause the memory cells to recover The target data status that has been programmed. The memory of claim 14, wherein the non-volatile memory system is a component of a memory system, the memory system includes a controller and the non-volatile memory, and the target data is written to the program by performing a programming operation After the memory unit, the target data status is not maintained in the controller. The memory of claim 15, wherein the target data status is not maintained in the memory independently of the verification data. The memory of claim 14, wherein the memory cells are complex state memory cells. The memory of claim 17, wherein the memory stores the plurality of state data in the memory unit in an upper page and a lower page format, and the target data is an upper page target data. The memory of claim 18, wherein the memory writes the lower page data to the memory device before writing the upper page target data to the memory unit Equal memory unit. The memory of claim 19, wherein the sensing circuit reads the lower page data into the data latches before writing the upper page target data to the memory cells. The memory of claim 18, wherein the logic circuit replies to the lower page data and the upper page target data.