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TWI498977B - Semiconductor package structure and method of manufacturing same - Google Patents

Semiconductor package structure and method of manufacturing same Download PDF

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Publication number
TWI498977B
TWI498977B TW101112704A TW101112704A TWI498977B TW I498977 B TWI498977 B TW I498977B TW 101112704 A TW101112704 A TW 101112704A TW 101112704 A TW101112704 A TW 101112704A TW I498977 B TWI498977 B TW I498977B
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Taiwan
Prior art keywords
substrate
wafer
conductive elements
package structure
film
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TW101112704A
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Chinese (zh)
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TW201342498A (en
Inventor
洪嘉臨
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日月光半導體製造股份有限公司
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Priority to TW101112704A priority Critical patent/TWI498977B/en
Publication of TW201342498A publication Critical patent/TW201342498A/en
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Publication of TWI498977B publication Critical patent/TWI498977B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝結構及其製造方法Semiconductor package structure and method of manufacturing same

本發明係關於一種半導體封裝結構及其製造方法。The present invention relates to a semiconductor package structure and a method of fabricating the same.

習知堆疊式封裝層疊結構(package on package,PoP)包括一下封裝結構及一上封裝結構。習知下封裝結構係利用外露的銲球與上封裝結構電性連接，故須去除部分封膠材料至使銲球外露，以利與上封裝結構接合。目前去除部分封膠材料有兩種方式，第一種是利用切割方式移除部分封膠材料，另一種方式是利用雷射燒融的方式移除部分封膠材料。此二種方式除了在機台的精度要求上是非常高以外，在移除部分封膠材料後，除了會造成殘膠外，也會造成銲球表面的污染，為了要去除以上兩種外來污染，必需要增加一道清除製程，進而使成本上升。A conventional package on package (PoP) includes a package structure and an upper package structure. Conventionally, the package structure is electrically connected to the upper package structure by using exposed solder balls, so that part of the sealant material must be removed to expose the solder balls to facilitate bonding with the upper package structure. At present, there are two ways to remove part of the sealing material. The first one is to remove part of the sealing material by cutting, and the other is to remove part of the sealing material by laser burning. In addition to the high precision of the machine, the two methods will not only cause residual glue, but also cause contamination of the surface of the solder ball. In order to remove the above two kinds of external pollution, It is necessary to add a cleaning process to increase the cost.

本發明提供一種半導體封裝結構之製造方法。首先，提供一基板，該基板具有一第一表面及一第二表面。接著，形成複數個導電元件於該基板之該第一表面。再設置一晶片至該基板之該第一表面，且該晶片係電性連接至該基板。接著，覆蓋一模具於該等導電元件上，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分。接著，形成一封膠材料以包覆該基板之第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面。The present invention provides a method of fabricating a semiconductor package structure. First, a substrate is provided having a first surface and a second surface. Next, a plurality of conductive elements are formed on the first surface of the substrate. A wafer is further disposed to the first surface of the substrate, and the wafer is electrically connected to the substrate. Next, a mold is coated on the conductive members, and an inner surface of the mold has a film that contacts a surface of the wafer, and the film houses portions of the conductive members. Next, a glue material is formed to cover the first surface of the substrate, the wafer and a portion of the conductive elements, and expose the surface of the wafer.

本發明另提供一種半導體封裝結構，包括：一基板、一晶片、複數個導電元件及一封膠材料。該基板具有一第一表面及一第二表面。該晶片設置於該基板之該第一表面，且電性連接至該基板。該等導電元件設置於該基板之該第一表面。該封膠材料係利用一模具進行灌模製程而成，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分，該封膠材料包覆該基板之該第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面。The invention further provides a semiconductor package structure comprising: a substrate, a wafer, a plurality of conductive elements and a glue material. The substrate has a first surface and a second surface. The wafer is disposed on the first surface of the substrate and electrically connected to the substrate. The conductive elements are disposed on the first surface of the substrate. The encapsulating material is formed by a mold filling process, and an inner surface of the mold has a film, the film contacts a surface of the wafer, and the film houses a portion of the conductive member, the sealing material Coating the first surface of the substrate, the wafer and a portion of the conductive elements, and exposing the surface of the wafer.

本發明又提供一種半導體封裝結構，包括：一基板、一晶片、複數個導電元件、一第一封膠材料、一上基板、一上晶片及一第二封膠材料。該基板具有一第一表面及一第二表面。該晶片設置至該基板之該第一表面，且電性連接至該基板。該等導電元件設置於該基板之該第一表面。該第一封膠材料係利用一模具進行灌模製程而成，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分，該第一封膠材料包覆該基板之該第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面。該上基板具有一第一表面及一第二表面，且該第二表面電性連接該等導電元件。該上晶片設置至該上基板之該第一表面，且電性連接至該上基板。該第二封膠材料包覆該上基板之該第一表面及該上晶片。The invention further provides a semiconductor package structure comprising: a substrate, a wafer, a plurality of conductive elements, a first sealing material, an upper substrate, an upper wafer and a second sealing material. The substrate has a first surface and a second surface. The wafer is disposed to the first surface of the substrate and electrically connected to the substrate. The conductive elements are disposed on the first surface of the substrate. The first encapsulating material is formed by a mold filling process, and an inner surface of the mold has a film, the film contacts a surface of the wafer, and the film houses a portion of the conductive elements, the first A glue material covers the first surface of the substrate, the wafer and a portion of the conductive elements, and exposes the surface of the wafer. The upper substrate has a first surface and a second surface, and the second surface is electrically connected to the conductive elements. The upper wafer is disposed to the first surface of the upper substrate and electrically connected to the upper substrate. The second encapsulant covers the first surface of the upper substrate and the upper wafer.

由於利用該薄膜接觸該晶片之該表面，且該薄膜容置該等導電元件之部分，以使部分該等導電元件及該晶片之該表面暴露，故不須習知移除部分封膠材料之步驟，及不須移除殘膠，也不會造成銲球表面的污染。因此可簡化製程、縮短製程時間及降低製造成本，以利於量產。Since the film is contacted with the surface of the wafer, and the film houses portions of the conductive elements to expose portions of the conductive elements and the surface of the wafer, it is not necessary to remove a portion of the sealing material. Steps, and no need to remove residual glue, will not cause contamination of the surface of the solder ball. Therefore, the process can be simplified, the process time can be shortened, and the manufacturing cost can be reduced to facilitate mass production.

參考圖1，顯示本發明半導體封裝結構之一實施例之示意圖。本發明半導體封裝結構10包括：一基板11、複數個導電元件12、一晶片13、一第一封膠材料14、一上基板15、一上晶片16及一第二封膠材料17。在本實施例中，本發明半導體封裝結構10係為堆疊式封裝層疊結構(package on package,PoP)。Referring to Figure 1, a schematic diagram of one embodiment of a semiconductor package structure of the present invention is shown. The semiconductor package structure 10 of the present invention comprises a substrate 11, a plurality of conductive elements 12, a wafer 13, a first sealing material 14, an upper substrate 15, an upper wafer 16, and a second sealing material 17. In the present embodiment, the semiconductor package structure 10 of the present invention is a package on package (PoP).

該基板11具有一第一表面111及一第二表面112，該第二表面112相對於該第一表面111。該等導電元件12設置於該基板11之該第一表面111。該晶片13設置至該基板11之該第一表面111，且電性連接至該基板11。在本實施例中，利用複數個凸塊131，設置於該基板11及該晶片13間，電性連接該基板11及該晶片13；且利用一底膠132，設置於該基板11及該晶片13間，包覆該等凸塊131。The substrate 11 has a first surface 111 and a second surface 112 opposite to the first surface 111. The conductive elements 12 are disposed on the first surface 111 of the substrate 11. The wafer 13 is disposed to the first surface 111 of the substrate 11 and electrically connected to the substrate 11. In this embodiment, a plurality of bumps 131 are disposed between the substrate 11 and the wafer 13 to electrically connect the substrate 11 and the wafer 13; and a primer 132 is disposed on the substrate 11 and the wafer. 13 covers the bumps 131.

該等導電元件12設置於該晶片13周圍，且該等導電元件12之一頂點相對於該基板之該第一表面的高度大於該晶片13之一表面133相對於該基板之該第一表面的高度。該第一封膠材料14包覆該基板11之該第一表面111、該晶片13及部分該等導電元件12，且暴露該晶片13之該表面133。The conductive elements 12 are disposed around the wafer 13 , and a height of one of the vertices of the conductive elements 12 relative to the first surface of the substrate is greater than a surface 133 of the wafer 13 relative to the first surface of the substrate height. The first encapsulant 14 covers the first surface 111 of the substrate 11, the wafer 13 and a portion of the conductive elements 12, and exposes the surface 133 of the wafer 13.

該上基板15具有一第一表面151及一第二表面152，且該第二表面152電性連接該等導電元件12。該上晶片16設置至該上基板15之該第一表面151，且電性連接至該上基板15。該第二封膠材料17包覆該上基板15之該第一表面151及該上晶片16。The upper substrate 15 has a first surface 151 and a second surface 152 , and the second surface 152 is electrically connected to the conductive elements 12 . The upper wafer 16 is disposed to the first surface 151 of the upper substrate 15 and electrically connected to the upper substrate 15 . The second encapsulant 17 covers the first surface 151 of the upper substrate 15 and the upper wafer 16 .

參考圖2至圖8，顯示本發明半導體封裝結構之製造方法之一實施例之示意圖。參考圖2，提供一基板11，該基板11具有一第一表面111及一第二表面112。再形成複數個導電元件12於該基板11之該第一表面111。在一實施例中，該等導電元件12可為銲球。Referring to Figures 2 through 8, there is shown a schematic diagram of one embodiment of a method of fabricating a semiconductor package structure of the present invention. Referring to FIG. 2, a substrate 11 having a first surface 111 and a second surface 112 is provided. A plurality of conductive elements 12 are formed on the first surface 111 of the substrate 11. In an embodiment, the electrically conductive elements 12 can be solder balls.

參考圖3，設置一晶片13至該基板11之該第一表面111，且該晶片13係電性連接至該基板。在本實施例中，利用複數個凸塊131，設置於該基板11及該晶片13間，電性連接該基板11及該晶片13。參考圖4，本發明之該製造方法另包括形成一底膠132於該基板11及該晶片13間，且包覆該等凸塊131之步驟。Referring to FIG. 3, a wafer 13 is disposed to the first surface 111 of the substrate 11, and the wafer 13 is electrically connected to the substrate. In this embodiment, a plurality of bumps 131 are disposed between the substrate 11 and the wafer 13 to electrically connect the substrate 11 and the wafer 13. Referring to FIG. 4, the manufacturing method of the present invention further includes the steps of forming a primer 132 between the substrate 11 and the wafer 13 and covering the bumps 131.

參考圖5，覆蓋一模具21於該基板11之該第一表面111上，該模具21之一內表面具有一薄膜22，該薄膜22接觸該晶片13之一表面133，且該薄膜22容置該等導電元件12之部分，亦即，該薄膜22覆蓋至該等導電元件12上時，受該等導電元件12擠壓而陷入，以容置該等導電元件12的部分上端。Referring to FIG. 5, a mold 21 is covered on the first surface 111 of the substrate 11. One inner surface of the mold 21 has a film 22 contacting the surface 133 of the wafer 13, and the film 22 is accommodated. Portions of the conductive elements 12, i.e., when the film 22 is overlying the conductive elements 12, are squeezed by the conductive elements 12 to receive portions of the upper ends of the conductive elements 12.

參考圖6，注入第一封膠材料14於該模具21內，以形成第一封膠材料14包覆該基板11之第一表面111、該晶片13及部分該等導電元件12。且因該薄膜22接觸該晶片13之該表面133，第一封膠材料14未包覆該晶片13之該表面133。再移除該模具21及該薄膜22，而該晶片13之該表面133暴露於該第一封膠材料14之外，且該晶片13之該表面133大致與該第一封膠材料14之一上表面齊平，以製造得本發明之一半導體封裝結構30，如圖7所示。在本實施例中，顯露之部分該等導電元件12之高度係為該等導電元件12整體高度之20%-70%。亦即，該封膠材料包覆該等導電元件整體高度之30%-80%。Referring to FIG. 6, a first encapsulant 14 is injected into the mold 21 to form a first encapsulant 14 to cover the first surface 111 of the substrate 11, the wafer 13 and a portion of the conductive elements 12. And because the film 22 contacts the surface 133 of the wafer 13, the first encapsulant 14 does not cover the surface 133 of the wafer 13. The mold 21 and the film 22 are removed, and the surface 133 of the wafer 13 is exposed outside the first sealant material 14, and the surface 133 of the wafer 13 is substantially associated with the first sealant material 14. The upper surface is flush to produce a semiconductor package structure 30 of the present invention, as shown in FIG. In this embodiment, the height of the exposed portions of the conductive elements 12 is between 20% and 70% of the overall height of the conductive elements 12. That is, the encapsulating material covers 30%-80% of the overall height of the conductive members.

本發明之該半導體封裝結構30可為上述本發明半導體封裝結構10(圖1)之下封裝結構，其結構如上所述，在此不再敘述。由於利用該薄膜22接觸該晶片13之該表面133，且該薄膜22容置該等導電元件12之部分，以使部分該等導電元件12及該晶片13之該表面133暴露，故不須習知移除部分封膠材料之步驟，及不須移除殘膠，也不會造成銲球表面的污染。因此可簡化製程、縮短製程時間及降低製造成本，以利於量產。The semiconductor package structure 30 of the present invention may be a package structure under the above-described semiconductor package structure 10 (FIG. 1) of the present invention, the structure of which is as described above, and will not be described herein. Since the film 22 is in contact with the surface 133 of the wafer 13 and the film 22 accommodates portions of the conductive elements 12 to expose portions of the conductive elements 12 and the surface 133 of the wafer 13, it is not necessary to Knowing the steps of removing part of the sealing material, and without removing the residual glue, it will not cause contamination of the surface of the solder ball. Therefore, the process can be simplified, the process time can be shortened, and the manufacturing cost can be reduced to facilitate mass production.

參考圖8，本發明半導體封裝結構之製造方法另包括提供一上封裝結構40之步驟。該上封裝結構40包括一上基板15、一上晶片16、一第二封膠材料17及複數個接合銲墊41。該上基板15具有一第一表面151及一第二表面152，該上晶片16係電性連接該上基板15之該第一表面151，該等接合銲墊41係設置於該上基板15之該第二表面152。Referring to FIG. 8, the method of fabricating the semiconductor package structure of the present invention further includes the step of providing an upper package structure 40. The upper package structure 40 includes an upper substrate 15 , an upper wafer 16 , a second encapsulant 17 , and a plurality of bonding pads 41 . The upper substrate 15 has a first surface 151 and a second surface 152. The upper substrate 16 is electrically connected to the first surface 151 of the upper substrate 15. The bonding pads 41 are disposed on the upper substrate 15. The second surface 152.

再堆疊該上封裝結構40之該等接合銲墊41於該等導電元件12上。接著，進行回銲(Reflow)步驟，使得該等接合銲墊41及該等導電元件12電性連接，以製造得本發明之該半導體封裝結構10，如圖1所示。且另形成複數個第一銲球18於該基板11之該第二表面112，以與外部元件電性連接。The bonding pads 41 of the upper package structure 40 are stacked on the conductive elements 12. Next, a reflow step is performed to electrically connect the bonding pads 41 and the conductive elements 12 to fabricate the semiconductor package structure 10 of the present invention, as shown in FIG. A plurality of first solder balls 18 are further formed on the second surface 112 of the substrate 11 to be electrically connected to external components.

參考圖9，顯示本發明半導體封裝結構之另一實施例之示意圖。與本發明半導體封裝結構10不同之處在於本發明半導體封裝結構50不具有底膠132，而利用第一封膠材料14包覆該等凸塊131。本發明半導體封裝結構50與本發明半導體封裝結構10相同之元件予以相同的標號，且不再敘述。Referring to Figure 9, a schematic diagram of another embodiment of a semiconductor package structure of the present invention is shown. The difference from the semiconductor package structure 10 of the present invention is that the semiconductor package structure 50 of the present invention does not have the primer 132, and the bumps 131 are covered by the first sealant material 14. The same components of the semiconductor package structure 50 of the present invention and the semiconductor package structure 10 of the present invention are given the same reference numerals and will not be described again.

參考圖10，顯示本發明半導體封裝結構之上封裝結構之另一實施例之示意圖。本發明半導體封裝結構之該上封裝結構70包括一上基板15、一上晶片16、一第二封膠材料17、複數個接合銲墊71及複數個第二銲球72。與上述圖8之該上封裝結構40不同之處在於，該等第二銲球72設置於該等接合銲墊71。Referring to Figure 10, there is shown a schematic diagram of another embodiment of a package structure over a semiconductor package structure of the present invention. The upper package structure 70 of the semiconductor package structure of the present invention comprises an upper substrate 15, an upper wafer 16, a second encapsulant 17, a plurality of bonding pads 71 and a plurality of second solder balls 72. The difference from the upper package structure 40 of FIG. 8 is that the second solder balls 72 are disposed on the bonding pads 71.

參考圖11，顯示本發明半導體封裝結構之再一實施例之示意圖。與本發明半導體封裝結構10不同之處在於本發明半導體封裝結構80包括圖10之該上封裝結構70，故該等第二銲球72與該等導電元件12電性連接。本發明半導體封裝結構80與本發明半導體封裝結構10相同之元件予以相同的標號，且不再敘述。Referring to Figure 11, a schematic diagram of still another embodiment of a semiconductor package structure of the present invention is shown. The semiconductor package structure 80 of the present invention includes the upper package structure 70 of FIG. 10, so that the second solder balls 72 are electrically connected to the conductive elements 12. The same components of the semiconductor package structure 80 of the present invention and the semiconductor package structure 10 of the present invention are given the same reference numerals and will not be described again.

參考圖12，顯示本發明半導體封裝結構之又一實施例之示意圖；圖13為圖12之導電元件及凹槽之部分局部放大示意圖。本發明半導體封裝結構60可為上述本發明半導體封裝結構10(圖1)之下封裝結構，與上述本發明半導體封裝結構30不同之處在於本發明半導體封裝結構60具有複數個凹槽61，形成於該等導電元件12之周圍之第一封膠材料14。在本實施例中，可利用雷射燒融的方式移除在該等導電元件12之周圍之第一封膠材料14，以形成該等凹槽61，使得在進行回銲(Reflow)步驟時，使該等接合銲墊41與該等導電元件12順利電性連接。其中，該等凹槽61之外圍寬度A大於該等導電元件12之直徑約20%至50%；且該等凹槽61之深度B約為該等導電元件12之直徑之5%至50%。Referring to FIG. 12, there is shown a schematic view of still another embodiment of the semiconductor package structure of the present invention. FIG. 13 is a partially enlarged schematic view showing a portion of the conductive member and the recess of FIG. The semiconductor package structure 60 of the present invention may be the package structure of the semiconductor package structure 10 (FIG. 1) of the present invention described above, which is different from the above-described semiconductor package structure 30 of the present invention in that the semiconductor package structure 60 of the present invention has a plurality of grooves 61 formed. A first encapsulant 14 around the conductive elements 12. In this embodiment, the first encapsulant 14 around the conductive elements 12 can be removed by laser ablation to form the recesses 61 such that during the Reflow step The bonding pads 41 are electrically connected to the conductive elements 12 in a smooth manner. The peripheral width A of the grooves 61 is greater than about 20% to 50% of the diameter of the conductive elements 12; and the depth B of the grooves 61 is about 5% to 50% of the diameter of the conductive elements 12. .

惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

10．．．本發明半導體封裝結構10. . . Semiconductor package structure of the invention

11．．．基板11. . . Substrate

12．．．導電元件12. . . Conductive component

13．．．晶片13. . . Wafer

14．．．第一封膠材料14. . . First rubber material

15．．．上基板15. . . Upper substrate

16．．．上晶片16. . . Upper wafer

17．．．第二封膠材料17. . . Second sealant

18．．．第一銲球18. . . First solder ball

21．．．模具twenty one. . . Mold

22．．．薄膜twenty two. . . film

30．．．本發明之半導體封裝結構30. . . Semiconductor package structure of the present invention

40．．．上封裝結構40. . . Upper package structure

41．．．接合銲墊41. . . Bonding pad

50．．．本發明半導體封裝結構50. . . Semiconductor package structure of the invention

60．．．本發明半導體封裝結構60. . . Semiconductor package structure of the invention

61．．．凹槽61. . . Groove

70．．．上封裝結構70. . . Upper package structure

71．．．接合銲墊71. . . Bonding pad

72．．．第二銲球72. . . Second solder ball

80．．．本發明之半導體封裝結構80. . . Semiconductor package structure of the present invention

111．．．第一表面111. . . First surface

112．．．第二表面112. . . Second surface

131．．．凸塊131. . . Bump

132．．．底膠132. . . Primer

133．．．表面133. . . surface

151．．．第一表面151. . . First surface

152．．．第二表面152. . . Second surface

圖1顯示本發明半導體封裝結構之一實施例之示意圖；1 shows a schematic diagram of an embodiment of a semiconductor package structure of the present invention;

圖2至圖8顯示本發明半導體封裝結構之製造方法之一實施例之示意圖；2 to 8 are schematic views showing an embodiment of a method of fabricating a semiconductor package structure of the present invention;

圖9顯示本發明半導體封裝結構之另一實施例之示意圖；9 is a schematic view showing another embodiment of a semiconductor package structure of the present invention;

圖10顯示本發明半導體封裝結構之上封裝結構之另一實施例之示意圖；10 is a schematic view showing another embodiment of a package structure over a semiconductor package structure of the present invention;

圖11顯示本發明半導體封裝結構之再一實施例之示意圖；11 is a schematic view showing still another embodiment of the semiconductor package structure of the present invention;

圖12顯示本發明半導體封裝結構之又一實施例之示意圖；及12 is a schematic view showing still another embodiment of the semiconductor package structure of the present invention; and

圖13為圖12之導電元件及凹槽之部分局部放大示意圖。FIG. 13 is a partially enlarged schematic view showing a portion of the conductive member and the recess of FIG.

10．．．本發明半導體封裝結構10. . . Semiconductor package structure of the invention

11．．．基板11. . . Substrate

12．．．導電元件12. . . Conductive component

13．．．晶片13. . . Wafer

14．．．第一封膠材料14. . . First rubber material

15．．．上基板15. . . Upper substrate

16．．．上晶片16. . . Upper wafer

17．．．第二封膠材料17. . . Second sealant

18．．．第一銲球18. . . First solder ball

41．．．接合銲墊41. . . Bonding pad

111．．．第一表面111. . . First surface

112．．．第二表面112. . . Second surface

131．．．凸塊131. . . Bump

132．．．底膠132. . . Primer

133．．．表面133. . . surface

151．．．第一表面151. . . First surface

152．．．第二表面152. . . Second surface

Claims (9)

一種半導體封裝結構之製造方法，包括以下步驟：(a)　提供一基板，該基板具有一第一表面及一第二表面；(b)　形成複數個導電元件於該基板之該第一表面；(c)　設置一晶片至該基板之該第一表面，且該晶片係電性連接至該基板；(d)　覆蓋一模具於該基板上，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分；及(e)　形成一封膠材料以包覆該基板之該第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面。A method of fabricating a semiconductor package structure, comprising the steps of: (a) providing a substrate having a first surface and a second surface; (b) forming a plurality of conductive elements on the first surface of the substrate; c) disposing a wafer to the first surface of the substrate, and the wafer is electrically connected to the substrate; (d) covering a mold on the substrate, an inner surface of the mold has a film, and the film contacts the a surface of one of the wafers, the film receiving portions of the conductive elements; and (e) forming a glue material to cover the first surface of the substrate, the wafer and a portion of the conductive elements, and exposing the wafer The surface. 如請求項1之方法，其中該步驟(e)後另包括於該等導電元件之周圍之封膠材料形成凹槽之步驟。The method of claim 1, wherein the step (e) further comprises the step of forming a recess in the encapsulating material around the conductive elements. 如請求項1之方法，其中該步驟(e)之後更包括：(f)　提供一上封裝結構，該上封裝結構包括一上基板、一上晶片及複數個接合銲墊，該上基板具有一第一表面及一第二表面，該上晶片係電性連接該上基板之該第一表面，該等接合銲墊係設置於該上基板之該第二表面；(g)　堆疊該等接合銲墊於該等導電元件上；及(h)　進行回銲(Reflow)，使得該等接合銲墊及該等導電元件電性連接。The method of claim 1, wherein the step (e) further comprises: (f) providing an upper package structure, the upper package structure comprising an upper substrate, an upper wafer, and a plurality of bonding pads, the upper substrate having a a first surface and a second surface, the upper wafer is electrically connected to the first surface of the upper substrate, the bonding pads are disposed on the second surface of the upper substrate; (g) stacking the bonding electrodes Padded on the conductive elements; and (h) reflowing such that the bond pads and the conductive elements are electrically connected. 一種半導體封裝結構，包括：一基板，具有一第一表面及一第二表面；一晶片，設置於該基板之該第一表面，且電性連接至該基板；複數個導電元件，設置於該基板之該第一表面；及一封膠材料，係利用一模具進行灌模製程而成，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分，該封膠材料包覆該基板之該第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面。A semiconductor package structure comprising: a substrate having a first surface and a second surface; a wafer disposed on the first surface of the substrate and electrically connected to the substrate; a plurality of conductive elements disposed on the substrate The first surface of the substrate; and an adhesive material is formed by a molding process using a mold, an inner surface of the mold has a film, the film contacts a surface of the wafer, and the film accommodates the film a portion of the electrically conductive member, the encapsulant coating the first surface of the substrate, the wafer and a portion of the electrically conductive elements, and exposing the surface of the wafer. 如請求項4之半導體封裝結構，另包括複數個凹槽，形成於該等導電元件之周圍之封膠材料。The semiconductor package structure of claim 4, further comprising a plurality of recesses, a sealant material formed around the conductive elements. 如請求項5之半導體封裝結構，其中該等凹槽之外圍寬度大於該等導電元件之直徑約20%至50%；且該等凹槽之深度約為該等導電元件之直徑之5%至50%。The semiconductor package structure of claim 5, wherein the peripheral width of the grooves is greater than about 20% to 50% of the diameter of the conductive elements; and the depth of the grooves is about 5% of the diameter of the conductive elements to 50%. 如請求項4之半導體封裝結構，該封膠材料包覆該等導電元件整體高度之30%-80%。The semiconductor package structure of claim 4, the encapsulant material covering 30%-80% of the overall height of the conductive elements. 一種堆疊式封裝結構，包括：一基板，具有一第一表面及一第二表面；一晶片，設置至該基板之該第一表面，且電性連接至該基板；複數個導電元件，設置於該基板之該第一表面；一第一封膠材料，係利用一模具進行灌模製程而成，該模具之一內表面具有一薄膜，該薄膜接觸該晶片之一表面，且該薄膜容置該等導電元件之部分，該第一封膠材料包覆該基板之該第一表面、該晶片及部分該等導電元件，且暴露該晶片之該表面；一上基板，具有一第一表面及一第二表面，且該第二表面電性連接該等導電元件；一上晶片，設置至該上基板之該第一表面，且電性連接至該上基板；及一第二封膠材料，包覆該上基板之該第一表面及該上晶片。A stacked package structure includes: a substrate having a first surface and a second surface; a wafer disposed on the first surface of the substrate and electrically connected to the substrate; and a plurality of conductive elements disposed on the substrate The first surface of the substrate; a first sealing material is formed by a mold filling process, and an inner surface of the mold has a film, the film contacts a surface of the film, and the film is accommodated a portion of the conductive material, the first encapsulant coating the first surface of the substrate, the wafer and a portion of the conductive elements, and exposing the surface of the wafer; an upper substrate having a first surface and a second surface electrically connected to the conductive elements; an upper wafer disposed to the first surface of the upper substrate and electrically connected to the upper substrate; and a second encapsulant, Coating the first surface of the upper substrate and the upper wafer. 如請求項8之堆疊式封裝結構，另包括複數個凹槽，形成於該等導電元件之周圍之封膠材料。The stacked package structure of claim 8, further comprising a plurality of grooves, a sealant material formed around the conductive elements.
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Publication number Priority date Publication date Assignee Title
TW200828458A (en) * 2006-12-25 2008-07-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof and stack structure
TW201118963A (en) * 2009-09-15 2011-06-01 Stats Chippac Ltd Integrated circuit packaging system with package-on-package and method of manufacture thereof
TW201142956A (en) * 2010-05-25 2011-12-01 Powertech Technology Inc Array molding method for avoiding air trap and mold utilized in the method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200828458A (en) * 2006-12-25 2008-07-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof and stack structure
TW201118963A (en) * 2009-09-15 2011-06-01 Stats Chippac Ltd Integrated circuit packaging system with package-on-package and method of manufacture thereof
TW201142956A (en) * 2010-05-25 2011-12-01 Powertech Technology Inc Array molding method for avoiding air trap and mold utilized in the method

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