TWI496247B - A fabrication method for buried bit-line formation - Google Patents

Description

Buried bit line manufacturing method

The invention relates to a semiconductor manufacturing method, in particular to a method for manufacturing a buried bit line.

The continuous improvement of semiconductor process technology has greatly reduced the size of electronic components on the one hand, and greatly reduced the manufacturing cost of electronic components on the other hand. The semiconductor process technology used in the past years is limited to the formation of planar semiconductor structures by etching, ion cloth values, wiring, etc. on the substrate, and the minimum wafer size can reach 6F2. However, at present, such technologies tend to be flattened with the miniaturization of the feature size, and the area occupied by the semiconductor on the wafer cannot be significantly reduced. Thus, vertical (or three-dimensional) semiconductor process technology is gradually evolving, which reduces the area occupied by the transistor on the wafer surface by vertically growing the semiconductor on the wafer, and further The chip size is reduced to 4F2.

For example, "SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME" and "SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME" of US Patent Publication No. 20120007171, respectively, disclose A method and a structure for manufacturing a vertical transistor and a buried bit line, which can be fabricated by ion implantation or direct etching after the bit line is fabricated. An oxide layer is formed to form the buried bit line, and then a transistor or dynamic random access memory process is performed.

Among them, no matter which kind of embedded bit line is made, it is necessary to form a trench and a column structure before the subsequent process can be performed. Since the development of vertical transistor technology is becoming more and more mature, the aspect ratio of the trench affects the cell size and the number of transistors that can be accommodated per unit area, and the aspect ratio is getting larger and larger. Under the condition, the column body is easy to bend or break during the process, and the overall process yield is lowered. Especially in the process technology of 40 nm or less, because the columnar body is too large in aspect ratio, there is a problem that it may be bent or even collapsed, and it is necessary to solve it.

The main object of the present invention is to solve the problem that the columnar body is easily bent or collapsed because the aspect ratio is too large.

In order to achieve the above object, the present invention provides a method for fabricating a buried bit line, comprising the steps of: S1: defining a plurality of parallelly disposed cover regions and a plurality of first etch regions on a surface of a substrate, each first The etched region is formed between any of the mask regions, wherein the width of the mask region is greater than the width of the first etch region; S2: etching the substrate at the first etch region to form a plurality of first etches a first trench of the region and a plurality of first pillars corresponding to the covered region; S3: fabricating a plurality of first conductive ions on both sidewalls of the first trench Planting, respectively, forming a single line on both sides of the first column; S4: filling a filler in the first trench; S5: forming a second on each of the first columns Etching the region, and the plurality of second etch regions are not adjacent to the fillers, and the plurality of second etch regions are parallel to the plurality of first etch regions; and S6: etching the plurality of second etch regions to form a plurality of second regions The trench and the plurality of second pillars, and the second pillars respectively correspond to the bit line to complete the preparation.

Further, a ratio of the width of the covered region to the etched region of 3:1 is a preferred embodiment.

Further, the substrate comprises a semiconductor layer sequentially stacked, a first isolation layer, an etch stop layer and a second isolation layer, and the cover layer is disposed on the surface of the second isolation layer. The material of the first isolation layer and the second isolation layer may be tantalum nitride, and the material of the etch stop layer may be cerium oxide.

Further, the filler is made of cerium oxide.

Further, in step S1, a plurality of photoresist layers are deposited on the surface of the substrate to form a plurality of the mask regions.

Further, in step S5, the method includes the following steps: S5A: etching and removing the second isolation layer, and causing the filler to protrude from the etch stop layer; S5B: along the etch stop layer and the filler Depositing a barrier layer The deposition of the barrier layer may be performed by Atomic Layer Deposition (ALD) or Molecular Layer Deposition (MLD) technology; S5C: performing etching back etching of the barrier layer and the etch stop layer (etch back And forming the second etched region on the surface of the first isolation layer.

Further, after step S6, there is a step S7: performing a plurality of second conductive ions in the second trench corresponding to the position of the bit line, and causing the bit line to include the first conductive The ions and the second conductive ions, wherein the material of the first conductive ions and the second conductive ions may be a Group 5A element.

It can be seen from the above description that, by the present invention, the width of the cover region is greater than the width of the first etched region, and the first trench and the second trench are formed in two stages to form the first The columnar body and the second columnar body thus have the following advantages:

1. Strengthening the stress support strength of the first columnar body and the second columnar body to prevent the columnar body from being bent or collapsed.

Second, the process is easy and simple, and effectively achieves the effect of reducing costs.

Third, it is easy to use in the process of reducing the cell size in the future.

The detailed description and technical contents of the present invention will now be described as follows: Please refer to "FIG. 1A" to "FIG. 1H", and the present invention is a buried type. A method for fabricating a bit line, and the present invention is exemplified by a dynamic random access memory (DRAM). The method for fabricating the buried bit line includes the following steps:

S1: a plurality of cover regions A1 and a plurality of first etch regions A2 arranged in parallel are defined on the surface of a substrate 10. Each of the first etch regions A2 is formed between any two of the cover regions A1. Please refer to FIG. 1A. The width of the cover area A1 is greater than the width of the first etched area A2. In the embodiment, the substrate 10 includes a semiconductor layer 11 and a layer sequentially stacked for the convenience of subsequent processes. An isolation layer 12, an etch stop layer 13 and a second isolation layer 14. The material of the semiconductor layer 11 is 矽, the material of the first isolation layer 12 and the second isolation layer 14 is tantalum nitride, and the material of the etch stop layer 13 is cerium oxide, and in this embodiment, A plurality of photoresist layers 20 disposed in parallel with each other may be deposited on the surface of the substrate 10 to form a plurality of the mask regions A1. Since the use cost of the negative photoresist is low, the overall fabrication can be reduced. The ratio of the width of the covered area A1 to the etched area is 3:1, and the width ratio of the covered area A1 to the first etched area A2 may be adjusted to be 3:2 or 5 according to the requirements of the implementation. :1, etc., adjusted according to actual needs.

S2: etching the substrate 10 located in the first etching region A2, as shown in FIG. 1B, to form a plurality of first trenches 15 corresponding to the first etching regions A2 and a plurality of corresponding covering regions A1. The first columnar body 16 has a width equal to three times that of the first trench 15 due to the difference in width between the cover area A1 and the first etched area A2. With better support and stress tolerance.

S3: performing the implantation of the plurality of first conductive ions 31 on the two sidewalls of the first trench 15, please refer to FIG. 1C to form a single-element line 30 on both sides of the first column 16 respectively. In the present embodiment, the first conductive ions 31 are Group 5A elements such as phosphorus or arsenic.

S4: filling a filler 33 in the first trenches 15, as shown in FIG. 1C, the filler 33 may be made of cerium oxide.

S5: forming a second etched region A3 (shown in FIG. 1F) on the first pillars 16 and making the second etched region A3 not adjacent to the fillers 33, and the first The second etched area A3 is parallel to the first etched area A2. Please refer to FIG. 1D to FIG. 1F. Step S5 includes the following steps:

S5A: etching and removing the second isolation layer 14, as shown in FIG. 1D, so that the filler 33 protrudes from the etch stop layer 13;

S5B: depositing a barrier layer 40 along the etch stop layer 13 and the surface of the filler 33, as shown in FIG. 1E, and in this embodiment, atomic layer deposition (ALD) or molecular layer deposition (MLD) may be utilized. The technique is formed on the surface of the etch stop layer 13 and the filler 33 in a linear Deposition manner. The material of the barrier layer 40 may be the same as the etch stop layer 13 and may be cerium oxide.

S5C: performing an etch back of the barrier layer 40 and the etch stop layer 13, as shown in FIG. 1F, and forming the second etched region A3 on the surface of the first isolation layer 12 due to the blocking The layer 40 and the etch stop layer 13 are all of the same material, and therefore, one etchback is performed. And etching a depth to expose the surface of the first isolation layer 12 to form the second etched region A3. In addition, in order to prevent an adjacent area A4 from being affected by subsequent processes, a masking layer 41 may be disposed in the adjacent area A4 as shown in FIG. 1G.

S6: etching the second etched region A3 to form a plurality of second trenches 17 and a plurality of second pillars 18 disposed between the second trenches 17 as shown in FIG. 1H to make the second pillars The body 18 corresponds to the bit line 30, respectively, to complete the preparation of the buried bit line 30 corresponding to the second column 18, wherein the second is etched due to the setting of the filler 33. The stress support is provided when the region A3 is etched, and the problem of bending or collapse of the second column 18 is avoided.

S7: implanting a plurality of second conductive ions 32 in the second trench 17 corresponding to the position of the bit line 30, as shown in FIG. 2A and FIG. 2B, depositing the second conductive ions 32 first, Then etching is performed again in the second trench 17, so that the bit line 30 includes the first conductive ions 31 and the second conductive ions 32, wherein the second conductive ions 32 can be the same as the first conductive ions The material of 31, or different from the first conductive ion 31, depends on the use. Since the first conductive ions 31 are not necessarily connected to the second trenches 17, if necessary, the second conductive ions 32 need to be additionally performed, so that the bit lines 30 can be separately fabricated by the first conductive ions. The ions 31 and the second conductive ions 32 are in communication with the first trench 15 and the second trench 17 .

After the above steps are completed, a high aspect ratio columnar structure and a buried bit line 30 structure can be obtained for subsequent word line fabrication, grinding, fabrication of electrical contacts, and capacitance. Production, etc. .

In summary, by the method of the present invention, the width of the cover region is greater than the width of the first etched region, and the two trenches are used to form the first trench and the second trench to form the first The columnar body and the second columnar body thus have the following advantages:

1. Forming the second columnar body having a high aspect ratio and providing sufficient stress to support the strength of the second columnar body during the manufacturing process, thereby avoiding the occurrence of the bending or collapse of the second columnar body. This improves the process yield of the second column and the buried bit line, and can be applied in a process technology of less than 40 nm in the future to improve the yield of the product.

Second, the negative photoresist can be used for the etching process, and the use of positive photoresist can be avoided to effectively reduce the cost.

Third, the process is easy and simple, and effectively achieves the effect of reducing costs.

Fourth, the same process can also be used in the production of word lines, and can effectively reduce the feature size of electronic components.

Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10‧‧‧Substrate

11‧‧‧Semiconductor layer

12‧‧‧First isolation layer

13‧‧‧etch stop layer

14‧‧‧Second isolation

15‧‧‧First ditches

16‧‧‧First columnar body

17‧‧‧Second ditches

18‧‧‧Second columnar body

A1‧‧‧ Covered area

A2‧‧‧First etched area

A3‧‧‧Second etched area

A4‧‧‧ adjacent areas

20‧‧‧ photoresist layer

30‧‧‧ bit line

31‧‧‧First Conductive Ions

32‧‧‧Second conductive ion

33‧‧‧Filling

40‧‧‧Block

41‧‧‧ Covering layer

1A-1H are schematic diagrams showing a process of a preferred embodiment of the present invention.

2A-2B are schematic diagrams showing a process of another preferred embodiment of the present invention.

10‧‧‧Substrate

11‧‧‧Semiconductor layer

12‧‧‧First isolation layer

13‧‧‧etch stop layer

14‧‧‧Second isolation

A1‧‧‧ Covered area

A2‧‧‧First etched area

20‧‧‧ photoresist layer

Claims (10)

A method for fabricating a buried bit line includes the following steps: S1: defining a plurality of cover regions disposed in parallel on a surface of a substrate, and a plurality of first etch regions, each of the first etch regions being formed on the second cover Between the regions, wherein the width of the cover region is greater than the width of the first etch region; S2: etching the substrate located in the first etch region to form a plurality of first trenches corresponding to the first etch regions and a plurality of pairs The first columnar body of the region should be covered; S3: implanting a plurality of first conductive ions on the two sidewalls of the first trench, and forming a single-element line on both sides of the first column; S4 Filling a filler into the first trenches; S5: forming a second etched region on the first pillars, and making the plurality of etched regions not adjacent to the fillers, and The plurality of second etch regions are parallel to the plurality of first etch regions; and S6: etching the plurality of second etch regions to form a plurality of second trenches and a plurality of second pillars, and wherein the second pillars respectively correspond to The bit line The method for fabricating a buried bit line according to claim 1, wherein a ratio of a width of the covered region to the etched region is 3:1. The method for fabricating a buried bit line according to claim 1, wherein the substrate comprises a semiconductor layer, a first isolation layer, an etch stop layer and a second isolation layer which are sequentially stacked. The method for fabricating a buried bit line according to claim 3, wherein the material of the semiconductor layer is germanium, and the material of the first isolation layer and the second isolation layer is tantalum nitride, and the etching stops. The material of the layer is cerium oxide. The method for fabricating a buried bit line according to claim 1, wherein the filler is made of cerium oxide. The method for fabricating a buried bit line according to claim 1, wherein in step S1, a plurality of photoresist layers are deposited on the surface of the substrate to form a plurality of the mask regions. The manufacturer of the buried bit line as described in claim 3 of the patent application scope The method includes the following steps in the step S5: S5A: etching removes the second isolation layer, and causing the filler to protrude from the etch stop layer; S5B: along the etch stop layer and the filler Depositing a barrier layer on the surface; S5C: performing etchback of the barrier layer and the etch stop layer, and forming the second etched region on the surface of the first isolation layer. The method for fabricating a buried bit line according to claim 7, wherein in step S5B, the deposition of the barrier layer is performed by atomic layer deposition or molecular layer deposition techniques. The method for fabricating a buried bit line according to claim 1, wherein after step S6, there is a step S7: performing a plurality of second conductive positions corresponding to the position of the bit line in the second trench Ion implantation, such that the bit line contains the first conductive ion and the second conductive ion. The method for fabricating a buried bit line according to claim 9, wherein the material of the first conductive ion and the second conductive ion is a Group 5A element.