TWI487037B - The manufacturing method for forming mosfet having the stable threshold voltage - Google Patents

Description

Method for forming a crystal having a stable threshold voltage

The present invention relates to a method of forming a transistor, and more particularly to a method of forming a transistor having a stable threshold voltage.

Complementary Metal Oxide Semiconductor (CMOS) has the advantage of requiring energy only when the transistor needs to be switched on and off, so it is very power-saving and generates less heat. A complementary metal oxide semiconductor fabrication process that traditionally manufactures electronic semiconductor components (or optoelectronic semiconductor components) refers to the ability to fabricate (P-channel MOSFET, PMOS) components and (N-channel MOSFETs, NMOS) on germanium wafers. The device, because of its complementary nature to the PMOS device, is referred to as a complementary metal oxide semiconductor process. The complementary metal oxide semiconductor process can be applied to a process including a semiconductor integrated circuit such as a microprocessor, a microcontroller, a static random access memory (SRAM), and other digital logic circuits.

CMOS

In the current process technology of semiconductor complementary metal oxide semiconductors, the current 32 nanometer (nm) line length grade has been developed, so the process requirements are more and more stringent, and the so-called process is not tolerated. Factors such as stability and defects affect the yield of the product. Therefore, the so-called process instability and defects in the semiconductor complementary metal oxide semiconductor process technology include process defects such as threshold voltage instability and dipole effect, and three threshold voltage instability. The reasons mainly include the following:

1. The Fermi-level pinning effect of the metal/gate oxide interface.

2. The charge effect in the gate oxide.

3. An interface dipole effect is generated between the gate oxide layer and the bismuth (Si) substrate. The interface dipole effect is due to the difference in oxygen density per unit area between the two materials (Areal oxygen). The density difference is caused by the σ value. Oxygen vacancy is left in materials with high σ values when oxygen ions diffuse from materials with higher σ values to materials with lower σ values, while extra oxygen is produced in materials with low σ. The atom, therefore, forms a dipole effect in the interface.

Therefore, in order to produce a more efficient phenomenon, to provide the industry with a better production process, and to be applied to the manufacture of transistor semiconductor components, it is necessary to develop a new method to improve the production yield and reduce the transistor semiconductor components. manufacturing cost.

The invention is a method for forming a transistor having a stable threshold voltage, the transistor having a bipolar sputtering high-k gate dielectric insulating layer, so that the generated electro-crystalline system does not generate a fee Field effect transistor with Fermi-level pinning effect.

The present invention is a method of forming a transistor having a stable threshold voltage, first providing a positive-type germanium semiconductor layer, followed by depositing a first oxide layer on an upper surface of the positive-type germanium semiconductor layer; and performing a first mask and a first mask An etching process to form a field oxide layer on the upper surface of the positive-type germanium semiconductor layer; continuing to deposit a selective gate oxide layer on the upper surface of the positive-type germanium semiconductor layer and the field oxide layer and applying an annealing process; deposition selection a gate metal layer on the upper surface of the selective gate oxide layer; a second mask and a second etching process to form a gate; followed by ion implantation to form a source and a drain; The dioxide layer is on the field oxide layer, the gate, the upper surface of the source and the drain; the third mask and the third etching process are performed to form a contact hole of the gate; the metal layer is continuously formed to form the metal wire. An oxide layer, a gate metal layer, an upper surface of the source and the drain; and finally a fourth mask and a fourth etching process to form a metal wire on the field oxide layer, the gate, the source and the drain Surface.

The present invention proposes a field effect transistor process capable of generating a high stability threshold voltage, thereby reducing the interface dipole effect of the high-k gate dielectrics and the ceria substrate interface.

The present invention can produce a metal gate electrode without a Fermi-level pinning effect, so that the transistor can effectively stabilize the threshold voltage instability.

The above and other objects, features, and advantages of the invention will be apparent from

As shown in Fig. 1A, there is shown a diagram of a method of forming a transistor having a stable threshold voltage, first providing a positive (P-type) germanium semiconductor layer 101.

Subsequently, as shown in FIG. 1B, a ceria (SiO ₂ ) layer (first oxide layer) 101 having a thickness of 5 nm is deposited on the upper surface of the positive-type germanium semiconductor layer 101.

As shown in FIG. 1C, a field oxide (Field Oxide) layer 102 is formed on the upper surface of the positive-type germanium semiconductor layer 101 after the mask and the etching process.

Further, as shown in FIG. 1D, a selective gate oxide layer 103 is deposited on the upper surface of the positive-type germanium semiconductor layer 101 and the field oxide layer 102. The method of depositing includes a physical deposition (PVD) method such as a sputtering method, an evaporation method, and a chemical vapor deposition (CVD) method such as plasma-assisted chemical vapor deposition ( Methods such as PECVD) and organometallic chemical vapor deposition (MOCVD). After the selective gate oxide layer 103 is formed, an annealing process is further performed, and annealing is performed at temperatures of 700 ° C, 800 ° C, and 900 ° C.

As shown in FIG. 2, the selective gate oxide layer 103 shown in FIG. 1D is formed by mixing different metal oxides in a specific ratio, including two. The composition of the group of metal oxides, the first group of elements consists of hafnium (Hf) metal oxides, aluminum (Aluminium, Al) metal oxides, molybdenum (Mo) metal oxides, and zirconium (Zirconium, Zr) is composed of a metal oxide or the like and has a percentage of M1 as a composition, and ranges from 0.1% to 99.9%. The composition of the second group of elements includes Samarium (Sm) metal oxides, Yttrium (Y) metal oxides, Gadolinium (Gd) metal oxides, and Erbium (Er) metal oxides. The composition, and the percentage of M2, which ranges from 99.9% to 0.1%. Therefore, the following percentage mathematical formula is derived, from M1 and M2: M1+M2=100%

Among them, M1 and M2 are metal elements in M1M2Ox, and the calculation method is as follows: If the ratio of M1 is 10%, the ratio of M2 is 90%. The metal mixing method includes double layer sputtering (Dual Sputtering) or vapor deposition by physical vapor deposition (PVD), and using atomic layer deposition (ALD) and metal organic vapor deposition (MOCVD). Chemical vapor deposition (CVD). The manner in which the mixing ratio is adjusted can be adjusted by the raw materials used in the deposition. Further, the proportion of the composition is the atomic composition ratio, that is, the ratio of the number of atoms occupied by M1 and M2 in the compound.

Continued as shown in FIG. 1E, a selective gate metal layer 104 is deposited on the upper surface of the selective gate oxide layer 103. The selective gate metal layer 104 includes a metal nitride gate layer or a multilayer metal gate layer. The metal nitride layer includes tantalum nitride (TaN), titanium nitride (TiN), and hafnium nitride (HfN); and the multilayer metal gate layer includes tantalum nitride/titanium (TaN/Ti). Niobium nitride/titanium (HfN/Ti), and tantalum nitride/niobium (HfN/Ta). The ratio of nitrogen gas is:

Nitrogen (N ₂ ) / Argon (Ar) + Nitrogen = 0% ~ 20%

When the selective gate metal layer 104 is deposited, the metal nitride gate layer is deposited by sputtering, and the process pressure during deposition is controlled at 20 mTorr, and the energy during sputtering. Then control at 150 watts. The argon ratio at the time of sputtering is controlled at 20 sccm, and the nitrogen is adjusted from 0 standard state cc/min (sccm) to 20 standard cc/min. When depositing a plurality of metal gate layers, a layer of pure metal (such as Ti, Ta, or La) is deposited in advance under the metal nitride layer, wherein the pure metal layer is interposed between the metal gates. The layer and the middle of the high dielectric constant oxide layer.

Further, as shown in FIG. 1F, after the mask and the etching process are performed, the gate 500 including the selective gate oxide layer 103 and the gate metal layer 104 is formed.

Further, as shown in FIG. 1G, ion implantation is performed to form a source 105 and a drain 106.

Continued as shown in FIG. 1H, a second oxide layer 107 is deposited on the field oxide layer 102, the gate metal layer 104, the source electrode 105 and the upper surface of the drain 106.

Further, as shown in FIG. 1I, a mask and an etching process are performed to form a contact hole of the gate metal layer 104.

Further, as shown in FIG. 1J, a metal layer is formed to form a metal wire on the field oxide layer, the gate metal layer 104, the source electrode 105 and the upper surface of the drain electrode 106 (not shown). After the mask and the etching process, a metal wire 108 is formed on the field oxide layer 102, the gate metal layer 104, the source electrode 105 and the upper surface of the drain 106.

The invention uses the work function of the metal gate and the metal nitride gate, and the value of the Fermi level pinning effect can be simultaneously obtained by adjusting the work function of the metal by different nitrogen flow rates and double metal structures. Volt, ie, the physical analysis of the present invention, the original metal work function can be compared with the equivalent metal work function extracted by electrical analysis, as follows Expressed by:

Φ _m(initial) -Φ _m(effective) =Fermi-level pinning effect

After the operation, the value of the Fermi level pinning effect can be obtained; therefore, the present invention can have a better effect than the effect of the conventional transistor.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following. Within the scope of the patent application.

101. . . Positive 矽 semiconductor layer

102. . . Field oxide layer

103. . . Selective gate oxide

104. . . Gate metal layer

105. . . Source

106. . . Bungee

107. . . Second oxide layer

108. . . Metal wire

500. . . Gate

1A-1J is a continuous schematic diagram of a method of forming a transistor having a stable threshold voltage.

Fig. 2 is a table showing the composition of the metal oxide of the present invention.

101. . . Positive 矽 semiconductor layer

102. . . Field oxide layer

103. . . Selective gate oxide

104. . . Gate metal layer

105. . . Source

106. . . Bungee

107. . . Second oxide layer

108. . . Metal wire

Claims (12)

A method of forming a transistor having a stable threshold voltage, comprising: providing a positive germanium semiconductor layer; depositing a first oxide layer on an upper surface of the positive germanium semiconductor layer; performing a first mask a first etching process to form a field oxide layer on the upper surface of the positive-type germanium semiconductor layer; depositing a selective gate oxide layer on the upper surface of the positive-type germanium semiconductor layer and the field oxide layer and performing an annealing The process wherein the selective gate oxide layer comprises different complex metal oxides mixed in a specific ratio; depositing a selective gate metal layer on the upper surface of the selective gate oxide layer; a second mask and a second etching process to form a gate, wherein the gate comprises the selective gate oxide layer and the gate metal layer; performing an ion implantation to form a source and a drain And in the positive-type germanium semiconductor layer between the field oxide layer and the selective gate oxide layer; depositing a second oxide layer on the field oxide layer, the gate, the source and the upper surface of the drain Up A third contact hole a reticle and a third etching process to form the gate electrode; Forming a metal layer to form a metal wire on the field oxide layer, the gate metal layer, the source and the upper surface of the drain; and performing a fourth mask and a fourth etching process to form a metal A wire is formed on the field oxide layer, the gate, the source and the upper surface of the drain, thereby forming the transistor having a stable threshold voltage. The method of claim 1, wherein the method of depositing comprises at least a physical deposition method. The method of claim 2, wherein the physical deposition method is selected from the group consisting of sputtering, evaporation, and the like. The method of claim 1, wherein the method of depositing comprises at least a chemical vapor deposition method. The method of claim 4, wherein the chemical vapor deposition method is selected from the group consisting of plasma assisted chemical vapor deposition, organometallic chemical vapor deposition, and the like. The method of claim 1, wherein the annealing temperature of the annealing process is selected from the group consisting of Celsius temperatures of 700 ° C, 800 ° C, and 900 ° C. The method of claim 1, wherein the specific ratio consists of the plurality of metal oxides comprising a first group of metal oxide elements and a second group of metal oxide elements, the first group of metal oxides. The sum of the composition of the elemental elements and the composition of the Group 2 metal oxide elements is 100%. The method of claim 7, wherein the first group of metal oxide element composition comprises a base metal oxide, an aluminum metal oxide, a molybdenum metal oxide, and a zirconium metal oxide, and the like The percentage ranges from 0.1% to 99.9%. The method of claim 7, wherein the Group 2 metal oxide element composition comprises a ruthenium metal oxide, a ruthenium metal oxide, a ruthenium metal oxide, and a ruthenium metal oxide, the percentage of which ranges From 99.9% to 0.1%. The method of claim 1, wherein the selective gate metal layer is selected from the group consisting of a metal nitride gate layer and a plurality of metal gate layer groups. The method of claim 10, wherein the metal nitride layer comprises tantalum nitride, titanium nitride, and tantalum nitride. The method of claim 10, wherein the multilayer metal gate layer comprises tantalum nitride/titanium, tantalum nitride/titanium, and tantalum nitride/ruthenium.