TWI482271B - Image sensor package structure and method with double-layer substrate - Google Patents
Image sensor package structure and method with double-layer substrate Download PDFInfo
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本發明關於一種影像感測器封裝結構，特別係關於一種含有晶粒嵌入之雙層基板影像感測器封裝結構。The present invention relates to an image sensor package structure, and more particularly to a two-layer substrate image sensor package structure including a die embedded.
在半導體元件的領域中，隨著元件尺寸不斷地縮小，元件密度也不斷地提高。在封裝或是內部連線方面的技術需求也必須要提高以符合上述情況。傳統上，在覆晶連接方法(flip-chip attachment method)中，一焊料凸塊陣列形成於上述晶粒的表面。上述焊料凸塊的形成可以藉由使用一焊接複合材料(solder composite material)，經過一焊接點遮罩(solder mask)來製造出所要的焊料凸塊圖案。晶片封裝的功能包含功率傳送(power distribution)、訊號傳送(signal distribution)、散熱(heat dissipation)、保護與支撐等等。當半導體變的更複雜，傳統的封裝技術，例如導線架封裝(lead frame package)、收縮式封裝(flex package)、硬式封裝技術(rigid package technique)，已無法滿足在一個更小的晶片上製造高密度元件之需求。當半導體變的更複雜，傳統的封裝技術，例如導線架封裝(lead frame package)、收縮式封裝(flex package)、硬式封裝技術(rigid package technique)，已無法滿足在一個更小的晶片上製造高密度元件之需求。今日的封裝技術的發展趨勢是朝向球狀矩陣排列(ball grid array，BGA)、覆晶(flip-chip，FC-BGA)、晶片尺寸封裝(chip scale package，CSP)和晶圓級封裝(wafer level chip scale package，WL-CSP)。In the field of semiconductor components, as component sizes continue to shrink, component densities continue to increase. The technical requirements for packaging or internal wiring must also be increased to meet the above conditions. Conventionally, in a flip-chip attachment method, a solder bump array is formed on the surface of the above-described crystal grains. The solder bumps described above can be formed into a desired solder bump pattern by using a solder composite material through a solder mask. The functions of the chip package include power distribution, signal distribution, heat dissipation, protection and support, and the like. As semiconductors become more complex, traditional packaging techniques, such as lead frame packages, flex packages, and rigid package techniques, are no longer sufficient for manufacturing on a smaller wafer. The need for high density components. As semiconductors become more complex, traditional packaging techniques, such as lead frame packages, flex packages, and rigid package techniques, are no longer sufficient for manufacturing on a smaller wafer. The need for high density components. Today's packaging technology trends toward ball grid array (BGA), flip-chip (FC-BGA), chip scale package (CSP) and wafer level packaging (wafer) Level chip scale package, WL-CSP).
現今影像感測器廣泛使用在數位相機、手機、行動電話及其他應用。在製造影像感測器的技術上，特別是CMOS影像感測器，都有很大的進步。舉例而言，對於高解析度及低功率消耗的需求，都促使影像感測器朝最小化及整合方面邁進。Today's image sensors are widely used in digital cameras, cell phones, mobile phones and other applications. In the technology of manufacturing image sensors, especially CMOS image sensors, great progress has been made. For example, the need for high resolution and low power consumption has driven image sensors toward minimization and integration.
在絕大部分的影像感測器常使用一種稱為孔扎式光電二極體(pinned photodiode)及嵌入式光電二極體(buried photodiode)的光電二極體，因為這種光電二極體有較低的雜訊表現。In most image sensors, a photodiode called a pinned photodiode and a buried photodiode is often used because the photodiode has Lower noise performance.
這種光電二極體結構的正極層通常是嵌入該光電二極體的表面或是下方而接近一傳輸閘(transfer gate)，而負極層則是嵌入一矽系基板較深的位置，這種嵌入式層可儲存電荷並遠離表面區域，意即可避免該矽系基板表面的缺陷，而正極層的目的則是在於提供光電二極體有增加的儲存容量及鈍化在光電二極體表面的缺陷。The positive electrode layer of the photodiode structure is usually embedded on the surface of the photodiode or below and close to a transfer gate, and the negative electrode layer is embedded in a deep position of the lanthanide substrate. The embedded layer can store charge and away from the surface area, thereby avoiding defects on the surface of the lanthanide substrate, and the purpose of the positive electrode layer is to provide an increased storage capacity of the photodiode and passivation on the surface of the photodiode. defect.
有許多影像感測器晶片使用覆晶式封固結構，都企圖發展將影像感測器封裝架構簡單化。美國專利6,144,507揭露一種直接將影像感測器晶片封固於印刷電路板(printed circuit board,PCB)上之技術。There are many image sensor wafers that use flip-chip mounting structures in an attempt to simplify the imaging sensor package architecture. U.S. Patent 6,144,507 discloses a technique for directly attaching an image sensor wafer to a printed circuit board (PCB).
一影像感測晶片藉由覆晶式封固結構封固在PCB裡的一個孔洞上，及一透明蓋體也直接附加在該晶片的主動側表面或是黏合在該影像感測晶片封固在該PCB裡孔洞上的相對側。An image sensing wafer is mounted on a hole in the PCB by a flip-chip sealing structure, and a transparent cover is directly attached to the active side surface of the wafer or bonded to the image sensing wafer. The opposite side of the hole in the PCB.
雖然這些方法都省略引線焊接的困難處，然而該PCB為了符合該影像感測晶片及該透明蓋體的尺寸，該PCB的尺寸通常會非常大。Although these methods all omit the difficulty of wire bonding, the PCB is usually very large in size in order to conform to the size of the image sensing wafer and the transparent cover.
美國專利5,786,589揭露一種膠黏標籤片狀物於玻璃基板上及膠黏一影像感測晶片及一導電薄膜至該標籤片。因為標籤片導線的緣故，所以這種設計需要一種特殊的基板附接技術。再者，該導電薄膜可能會干擾該影像感測晶片上之感測電路及需要形成一虛擬配線或是壩體結構來彌補這個問題。No. 5,786,589 discloses an adhesive label sheet on a glass substrate and an image sensing wafer and a conductive film to the label sheet. This design requires a special substrate attachment technique because of the label wire. Moreover, the conductive film may interfere with the sensing circuit on the image sensing wafer and need to form a virtual wiring or dam structure to compensate for this problem.
美國專利6,885,107揭露一種傳統影像感測晶片封裝結構。其採用一種在基板底層具有複數焊錫球及該晶粒外露於基板之BGA封裝。A conventional image sensing chip package structure is disclosed in U.S. Patent No. 6,885,107. It uses a BGA package with a plurality of solder balls on the bottom layer of the substrate and the crystal grains exposed on the substrate.
根據本發明所提供之影像感測器封裝結構之製作具有前述及其他之有利特點及方法。一影像感測晶片利用一覆晶方式安裝在一透明基板之一第一表面上之導電跡線。該影像晶片之主動面則藉由安裝後在該影像晶片之主動面及該基板之該第一表面之周圍空間沈積封膠珠來保護避免污染，因此省略了先前技術另外所需之壩體結構或間隔框架。分散的傳導元件如焊錫球及柱狀物則黏附在該導電跡線末端而形成一陣列圖形，該分散的傳導元件從該第一表面上之該導電跡線橫向外擴至大致上超過該影像感測晶片之一背表面之共用平面。這樣子的結構包含了一種BOC(board-on-chip)的封裝排列。因此，因為該結構的焊錫球高度及該押出模接受結構而讓該基板厚度無法減小而限 制了封裝結構的尺寸的縮小。The fabrication of the image sensor package structure provided in accordance with the present invention has the foregoing and other advantageous features and methods. An image sensing wafer is mounted on a conductive trace on a first surface of a transparent substrate by a flip chip. The active surface of the image wafer is protected from contamination by depositing a sealing bead on the active surface of the image wafer and the first surface of the substrate after installation, thereby omitting the dam structure additionally required by the prior art. Or the spacing frame. Dispersed conductive elements, such as solder balls and pillars, are adhered to the ends of the conductive traces to form an array pattern, the dispersed conductive elements being laterally expanded from the conductive traces on the first surface to substantially exceed the image A common plane of the back surface of one of the wafers is sensed. This structure contains a BOC (board-on-chip) package arrangement. Therefore, the thickness of the substrate cannot be reduced because of the solder ball height of the structure and the extrusion die receiving structure. The size reduction of the package structure is made.
先前技術形成該影像感測晶片封裝具有複雜的過程，以及該封裝結構太高及無法被縮減。此外，這些先前技術僅揭露單晶片之封裝並無說明多晶片的結構。The prior art method of forming the image sensing chip package has a complicated process, and the package structure is too high and cannot be reduced. Moreover, these prior art only disclose that the package of a single wafer does not illustrate the structure of the multi-wafer.
如前所述，本發明關於一種影像感測器封裝結構，特別係關於一種具有雙層基板之影像感測器封裝結構。As described above, the present invention relates to an image sensor package structure, and more particularly to an image sensor package structure having a two-layer substrate.
本發明之目的在於提供一種具有預先形成穿透孔洞及晶粒接受開口的雙層基板之影像感測器封裝結構。It is an object of the present invention to provide an image sensor package structure having a two-layer substrate in which a through hole and a die receiving opening are formed in advance.
本發明之另一目的在於提供一種具有晶粒開口窗的雙層基板之影像感測器封裝結構，用以改善裝置的可靠性及縮減裝置的尺寸。Another object of the present invention is to provide an image sensor package structure of a two-layer substrate having a die opening window for improving the reliability of the device and reducing the size of the device.
本發明之又一目的在於提供一種具有利用銅箔基板及電鍍銅/金或銅/鎳/金合金金屬可增加電性傳導形成之佈線圖位於雙層基板下方及上方之影像感測器封裝結構。Still another object of the present invention is to provide an image sensor package structure having a wiring pattern using a copper foil substrate and an electroplated copper/gold or copper/nickel/gold alloy metal to increase electrical conduction formation under and above the double layer substrate. .
該具有雙層基板之影像感測器封裝結構包含一具有晶粒接受開口之第一基板及複數第一穿透孔洞，其穿透該第一基板；一第二基板，其形成於該第一基板之上，其中該第一基板具有一第一佈線圖及一第二佈線圖，其形成於該第一基板之下方及上方表面，而該第二基板具有一第三佈線圖及一第四佈線圖，其形成於該第二基板之下方及上方表面，部分的第二佈線圖與部分的第三佈線圖耦合；一影像晶粒其包含一導電墊及一接收感測陣列，其中該晶粒接受開口及該感測陣列窗暴露於該晶粒開口窗及一穿透孔洞 導電材料，用以填充於該複數第二穿透孔洞，其中該複數第二穿透孔洞中的部分孔洞與該影像晶粒之導電墊耦合。The image sensor package structure having a two-layer substrate includes a first substrate having a die receiving opening and a plurality of first through holes penetrating the first substrate; a second substrate formed on the first On the substrate, the first substrate has a first wiring pattern and a second wiring pattern formed on the lower surface and the upper surface of the first substrate, and the second substrate has a third wiring pattern and a fourth a wiring pattern formed on the lower surface and the upper surface of the second substrate, a portion of the second wiring pattern coupled to a portion of the third wiring pattern; an image die comprising a conductive pad and a receiving sensing array, wherein the crystal a particle receiving opening and the sensing array window are exposed to the die opening window and a through hole And a conductive material for filling the plurality of second penetration holes, wherein a part of the holes of the plurality of second penetration holes are coupled to the conductive pads of the image die.
一光學玻璃基板，其形成於該第二基板及該晶粒開口窗之上。一透鏡固定架包含一透鏡，其形成於該光學玻璃基板之上，及其中該透鏡與該影像感測晶粒對齊。一紅外線濾波器，其形成於該透鏡固定架之內。一被動式晶粒及/或一主動式晶粒，其形成於該第二基板之上，其中該主動式晶粒包含：晶片尺寸封裝、圓級晶片尺寸封裝、球狀矩陣排列及覆晶晶粒。另外，該複數第一穿透孔洞之至少一側壁包含傳導金屬。該穿透孔洞導電材料，包含金屬或合金，如焊錫及異向性導電膜。An optical glass substrate is formed on the second substrate and the die opening window. A lens holder includes a lens formed on the optical glass substrate, and wherein the lens is aligned with the image sensing die. An infrared filter is formed within the lens holder. a passive die and/or an active die formed on the second substrate, wherein the active die comprises: a wafer size package, a circular wafer size package, a spherical matrix arrangement, and a flip chip . In addition, at least one sidewall of the plurality of first penetration holes comprises a conductive metal. The through hole conductive material comprises a metal or an alloy such as a solder and an anisotropic conductive film.
一含有一透鏡之透鏡固定架，其形成於該第二基板之上，其中該透鏡與該影像感測晶粒對齊。一紅外線濾波器，其形成於該透鏡固定架之內。一被動式晶粒，其形成於該第二基板之上。一主動式晶粒，其形成於該第二基板之上。A lens holder including a lens is formed on the second substrate, wherein the lens is aligned with the image sensing die. An infrared filter is formed within the lens holder. A passive die formed on the second substrate. An active die formed on the second substrate.
該主動式晶粒包含：晶片尺寸封裝、圓級晶片尺寸封裝、球狀矩陣排列及覆晶晶粒。該複數第一穿透孔洞之至少一側壁包含一傳導金屬。該穿透孔洞導電材料，包含金屬或合金或異方性導電膜。該第一基板及該第二基板材料，包含FR5或FR4。另外，該第一基板及該第二基板材料，包含雙馬來醯亞胺三氮雜苯樹脂、矽系、印刷電路板材料、玻璃、陶瓷、金屬或合金。The active die includes: a wafer size package, a circular wafer size package, a spherical matrix arrangement, and a flip chip. At least one sidewall of the plurality of first through holes includes a conductive metal. The through hole conductive material comprises a metal or an alloy or an anisotropic conductive film. The first substrate and the second substrate material comprise FR5 or FR4. Further, the first substrate and the second substrate material comprise a bismaleimide triazine resin, a lanthanide, a printed circuit board material, glass, ceramic, metal or alloy.
copper clad laminated)係亦如金屬晶種層以層疊形 成，而該銅/鎳合金及銅/鎳/金合金係以電鍍形成；利用電鍍製程所成形之佈線層有足夠的厚度及較佳的機械特性，能在溫度循環和機械彎曲中承受熱膨脹係數不匹配之問題。該傳導墊可為金或銅/金或鋁或及其組合。Copper clad laminated) is also like a metal seed layer The copper/nickel alloy and the copper/nickel/gold alloy are formed by electroplating; the wiring layer formed by the electroplating process has sufficient thickness and better mechanical properties to withstand thermal expansion coefficients in temperature cycling and mechanical bending. Mismatched issue. The conductive pad can be gold or copper/gold or aluminum or a combination thereof.
在本發明之一實施例中，如圖一所示，一第一基板100包含一傳導佈線圖101形成於該第一基板之上表面，及一傳導佈線圖102形成於該第一基板100之下表面。該佈線圖101及該佈線圖102包含以銅箔基板及電鍍形成之電鍍銅或銅/鎳/金合金金屬。該晶粒120具有一傳導(鋁或金)墊121(輸入輸出墊)形成於其中。該晶粒120暴露於該第一基板100之晶粒接受開口105中。一第二基板104其形成於該第一基板100上，該第二基板104包含一晶粒開口窗107、一第三佈線圖106位於該第二基板104上表面及一第四佈線圖106a位於該第二基板104下表面。In one embodiment of the present invention, as shown in FIG. 1, a first substrate 100 includes a conductive wiring pattern 101 formed on an upper surface of the first substrate, and a conductive wiring pattern 102 is formed on the first substrate 100. lower surface. The wiring pattern 101 and the wiring pattern 102 include electroplated copper or copper/nickel/gold alloy metal formed by a copper foil substrate and plating. The die 120 has a conductive (aluminum or gold) pad 121 (input and output pad) formed therein. The die 120 is exposed to the die receiving opening 105 of the first substrate 100. A second substrate 104 is formed on the first substrate 100. The second substrate 104 includes a die opening window 107. A third wiring pattern 106 is located on the upper surface of the second substrate 104 and a fourth wiring pattern 106a is located. The lower surface of the second substrate 104.
本發明形成影像感測器封裝之製程，如圖一所示，包含準備一第一基板100及一第二基板104(較佳為FR4/FR5/BT系列材料之有機基板)及該第一基板具有佈線電路102及101，分別形成於該第一基板100之上表面及下表面。該佈線圖106a及106則分別形成於該第二基板104之上表面及下表面。該基板中之101、102、106a及106層可以電鍍形成之電鍍銅或銅/鎳/金合金金屬形成。該連結傳導穿透孔103可以穿透該第一基板100形成。如圖一及圖二所示，該第一基板100具有一預先形成之晶粒接受開口105及該晶粒開口窗107亦為預先形成，該晶粒接受 開口105藉由雷射切割或機械沖壓(多骰沖床)，其開口尺寸大於該晶粒，其開口每邊比晶粒之大小增加約100um~200um。如圖二所示，該第二基板104黏附(附著性膠膜)在該第一基板100。The process of forming an image sensor package of the present invention, as shown in FIG. 1 , includes preparing a first substrate 100 and a second substrate 104 (preferably an organic substrate of FR4/FR5/BT series materials) and the first substrate. The wiring circuits 102 and 101 are formed on the upper surface and the lower surface of the first substrate 100, respectively. The wiring patterns 106a and 106 are formed on the upper surface and the lower surface of the second substrate 104, respectively. The layers 101, 102, 106a and 106 in the substrate may be formed by electroplating of electroplated copper or copper/nickel/gold alloy metal. The connection conductive through hole 103 may be formed through the first substrate 100. As shown in FIG. 1 and FIG. 2, the first substrate 100 has a pre-formed die receiving opening 105 and the die opening window 107 is also formed in advance. The opening 105 is formed by laser cutting or mechanical stamping (multiple punching), and the opening size thereof is larger than the crystal grain, and the opening of each side is increased by about 100 um to 200 um than the size of the crystal grain. As shown in FIG. 2, the second substrate 104 is adhered (adhesive film) to the first substrate 100.
下一步驟，如圖三所示，則是將該影像感測器120設置於該晶粒接受開口105及該藉由晶粒/基板校準工具將感測區域122外露於該第二基板104上之晶粒開口窗107。而下一步驟，則是形成該導電材料162(如焊接劑)於該第二基板104之該傳導穿透孔159、159a。該填充步驟可形成於該第二基板104黏附於該第一基板100之前。IR迴焊製程則是於該焊接劑流向穿透孔床新填充焊接劑後執行，及在穿透孔159a中連接至該傳導墊121。In the next step, as shown in FIG. 3 , the image sensor 120 is disposed on the die receiving opening 105 and the sensing region 122 is exposed on the second substrate 104 by the die/substrate calibration tool. The die opening window 107. The next step is to form the conductive material 162 (such as a solder) on the conductive through holes 159, 159a of the second substrate 104. The filling step may be formed before the second substrate 104 is adhered to the first substrate 100. The IR reflow process is performed after the flux flows to the penetrating bed to newly fill the solder, and is connected to the conductive pad 121 in the through hole 159a.
當焊接劑162重新回填至該該穿透孔159、159a，該玻璃基板160隨後藉由該黏附材料164形成於該第二基板104之上當做另外一可選擇之製程。When the soldering agent 162 is backfilled to the through holes 159, 159a, the glass substrate 160 is then formed on the second substrate 104 by the adhesive material 164 as an alternative process.
該主動或被動裝置180亦黏附(表面貼裝，SMT)在如圖五所示層上，接著如圖六所示，具有一透鏡184之透鏡固定架182，其黏附於該第二基板104之上並與該影像感測晶粒120對齊。該第一基板100可藉由焊接劑或異向性導電膜(ACF)黏附在軟性電路板186上。該光學透鏡高度則視其光學表現及物理參數而定。如圖七所示，一紅外線濾波器188可形成於該透鏡固定架182之內(該紅外線濾波器188可以該玻璃基板160置換)。The active or passive device 180 is also adhered (surface mount, SMT) on the layer shown in FIG. 5, and then, as shown in FIG. 6, a lens holder 182 having a lens 184 adhered to the second substrate 104. And aligned with the image sensing die 120. The first substrate 100 may be adhered to the flexible circuit board 186 by a solder or an anisotropic conductive film (ACF). The height of the optical lens depends on its optical performance and physical parameters. As shown in FIG. 7, an infrared filter 188 can be formed within the lens holder 182 (the infrared filter 188 can be replaced by the glass substrate 160).
該被動元件180可為電容或電阻，而另以晶圓級封裝 (wafer level chip scale package，WL-CSP)、晶片尺寸封裝(chip scale package，CSP)、覆晶(flip-chip，FC-BGA)和球狀矩陣排列(ball grid array，BGA)之晶粒亦可安裝在該第二基板104之頂端電路上。因此建構至少兩晶片可一起嵌入裡面，及具有傳導穿透孔用以作為電子訊號內部連結。所有的傳導穿透孔159、159a及103可以CNC或雷射鑽孔形成。The passive component 180 can be a capacitor or a resistor, and is additionally packaged in a wafer level. (wafer level chip scale package, WL-CSP), chip scale package (CSP), flip-chip (FC-BGA), and ball grid array (BGA) It can be mounted on the top circuit of the second substrate 104. Therefore, at least two wafers can be embedded together and have conductive through holes for internal connection of electronic signals. All of the conductive through holes 159, 159a and 103 can be formed by CNC or laser drilling.
本系統影像感測晶片封裝結構及製程皆比欠缺揭露多晶片及雙層結構的傳統影像感測晶片封裝來的簡單。而本系統影像感測晶片封裝結構厚度可以容易控制，並可消除在製程中會造成晶片移位的問題。並可以省略射出成型工具；也不須導入化學機械研磨製程及本製程也不會產生翹曲。該基板為一具有預先形成晶粒開口窗、內部連結穿透孔之預先準備基板；該晶粒開口窗尺寸等於該晶粒尺寸每邊增加大約100um至200um；藉由填充彈性核心膠體，上述開口可以作為應力緩衝釋放區域，吸收由矽晶粒與基板(耐高溫玻璃纖維板/雙馬來醯亞胺三氮雜苯樹脂)之間熱膨脹係數不匹配，所造成之熱應力。此外，也可以在晶粒與基板側壁間隙之間填充彈性介電材料，以吸收由熱膨脹係數不匹配所造成之機械彎曲及/或熱應力。由於同時在上表面與底表面施加上述簡單增層，故可增加封裝生產率(減少製造週期)。該晶粒及基板(即該第一基板及該第二基板)黏合在一起。上述封裝與主機板(母板)級封裝之可靠度也比以前更好。特別對主機板級封裝溫度循環測試而言，由 於基板與印刷電路板(母板)之熱膨脹係數一致，故不會有任何施加於焊錫凸塊/球之熱機械應力；對主機板級封裝機械彎曲測試而言，支撐機械強度之基板底側可以吸收基板上側之晶粒區域與邊界區域之應力。The image sensing chip package structure and process of the system are simpler than the conventional image sensing chip package exposing the multi-wafer and double-layer structure. The thickness of the image sensing chip package structure of the system can be easily controlled, and the problem of wafer shift in the process can be eliminated. The injection molding tool can be omitted; there is no need to introduce a chemical mechanical polishing process and the process does not cause warpage. The substrate is a pre-prepared substrate having a pre-formed grain opening window and an inner connecting through hole; the die opening window has a size equal to about 100 um to 200 um per side of the grain size; and the opening is filled by filling the elastic core colloid It can be used as a stress buffer release region to absorb the thermal stress caused by the mismatch between the thermal expansion coefficients between the germanium grains and the substrate (high temperature resistant glass fiber board / bismaleimide triazabenzene resin). In addition, an elastic dielectric material may be filled between the die and the sidewall gap of the substrate to absorb mechanical bending and/or thermal stress caused by a mismatch in thermal expansion coefficients. Since the above simple build-up layer is applied to both the upper surface and the bottom surface, the package productivity can be increased (the manufacturing cycle is reduced). The die and the substrate (ie, the first substrate and the second substrate) are bonded together. The reliability of the above package and motherboard (motherboard) package is also better than before. Especially for the motherboard-level package temperature cycle test, The thermal expansion coefficient of the substrate and the printed circuit board (motherboard) is the same, so there is no thermo-mechanical stress applied to the solder bumps/balls; for the mechanical bending test of the motherboard-level package, the bottom side of the substrate supporting the mechanical strength The stress of the grain region and the boundary region on the upper side of the substrate can be absorbed.
雖然本發明之參考實施例已被加以描述，然而對該領域具有通常知識者應能理解本發明內容不被上述之實施例所限制。再者，在本發明之精神與概念範疇內，可以提出各種變化與修正。本發明由下述專利申請範圍所定義。While the present invention has been described, it should be understood by those of ordinary skill in the art that the present invention is not limited by the embodiments described above. Furthermore, various changes and modifications can be made within the spirit and concept of the invention. The invention is defined by the scope of the following patent application.
100‧‧‧第一基板100‧‧‧First substrate
101‧‧‧第一佈線圖101‧‧‧First wiring diagram
102‧‧‧第二佈線圖102‧‧‧Second wiring diagram
103‧‧‧傳導穿透孔103‧‧‧Transmission through hole
104‧‧‧第二基板104‧‧‧second substrate
105‧‧‧晶粒接受開口105‧‧‧ die acceptance opening
106‧‧‧第三佈線圖106‧‧‧ Third wiring diagram
106a‧‧‧第四佈線圖106a‧‧‧4th wiring diagram
107‧‧‧晶粒開口窗107‧‧‧ grain opening window
120‧‧‧晶粒(晶片)120‧‧‧ die (wafer)
121‧‧‧導電墊121‧‧‧Electrical mat
122‧‧‧感測陣列122‧‧‧Sensor array
159‧‧‧傳導穿透孔159‧‧‧Transmission through hole
159a‧‧‧傳導穿透孔159a‧‧‧Transmission through hole
160‧‧‧光學玻璃元件160‧‧‧Optical glass components
162‧‧‧導電材料162‧‧‧Electrical materials
164‧‧‧黏附材料164‧‧‧Adhesive materials
180‧‧‧主動(被動)元件180‧‧‧Active (passive) components
182‧‧‧透鏡固定架182‧‧‧ lens holder
184‧‧‧光學透鏡184‧‧‧ optical lens
186‧‧‧可撓式印刷電路板186‧‧‧Flexible printed circuit boards
188‧‧‧紅外線濾波器188‧‧‧Infrared filter
圖一根據本發明之實施例，圖示一第一基板、一第二基板及影像感測器連結前之截面圖。1 is a cross-sectional view showing a first substrate, a second substrate, and an image sensor before being joined according to an embodiment of the present invention.
圖二根據本發明之實施例，圖示第一基板與具有晶粒開口之第二基板組合之截面圖。2 is a cross-sectional view showing a combination of a first substrate and a second substrate having a die opening, in accordance with an embodiment of the present invention.
圖三根據本發明之實施例，圖示第一基板接受晶粒之截面圖。Figure 3 is a cross-sectional view showing a first substrate receiving a die according to an embodiment of the present invention.
圖四根據本發明之實施例，圖示形成焊錫球於穿透孔洞之截面圖。Figure 4 is a cross-sectional view showing the formation of a solder ball in a through hole according to an embodiment of the present invention.
圖五根據本發明之實施例，圖示第二基板之附屬玻璃基板之截面圖。Figure 5 is a cross-sectional view showing an attached glass substrate of a second substrate in accordance with an embodiment of the present invention.
圖六根據本發明之實施例，圖示透鏡固定架形成於該第二基板之上之截面圖。Figure 6 is a cross-sectional view showing the lens holder formed on the second substrate in accordance with an embodiment of the present invention.
圖七根據本發明之實施例，圖示另一實施例之截面圖。Figure 7 illustrates a cross-sectional view of another embodiment in accordance with an embodiment of the present invention.
100‧‧‧第一基板100‧‧‧First substrate
101‧‧‧第一佈線圖101‧‧‧First wiring diagram
102‧‧‧第二佈線圖102‧‧‧Second wiring diagram
103‧‧‧傳導穿透孔103‧‧‧Transmission through hole
104‧‧‧第二基板104‧‧‧second substrate
105‧‧‧晶粒接受開口105‧‧‧ die acceptance opening
106‧‧‧第三佈線圖106‧‧‧ Third wiring diagram
106a‧‧‧第四佈線圖106a‧‧‧4th wiring diagram
107‧‧‧晶粒開口窗107‧‧‧ grain opening window
120‧‧‧晶粒(晶片)120‧‧‧ die (wafer)
121‧‧‧導電墊121‧‧‧Electrical mat
122‧‧‧感測陣列122‧‧‧Sensor array
159‧‧‧傳導穿透孔159‧‧‧Transmission through hole
159a‧‧‧傳導穿透孔159a‧‧‧Transmission through hole
Claims (15)
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| Application Number | Priority Date | Filing Date | Title |
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| US13/289,864 US8232633B2 (en) | 2008-09-25 | 2011-11-04 | Image sensor package with dual substrates and the method of the same |
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| TW201320314A TW201320314A (en) | 2013-05-16 |
| TWI482271B true TWI482271B (en) | 2015-04-21 |
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| CN105742253B (en) * | 2014-12-10 | 2018-08-07 | 旭景科技股份有限公司 | Printed circuit board assembly for mounting image sensor |
| CN106033753B (en) * | 2015-03-12 | 2019-07-12 | 恒劲科技股份有限公司 | Packaging module and substrate structure thereof |
| TWI559464B (en) * | 2015-03-12 | 2016-11-21 | 恆勁科技股份有限公司 | Package module and its substrate structure |
| TWI619389B (en) * | 2016-07-13 | 2018-03-21 | 許志行 | Portable electronic device and image capturing module thereof |
| US9860431B1 (en) | 2016-10-11 | 2018-01-02 | Chi-Hsing Hsu | Portable electronic device and image capturing module thereof |
| KR101942740B1 (en) | 2017-10-19 | 2019-01-28 | 삼성전기 주식회사 | Fan-out sensor package and optical-type fingerprint sensor module |
| TWI639880B (en) * | 2017-11-10 | 2018-11-01 | 群光電子股份有限公司 | Lens structure and method for correcting thermal drift |
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| TW200847418A (en) * | 2007-05-30 | 2008-12-01 | Advanced Chip Eng Tech Inc | CMOS image sensor chip scale package with die receiving opening and method of the same |
| TW200947007A (en) * | 2007-12-19 | 2009-11-16 | Heptagon Oy | Optical module for a camera device, baffle substrate, wafer scale package, and manufacturing methods therefor |
| TW201121015A (en) * | 2009-12-02 | 2011-06-16 | Wen-Kun Yang | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
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| TWI460844B (en) * | 2009-04-06 | 2014-11-11 | 金龍國際公司 | Stacked package structure with embedded wafer and germanium via film and manufacturing method thereof |
| CN102045494A (en) * | 2009-10-22 | 2011-05-04 | 国碁电子(中山)有限公司 | Camera module and making method thereof |
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| TW200847418A (en) * | 2007-05-30 | 2008-12-01 | Advanced Chip Eng Tech Inc | CMOS image sensor chip scale package with die receiving opening and method of the same |
| TW200947007A (en) * | 2007-12-19 | 2009-11-16 | Heptagon Oy | Optical module for a camera device, baffle substrate, wafer scale package, and manufacturing methods therefor |
| TW201121015A (en) * | 2009-12-02 | 2011-06-16 | Wen-Kun Yang | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
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