TWI482160B - Programming method for nonvolatile semiconductor memory device - Google Patents

Description

Stylized method for non-volatile semiconductor memory components

The present invention relates to a method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory device.

A semiconductor memory component is a component in which data from which data can be stored and stored can be read. Semiconductor memory components can be classified into volatile memory components and non-volatile memory components. Volatile memory components require a supply of power to persist to preserve data, while non-volatile memory components retain data when the power supply disappears. Therefore, non-volatile memory components are widely used in applications where the power supply may be suddenly disturbed.

The non-volatile memory component comprises an electrically erasable and programmable mable (EEPROM) cell, such as a flash EEPROM cell. Figure 1 shows a vertical cross-sectional view of a flash EEPROM cell 10. Referring to FIG. 1, an N-type source region 13 and an N-type drain region 14 are formed on a P-type substrate 12 or a body region. A P-type channel region is formed between the source region 13 and the drain region 14. A floating gate 16 isolated by an insulating layer 15 is formed over the P-type channel region. A control gate 18 isolated by another insulating layer 17 is formed over the floating gate 16.

Figure 2 shows the threshold voltage range of the flash EEPROM cell 10 during staging and erase operations. Referring to Figure 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7 V) during the staging operation and a lower threshold voltage range (about 1 to 3 V) during the erase operation.

Referring to Figures 1 and 2, during the stylization operation, hot electrons must be injected from the channel region adjacent to the drain region 14 to the floating gate electrode, so that the threshold voltage range of the EEPROM cell increases. Conversely, the hot electrons injected into the floating gate 16 during the staging operation must be removed during the erase operation, so the threshold voltage range of the EEPROM cell will decrease. Accordingly, the threshold voltage value of the EEPROM cell changes after the staging and erasing operations.

A conventional method for programming a flash EEPROM cell is to apply a high voltage to the drain of the EEPROM cell transistor. For example, if there are eight EEPROM cell transistors that need to be programmed, a high voltage is applied to the drain of an EEPROM cell transistor each time in a sequential manner. Therefore, the number of times the high voltage is applied to the drains of all the EEPROM cell transistors is eight times. After the eight EEPROM cell transistors have all performed the stylized operation, a verify operation is performed to check if all of the EEPROM cells have been programmed. If all of the memory cells have been programmed, the stylization of the cells is complete and no further stylization is required. Conversely, if any of the memory cells are not programmed, the cells must undergo a second stylization. At the second stylization, the high voltage is applied to the drain of an EEPROM cell transistor each time in a sequential manner. This verification operation continues after the high voltage is applied to all of the EEPROM cell transistors for eight times. These stylization and verification operations are repeated continuously until all of the threshold voltages of the programmed EEPROM cell transistors reach a predetermined value (e.g., 6V).

As mentioned above, the total time required to complete a stylized operation in a conventional stylized operation increases with the number of repetitive stylization steps required. In addition, a verification operation is required after each stylization operation to confirm whether the threshold voltage of the EEPROM cell transistor to be programmed has reached a predetermined value. Therefore, the overall stylized time is increased by the steps of inserting multiple verification operations. The memory component also requires multiple complex circuits to perform the verify operation. Accordingly, it is necessary to propose an improved stylized method to solve the above problems.

It is an object of the present invention to provide a method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory device. By the method disclosed by the present invention, the overall time for staging the memory cells can be greatly reduced.

In order to achieve the above object, an embodiment of the method of the present invention comprises the steps of sequentially performing a plurality of divisions by two operations in the memory cells, and from the completion of the operations of dividing by two A plurality of progressively decreasing groups are generated in the memory unit cell, and the memory cell in the step-down group generated is programmed after each operation of dividing by 2, and the last division is performed. After the operation of 2, a final group is generated, a plurality of memory cells in the final group are programmed, and it is verified whether the memory cells in the final group have been programmed.

To clearly illustrate the method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory device disclosed herein, the architecture of the non-volatile semiconductor memory device in the present invention for performing the method will first be described. 3 shows a block diagram of a non-volatile semiconductor memory device 30 incorporating one embodiment of the present invention. Referring to FIG. 3, the memory component 30 includes a memory cell array 32. The memory cell array 32 includes a plurality of memory cells MC arranged in rows and columns. In one embodiment of the invention, the non-volatile semiconductor memory device 30 is a NOR-form flash EEPROM device, and a plurality of NOR-formed flash EEPROM cells form the entire memory cell array 32.

Referring to FIG. 3, a plurality of word lines WL are connected to a plurality of first terminals in the memory cells MC, and a plurality of bit lines BL are connected to a plurality of second terminals in the memory cells MC. A column of decoders 36 is coupled to the memory cell array 32 to provide a plurality of word line voltages for the memory cell array 32, and a row of decoders 34 is coupled to the memory cell array 32 to provide the memory cell. The array has more than 32 bit line voltages. A sense amplifier section 38 includes a plurality of sense amplifiers for detecting and amplifying data in the memory cell MC connected to the selected column of the memory cell array 32. A write driver segment 40 includes a plurality of write drivers for writing data to selected memory cells MC in the memory cell array 32. A high voltage generator 44 generates a high voltage required to program the memory cell in response to the programmed signal and applies the high voltage to the sense amplifier segment 38 and the write driver segment 40.

4 shows a flow chart of a method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory in accordance with an embodiment of the present invention. The method comprises the steps of sequentially performing a plurality of divisions by two operations in a plurality of memory cells (S10), and generating a plurality of steps from the memory cells after the operation of dividing by two is completed. The reduced group (S20), the memory cell in the step-down group generated is programmed after each operation of dividing by 2 (S30), and the last division by 2 is performed. Then generating a final group (S40), stabilizing a plurality of memory cells in the final group (S50), and verifying whether the memory cells in the final group have been programmed (S60) ). Details of the stylized method disclosed by the present invention will be described below.

Referring to FIG. 3, after receiving a stylized command PGM_S, the memory element 30 enters a programmable mode, and a decoding controller 42 generates a decoded signal to the row decoder 34 and the column decoder 36 to determine the difference. The memory cell to be programmed in the memory cell array 32 at the time. Figure 5 shows a timing diagram of a stylized operation in conjunction with an embodiment of the present invention. In the present embodiment, the number of memory cells to be programmed is set to eight. However, the invention should not be limited thereto. Referring to FIG. 5, during a first stylized operation, the stylized signal PGM1 has a high logic level during the time interval T1, and the stylized signal PGM2 has a high logic level during the time interval T2, and the stylized signal PGM3 is at The time interval T3 has a high logic level, and the stylized signal PGM4 has a high logic level during the time interval T1.

The stylized signals PGM1 through PGM4 are signals indicating the memory cells that will be programmed at the same time each time. In other words, when one of the programmed signals PGM1 to PGM4 transitions from a low logic level to a high logic level, the particular memory cells corresponding to the programmed signals PGM1 through PGM4 are simultaneously programmed. In an embodiment of the invention, during the first stylization operation, the memory cells 0 to 7 are divided into four groups, and the stylized operation is performed four times in a group-by-group manner. For example, during the first stylization operation, the memory cells 0 and 4 corresponding to the stylized signal PGM1 belong to the first group and are simultaneously programmed during the time interval T1; corresponding to the stylized signal The memory cells 1 and 5 of PGM2 belong to the second group and are simultaneously programmed during the time interval T2; the memory cells 2 and 6 corresponding to the stylized signal PGM3 belong to the third group, and at time interval T3 The period is simultaneously stylized; the memory cells 3 and 7 corresponding to the stylized signal PGM4 belong to the fourth group and are simultaneously programmed during the time interval T4.

After the first stylization, the memory cells 0 through 7 are divided into two groups, and in the second stylized operation, the stylized operation is performed twice in a set-by-group manner. Referring to FIG. 5, during the second stylization operation, the stylized signals PGM1 and PGM2 transition from a low logic level to a high logic level during a time interval T5, while the stylized signals PGM3 and PGM4 are at a time interval T6. The period will be changed from a low logic level to a high logic level. Therefore, in the second stylization operation, the memory cells 0, 1, 4, and 5 corresponding to the stylized signals PGM1 and PGM2 belong to the first group, and are simultaneously programmed during the time interval T5, and corresponding The memory cells 2, 3, 6 and 7 of the stylized signals PGM3 and PGM4 belong to the second group and are simultaneously programmed during the time interval T6.

After the second stylization operation, the memory cells 0 to 7 will be classified into only one group, and the stylized operation will be performed only once during the third stylization operation. That is, at the last grouping, all memory cells that need to be programmed are classified into the same group. Referring to Figure 5, during the third stylization operation, the stylized signals PGM1 through PGM4 will have a high logic level during time interval T7. Therefore, during this third stylization operation, all of the memory cells 0 to 7 are simultaneously programmed during the time interval T7. After this third stylization operation, a verification operation is performed to confirm that all memory cells are programmable. Referring to Figure 5, a signal VERIFY has a high logic level during time interval T8. Therefore, during this third stylization operation, a stylized check operation will be performed during time interval T8.

The details of the stylized operation are described below with reference to FIG. Referring to FIG. 3, the high voltage generator 44 is coupled to the write driver section 40. The high voltage generator 44 generates a high voltage required to program the memory cells in response to the programmed signals PGM1 through PGM4 and applies the high voltage to the write driver segment 40. In one embodiment of the invention, the write driver section 40 applies the high voltage to the selected memory cell transistor to increase the threshold voltage during the staging operation. Therefore, the threshold voltage of the memory cells 0 to 7 increases during the first stylization operation and further increases during the second and third stylization operations, as shown in FIG. The increased amplitude of the threshold voltage of the memory cells 0 to 7 can be adjusted by changing the programmed time, for example, changing the time interval T1 to T7. In addition, the increased amplitude of the threshold voltage of the memory cells 0 to 7 can also be adjusted by changing the stylized voltage applied to the memory cell.

Referring to Figure 5, if any of the memory cells are not programmed, the stylization and verification operations are repeated. The verification operation can be performed by comparing the threshold voltage of each of the programmed memory cells with a predetermined value. If the threshold voltage of any of the memory cells does not reach the preset value, all of the memory cells 0 to 7 are reprogrammed. Conversely, if all of the threshold voltages of the programmed memory cells have reached the preset value, the verification step is not performed and the stylized operation of the memory cells MC is completed.

Compared to the conventional stylized operation, the number of memory cells that will be programmed at the same time in the second stylization operation will be reduced by half, and in the subsequent (third, fourth, .. .) The number of memory cells that will be programmed at the same time is reduced more during stylization, so the stylized overall time can be greatly reduced using the stylized method disclosed by the present invention. Furthermore, in the method of the present invention, the verification step is performed only after all of the memory cells are classified into the same group and simultaneously programmed. Therefore, the overall programming time can be reduced and the circuit of the memory element can be simplified in the present invention.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

10. . . Flash EEPROM cell

12. . . P-type substrate

13. . . N-type source region

14. . . N-type bungee area

15. . . Insulation

16. . . Floating gate

17. . . Insulation

18. . . Control gate

30. . . Non-volatile semiconductor memory component

32. . . Memory cell array

34. . . Row decoder

36. . . Column decoder

38. . . Sense amplifier section

40. . . Write to drive segment

42. . . Decoding controller

44. . . High voltage generator

S10~S60. . . step

Figure 1 shows a vertical sectional view of a flash EEPROM cell;

Figure 2 shows the threshold voltage range of the flash EEPROM cell during stylized operation and erase operation;

3 is a block diagram showing a nonvolatile semiconductor memory device incorporating an embodiment of the present invention;

4 is a flow chart showing a method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory in accordance with an embodiment of the present invention;

Figure 5 shows a timing diagram of a stylized operation in connection with an embodiment of the present invention;

Figure 6 shows the variation of the threshold voltage of the memory cells after multiple stylized operations.

S10~S60. . . step

Claims (7)

A method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory device, comprising the steps of sequentially performing a plurality of divisions by two operations in the memory cells; After the operation of 2 is completed, a plurality of gradually decreasing groups are generated from the memory cells; after each operation of dividing by 2 is completed, the memory cell in the step-down group generated is programmed. Generating a final group after performing the last divide by 2 operation; stylizing a plurality of memory cells in the final group; and verifying whether the memory cells in the final group have been averaged Stylized; wherein the memory cells in the final group are composed of all memory cells in the non-volatile semiconductor memory, and the verifying step is only in the stylized final group Performing the steps of the memory cells: wherein the plurality of divisions by 2 are performed sequentially in the memory cells and generated from the memory cells after the operations of dividing by 2 are completed Multiple step by step group Furthermore, the first division by 2 is performed in m memory cells to divide m memory cells into n groups, each group consisting of m/n memory cells. And performing the second divide by 2 operation in m memory cells to divide n memory cells into n/2 groups after performing the first divide by 2 operation, each of which The group consists of 2m/n memory cells. The method of claim 1, wherein the non-volatile semiconductor memory is a NOR type flash EEPROM. The method of claim 1, further comprising: if the programming of any of the memory cells in the final group fails, reprogramming the memory cells in the final group. The method of claim 1, wherein the verifying step is performed by comparing a threshold voltage of each of the programmed memory cells with a predetermined voltage value. The method of claim 1, wherein the stylizing step is performed by increasing a threshold voltage of the memory cells. According to the method of claim 4, wherein the threshold voltages of the memory cells are controlled by applying different stylized time intervals to the memory cells. According to the method of claim 4, wherein the threshold voltages of the memory cells are controlled by applying different voltages to the memory cells.