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TWI473181B - Package substrate with electrical connection structure and preparation method thereof - Google Patents

Package substrate with electrical connection structure and preparation method thereof Download PDF

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Publication number
TWI473181B
TWI473181B TW96147578A TW96147578A TWI473181B TW I473181 B TWI473181 B TW I473181B TW 96147578 A TW96147578 A TW 96147578A TW 96147578 A TW96147578 A TW 96147578A TW I473181 B TWI473181 B TW I473181B
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Taiwan
Prior art keywords
layer
electrical connection
package substrate
tin
connection structure
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TW96147578A
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Chinese (zh)
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TW200926317A (en
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史朝文
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欣興電子股份有限公司
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Priority to TW96147578A priority Critical patent/TWI473181B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

具電性連接結構之封裝基板及其製法Package substrate with electrical connection structure and preparation method thereof

本發明係有關於一種封裝基板及其製法,尤指一種具電性連接結構之封裝基板及其製作方法。The present invention relates to a package substrate and a method for fabricating the same, and more particularly to a package substrate having an electrical connection structure and a method of fabricating the same.

目前半導體晶片與封裝基板之電性連接方式包括有打線式(Wire bonding)及覆晶式(Flip Chip)兩種技術,其中之打線式封裝結構係以焊線將半導體晶片電性連接至封裝基板,而該覆晶式封裝結構係將半導體晶片以主動面朝下之倒置方式安置於封裝基板上,並藉由複數個焊塊(Bump)而焊結並電性連接至封裝基板上,由於覆晶式封裝結構不需要使用較佔空間之焊線,且電訊傳輸距離較短,以將半導體晶片電性連接至封裝基板,因此可使整體封裝結構更為輕薄短小。現行封裝技術中,無論打線式或覆晶式封裝結構在完成接置有半導體晶片之封裝基板進行封裝製程時,均須於該封裝基板底面植設複數球閘陣列配置(Ball Grid Array,BGA)之焊球(Solder ball),作為該封裝基板與外界電子裝置(如印刷電路板)之電性連接。At present, the electrical connection between the semiconductor chip and the package substrate includes two technologies: wire bonding and Flip Chip, wherein the wire-bonding package electrically connects the semiconductor chip to the package substrate by wire bonding. The flip-chip package structure is disposed on the package substrate with the active surface facing down, and is soldered and electrically connected to the package substrate by a plurality of bumps. The crystalline package structure does not require the use of a space-consuming bonding wire, and the telecommunications transmission distance is short to electrically connect the semiconductor wafer to the package substrate, thereby making the overall package structure lighter, thinner and shorter. In the current packaging technology, when a packaged circuit is mounted on a package substrate on which a semiconductor wafer is mounted, a plurality of ball grid arrays (BGAs) must be implanted on the bottom surface of the package substrate. The solder ball is electrically connected to the external electronic device (such as a printed circuit board).

目前常用於封裝基板之電性連接墊(包括晶片接置區及植球區)上形成焊接材料的製作方法為模板印刷技術。主要係於一完成電路佈線之封裝基板上形成具絕緣保護層開孔之絕緣保護層,並外露出多數電性連接墊,以令一具有複數個模孔之模板置於該封裝基板之絕緣保護層上,透過該些模孔以在電性連接墊上形成焊錫堆。可採用刮刀或噴灑方式,以將焊料堆積在模孔內,於該模板移除後,形成焊錫堆。復進行迴焊製程,使電性連接墊上之焊錫堆固化形成焊錫結構。At present, a method for fabricating a solder material on an electrical connection pad (including a wafer connection region and a ball placement region) of a package substrate is a stencil printing technique. The invention mainly comprises forming an insulating protective layer with an insulating protective layer opening on a package substrate on which the circuit wiring is completed, and exposing a plurality of electrical connecting pads, so that a template having a plurality of die holes is placed on the insulating protection of the package substrate On the layer, through the die holes, a solder stack is formed on the electrical connection pads. A scraper or spray can be used to deposit the solder in the die hole, and after the template is removed, a solder bump is formed. The reflow process is repeated to cure the solder bump on the electrical connection pad to form a solder structure.

請參閱第1A及1B圖所示,係為顯示習知在封裝基板之電性連接墊上形成焊接材料之局部示意圖,係於一具有電性連接墊12之封裝基板10上形成有絕緣保護層11,且該絕緣保護層11具有開孔11a,該電性連接墊12與該開孔11a之間形成近90度之角落C,從而使得於該開孔11a中形成焊接材料時,由於該角落C係約呈90度角,以致焊接材料不易沉積於該角落C。此外,對該焊接材料進行迴焊製程時,由於焊接材料在未凝固前,因為液態狀金屬凝聚力與表面張力的關係,而未能完全填充於該90度的角落C處,使得經迴焊製程所形成的焊錫結構15與絕緣保護層11之間會產生間隙S(如第1B圖所示),而有氣泡形成於其中,如此,後續製程中將發生焊錫結構15剝離等信賴性不佳問題。Please refer to FIGS. 1A and 1B for a partial schematic view showing the formation of a solder material on an electrical connection pad of a package substrate, and an insulating protection layer 11 is formed on a package substrate 10 having an electrical connection pad 12. And the insulating protective layer 11 has an opening 11a, and the electrical connecting pad 12 forms a corner C of nearly 90 degrees with the opening 11a, so that when the solder material is formed in the opening 11a, the corner C The line is at an angle of about 90 degrees, so that the solder material is not easily deposited in the corner C. In addition, when the soldering material is subjected to the reflow process, since the solder material is not solidified, the liquid metal cohesive force and the surface tension are not completely filled in the corner C of the 90 degree, so that the reflow process is performed. A gap S is formed between the formed solder structure 15 and the insulating protective layer 11 (as shown in FIG. 1B), and bubbles are formed therein, so that a problem of poor reliability such as peeling of the solder structure 15 occurs in a subsequent process. .

此外,由於焊接材料未能完全填充於該電性連接墊與絕緣保護層開孔間所夾之角落,使得焊接材料與該電性連接墊之接觸面積縮減,造成後續形成焊錫結構之焊接材料不易附著在該電性連接墊上,從而影響了焊球之品質及封裝基板之電性連接性能。In addition, since the solder material is not completely filled in the corner between the electrical connection pad and the opening of the insulating protective layer, the contact area between the solder material and the electrical connection pad is reduced, which makes the solder material of the subsequent solder structure difficult to be formed. Adhered to the electrical connection pad, thereby affecting the quality of the solder ball and the electrical connection performance of the package substrate.

又該焊錫結構15於迴焊製程中僅藉由該絕緣保護層11之拒焊特性防止該焊錫結構15產生溢流,惟該焊錫結構15於迴焊時成為液態時,如應用於細間距電性連接墊之封裝基板時,則兩相鄰之焊錫結構15容易因溢流橋接而造成短路;為此,則必須加大該焊錫結構15之間的間距,故無法提供細間距封裝基板之使用需求。Moreover, the solder structure 15 prevents the solder structure 15 from overflowing only by the solder resisting property of the insulating protective layer 11 in the reflow process, but the solder structure 15 is in a liquid state during reflow, as applied to fine pitch electric When the package substrate of the connection pad is connected, the two adjacent solder structures 15 are easily short-circuited due to overflow bridging; therefore, the spacing between the solder structures 15 must be increased, so that the use of the fine pitch package substrate cannot be provided. demand.

因此,鑒於上述之問題,如何避免習知技術中焊接材料之形成不易、形成的焊錫結構與絕緣保護層之間產生間隙、無法提昇焊錫結構與封裝基板之電性連接品質、以及焊錫結構於迴焊製程中產生溢流等問題,實已成目前亟欲解決的課題。Therefore, in view of the above problems, how to avoid the formation of solder materials in the prior art is difficult, a gap is formed between the formed solder structure and the insulating protective layer, the electrical connection quality of the solder structure and the package substrate cannot be improved, and the solder structure is returned. Problems such as overflow in the welding process have become a problem that is currently being solved.

鑒於上述習知技術之缺失,本發明之一目的係提供一種具電性連接結構之封裝基板及其製法,避免焊接材料於迴焊製程中產生溢流而導致短路。In view of the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide a package substrate having an electrical connection structure and a method of manufacturing the same, which prevents the solder material from overflowing in the reflow process and causing a short circuit.

本發明之又一目的係提供一種具電性連接結構之封裝基板及其製法,得提供細間距之電性連接結構。Another object of the present invention is to provide a package substrate having an electrical connection structure and a method of fabricating the same, which provides a fine pitch electrical connection structure.

本發明之再一目的係提供一種具電性連接結構之封裝基板及其製法,得提高形成於金屬層上之焊接材料與電性連接墊之間的結合性,以避免產生脫落。A further object of the present invention is to provide a package substrate having an electrical connection structure and a method of manufacturing the same, which improves the bonding between the solder material formed on the metal layer and the electrical connection pads to prevent detachment.

為達上述及其他目的,本發明揭露一種具電性連接結構之封裝基板,係包括:封裝基板本體,於其至少一表面具有複數電性連接墊,且於該表面及電性連接墊上具有一絕緣保護層,該絕緣保護層具有對應各該電性連接墊之開孔,以外露出該電性連接墊之部份表面;化鍍接著層,係位於該電性連接墊之外露表面;以及金屬層,係位於該化鍍接著層上、絕緣保護層之開孔側壁及絕緣保護層於該開孔外部之表面上。To achieve the above and other objects, the present invention discloses a package substrate having an electrical connection structure, comprising: a package substrate body having a plurality of electrical connection pads on at least one surface thereof, and having a surface on the surface and the electrical connection pads An insulating protective layer having an opening corresponding to each of the electrical connection pads, exposing a portion of the surface of the electrical connection pad; a plating adhesion layer disposed on an exposed surface of the electrical connection pad; and a metal The layer is located on the plating adhesion layer, the sidewall of the insulating protective layer and the insulating protective layer on the surface outside the opening.

依上述結構,復包括於該化鍍接著層上、絕緣保護層開孔之側壁及絕緣保護層於該開孔外部之表面上,以及於該金屬層之下表面具有一導電層。According to the above structure, the sidewall of the insulating plating layer and the insulating protective layer on the surface of the opening of the opening and the conductive layer are provided on the lower surface of the metal layer.

又依上述之結構,於該金屬層表面上具有焊接材料;或於該金屬層上表面具有表面處理層,且於該表面處理層上具有焊接材料;或於該金屬層之上表面及側表面具有表面處理層,且於該表面處理層外表面具有焊接材料。Further, according to the above structure, the surface of the metal layer has a solder material; or the surface of the metal layer has a surface treatment layer, and the surface treatment layer has a solder material; or the upper surface and the side surface of the metal layer It has a surface treatment layer and has a solder material on the outer surface of the surface treatment layer.

該化鍍接著層係為鎳/金(Ni/Au,係先形成鎳,之後再形成金)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者;該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者;該金屬層係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬其中一者。The plating adhesion layer is nickel/gold (Ni/Au, which is formed by nickel first, then gold is formed), nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), and nickel-palladium immersion gold (Electroless Nickel/Electroless) Palladium/Immersion Gold, ENEPIG), Immersion Tin, and Direct Immersion Gold (DIG); the solder material is tin-lead (Sn/Pb), tin-silver (Sn/) One of Ag), tin-silver-copper (Sn/Ag/Cu), tin-copper (Sn/Cu), tin (Sn), and low-melting solder of lead-free solder; the metal layer is copper (Cu), gold (Au ), one of silver (Ag) and high lead (high lead) high melting point metals.

本發明復提供一種具電性連接結構之封裝基板之製法,係包括:提供至少一表面形成有電性連接墊之封裝基板本體,且於該封裝基板本體上形成絕緣保護層,該絕緣保護層具有開孔以露出該電性連接墊之部份表面;於該電性連接墊之外露表面形成化鍍接著層;於該化鍍接著層、絕緣保護層及其開孔處表面上形成一導電層;於該導電層上形成一阻層,且該阻層中對應該電性連接墊位置形成阻層開口,以外露出對應該電性連接墊及其周圍之絕緣保護層上之導電層;進行電鍍製程,以於該阻層開口中之導電層上形成一金屬層;以及移除該阻層及其所覆蓋之導電層以露出該金屬層。The invention provides a method for manufacturing a package substrate having an electrical connection structure, comprising: providing a package substrate body having at least one surface formed with an electrical connection pad, and forming an insulation protection layer on the package substrate body, the insulation protection layer Having an opening to expose a portion of the surface of the electrical connection pad; forming a plating adhesion layer on the exposed surface of the electrical connection pad; forming a conductive layer on the surface of the plating adhesion layer, the insulating protection layer and the opening thereof a resist layer is formed on the conductive layer, and a resist layer opening is formed in the resist layer corresponding to the position of the electrical connection pad, and the conductive layer on the insulating protective layer corresponding to the electrical connection pad and the periphery thereof is exposed; An electroplating process to form a metal layer on the conductive layer in the opening of the resist layer; and removing the resist layer and the conductive layer covered thereby to expose the metal layer.

依上述製法,復包括於該金屬層表面形成焊接材料;或復包括於該金屬層上表面形成表面處理層,再於該表面處理層上形成焊接材料;或復包括於該金屬層之上表面及側表面形成表面處理層,再於該表面處理層外表面形成焊接材料。According to the above method, a solder material is formed on the surface of the metal layer; or a surface treatment layer is formed on the upper surface of the metal layer, and a solder material is formed on the surface layer; or is included on the surface of the metal layer. And the side surface forms a surface treatment layer, and a solder material is formed on the outer surface of the surface treatment layer.

該化鍍接著層係為鎳/金(Ni/Au,係先形成鎳,之後再形成金)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者;該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者;該金屬層係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬其中一者。The plating adhesion layer is nickel/gold (Ni/Au, which is formed by nickel first, then gold is formed), nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), and nickel-palladium immersion gold (Electroless Nickel/Electroless) Palladium/Immersion Gold, ENEPIG), Immersion Tin, and Direct Immersion Gold (DIG); the solder material is tin-lead (Sn/Pb), tin-silver (Sn/) One of Ag), tin-silver-copper (Sn/Ag/Cu), tin-copper (Sn/Cu), tin (Sn), and low-melting solder of lead-free solder; the metal layer is copper (Cu), gold (Au ), one of silver (Ag) and high lead (high lead) high melting point metals.

本發明之具電性連接結構之封裝基板及其製法中,係先在電性連接墊表面先化學沉積形成化鍍接著層,再於該化鍍接著層上透過導電層電鍍形成該金屬層,以藉由該化鍍接著層結合該電性連接墊與金屬層,並使形成於該金屬層上之焊接材料於迴焊製程中,得藉由該金屬層與焊接材料之間的親合性,以及該金屬層高熔點不熔之特性,以限制液態焊接材料流動,使該焊接材料避免產生溢流,進而得以提供細間距封裝基板之電性連接;且藉由該形成於電性連接墊及金屬層之間的化鍍接著層,以提高電性連接墊及金屬層之結合強度,以避免形成於金屬層上之焊接材料產生脫落。In the package substrate with the electrical connection structure of the present invention and the method for fabricating the same, the surface of the electrical connection pad is first chemically deposited to form a subsequent layer, and then the metal layer is formed by electroplating on the subsequent layer. The affinity between the metal layer and the solder material is obtained by bonding the electrical connection pad and the metal layer by the plating adhesion layer and the solder material formed on the metal layer in the reflow process. And the high melting point non-melting property of the metal layer to restrict the flow of the liquid solder material, so that the solder material avoids overflow, thereby providing an electrical connection of the fine pitch package substrate; and by forming the electrical connection pad And plating the adhesion layer between the metal layers to improve the bonding strength between the electrical connection pad and the metal layer to prevent the solder material formed on the metal layer from falling off.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

請參閱第2A圖至第2E圖,係顯示本發明具電性連接結構之封裝基板製法的剖面示意圖。2A to 2E are schematic cross-sectional views showing a method of manufacturing a package substrate having an electrical connection structure according to the present invention.

如第2A圖所示,提供至少一表面形成有電性連接墊200之封裝基板本體20,其係為一已完成線路佈局之兩層或多層封裝基板,其中該電性連接墊200係可藉由導電盲孔(圖未示)電性連接內層線路。As shown in FIG. 2A, at least one package substrate body 20 having an electrical connection pad 200 formed thereon is provided as a two-layer or multi-layer package substrate having a completed circuit layout, wherein the electrical connection pad 200 can be borrowed. The inner layer line is electrically connected by a conductive blind hole (not shown).

該封裝基板本體20上復形成有絕緣保護層21,該絕緣保護層21係利用印刷、旋塗及貼合之任一方式塗覆於該封裝基板上,且該絕緣保護層21可為例如綠漆等具有縮錫特性之防焊材料所製成,並藉由曝光、顯影等方式加以圖案化使該絕緣保護層21形成有外露出該電性連接墊200之開孔210。An insulating protective layer 21 is formed on the package substrate body 20, and the insulating protective layer 21 is applied to the package substrate by any one of printing, spin coating and bonding, and the insulating protective layer 21 can be, for example, green. A solder resist material having a tin-reducing property such as lacquer is formed, and patterned by exposure, development, or the like to form the insulating protective layer 21 with an opening 210 exposing the electrical connection pad 200.

如第2B圖所示,於該電性連接墊200之外露表面形成化鍍接著層22;該化鍍接著層22係為鎳/金(Ni/Au,係先形成鎳,之後再形成金)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。As shown in FIG. 2B, a plating adhesion layer 22 is formed on the exposed surface of the electrical connection pad 200; the plating adhesion layer 22 is made of nickel/gold (Ni/Au, which is formed by nickel first, then gold is formed). , Electroless Ni & Immersion Gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Immersion Tin, and Direct Immersion Gold (Direct Immersion Gold, One of DIG).

如第2C圖所示,於該化鍍接著層22上表面、絕緣保護層21上表面及其開孔210側表面形成一導電層23,該導電層23主要作為後述電鍍金屬材料所需之電流傳導路徑,其可由金屬、合金或沉積數層金屬層所構成,或可使用導電高分子材料以作為該導電層23;接著於該導電層23上覆蓋一阻層24,並加以圖案化該阻層24。該阻層24可為一例如乾膜或液態光阻等光阻層(Photoresist),其係利用印刷、旋塗或貼合等方式形成於該導電層23表面,再藉由曝光、顯影等方式加以圖案化,以使該阻層24形成有阻層開口240,而該阻層開口240係對應於該電性連接墊200之位置,且該阻層開口240尺寸係大於該開孔210尺寸,藉以顯露出對應於該電性連接墊200及該電性連接墊200周圍之部分絕緣保護層21上之導電層23。As shown in FIG. 2C, a conductive layer 23 is formed on the upper surface of the plating resist layer 22, the upper surface of the insulating protective layer 21, and the surface of the opening 210 thereof. The conductive layer 23 is mainly used as a current required for plating a metal material to be described later. a conductive path, which may be composed of a metal, an alloy or a plurality of deposited metal layers, or a conductive polymer material may be used as the conductive layer 23; then a resist layer 24 is overlaid on the conductive layer 23 and patterned to resist Layer 24. The resist layer 24 can be a photoresist layer such as a dry film or a liquid photoresist, which is formed on the surface of the conductive layer 23 by printing, spin coating or lamination, and then exposed, developed, etc. The resist layer 24 is formed with a resist opening 240, and the resist opening 240 corresponds to the position of the electrical connection pad 200, and the resist opening 240 is larger than the opening 210. Thereby, the conductive layer 23 corresponding to the electrical connection pad 200 and a portion of the insulating protective layer 21 around the electrical connection pad 200 is exposed.

如第2D圖所示,再對該封裝基板進行電鍍(Electroplating)製程,藉由該導電層23作為電流傳導路徑,以在顯露於該阻層開口240中之導電層23上電鍍形成金屬層25;其中,該金屬層25之材料係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬其中一者;惟,依實際操作之經驗,由於銅為成熟之電鍍材料且成本較低,因此,該金屬層25以由電鍍銅所構成者為較佳,但非以此為限;接著於該金屬層25表面上電鍍形成焊接材料26,該焊接材料26係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。又該焊接材料26之另一形成方式,係為該金屬層25電鍍形成後,以印刷方式形成焊接材料26於金屬層25表面。As shown in FIG. 2D, the package substrate is subjected to an electroplating process, and the conductive layer 23 is used as a current conduction path to form a metal layer 25 on the conductive layer 23 exposed in the resist layer opening 240. Wherein, the material of the metal layer 25 is one of copper (Cu), gold (Au), silver (Ag) and high lead (high lead) high melting point metal; however, according to practical experience, due to copper It is a mature electroplating material and has a low cost. Therefore, the metal layer 25 is preferably made of electroplated copper, but not limited thereto; then, a solder material 26 is formed on the surface of the metal layer 25, and the soldering is performed. Material 26 is a low melting point solder of tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/Cu), tin-copper (Sn/Cu), tin (Sn) and lead-free solder. One of them. Further, another form of the solder material 26 is formed by electroplating the metal layer 25 to form a solder material 26 on the surface of the metal layer 25.

如第2E圖所示,移除該阻層24及其所覆蓋之導電層23,以露出該金屬層25及焊接材料26。As shown in FIG. 2E, the resist layer 24 and the conductive layer 23 covered thereby are removed to expose the metal layer 25 and the solder material 26.

請參閱第3A及3B圖,於形成該焊接材料26之前,復可於該金屬層25上以電鍍或化學沉積形成一表面處理層27,接著再於該表面處理層27表面形成該焊接材料26,之後再移除該阻層24及其所覆蓋之導電層23,如第3A圖所示;或先移除該阻層24及其所覆蓋之導電層23以露出該金屬層25,然後於該金屬層25上表面及側表面形成表面處理層27’,接著再於該表面處理層27’外露表面形成該焊接材料26’,如第3B圖所示。此後,該焊接材料26,26’得進行迴焊製程與表面處理層27,27’以形成一焊球端結構,以供該封裝基板與外部電子裝置電性導接。Referring to FIGS. 3A and 3B, before the formation of the solder material 26, a surface treatment layer 27 is formed on the metal layer 25 by electroplating or chemical deposition, and then the solder material 26 is formed on the surface of the surface treatment layer 27. And then removing the resist layer 24 and the conductive layer 23 covered thereon, as shown in FIG. 3A; or removing the resist layer 24 and the conductive layer 23 covered thereby to expose the metal layer 25, and then The upper surface and the side surface of the metal layer 25 form a surface treatment layer 27', and then the exposed surface of the surface treatment layer 27' forms the solder material 26' as shown in Fig. 3B. Thereafter, the solder material 26, 26' is subjected to a reflow process and surface treatment layer 27, 27' to form a solder ball end structure for electrically connecting the package substrate to an external electronic device.

本發明復提供一種具電性連接結構之封裝基板,係包括:封裝基板本體20,於其至少一表面具有複數電性連接墊200,且於該表面及電性連接墊200上具有一絕緣保護層21,該絕緣保護層21具有對應各該電性連接墊之開孔210,以外露出該電性連接墊200之部份表面;化鍍接著層22,係位於該電性連接墊200之外露表面上;以及金屬層25,係位於該化鍍接著層22上、絕緣保護層21之絕緣保護層21之開孔210側壁及絕緣保護層21於該開孔210外部之表面上。The present invention provides a package substrate having an electrical connection structure, comprising: a package substrate body 20 having a plurality of electrical connection pads 200 on at least one surface thereof, and an insulation protection on the surface and the electrical connection pads 200 The insulating layer 21 has an opening 210 corresponding to each of the electrical connection pads, and a portion of the surface of the electrical connection pad 200 is exposed; and the plating adhesion layer 22 is exposed outside the electrical connection pad 200. The metal layer 25 is disposed on the plating resist layer 22, the sidewall of the opening 210 of the insulating protective layer 21 of the insulating protective layer 21, and the surface of the insulating protective layer 21 on the outside of the opening 210.

依上述結構,復包括於該化鍍接著層22上表面、絕緣保護層21之開孔210側壁及絕緣保護層21於該開孔210外部之表面上具有導電層23,且該導電層23位於該金屬層25之下表面。According to the above structure, the upper surface of the plating resist layer 22, the sidewall of the opening 210 of the insulating protective layer 21, and the insulating protective layer 21 have a conductive layer 23 on the surface of the outside of the opening 210, and the conductive layer 23 is located. The lower surface of the metal layer 25.

又於該金屬層25上表面具有焊接材料26,如第2E圖所示;或於該金屬層25上依序由下往上具有一表面處理層27及一焊接材料26,如第3A圖所示;或於該金屬層25之上表面及側表面具有表面處理層27’,且該表面處理層27’上具有焊接材料26,如第3B圖所示。Further, the upper surface of the metal layer 25 has a solder material 26 as shown in FIG. 2E; or a surface treatment layer 27 and a solder material 26 are sequentially provided on the metal layer 25 from bottom to top, as shown in FIG. 3A. Or a surface treatment layer 27' on the upper surface and the side surface of the metal layer 25, and the surface treatment layer 27' has a solder material 26 thereon, as shown in FIG. 3B.

該化鍍接著層22係為鎳/金(Ni/Au,係先形成鎳,之後再形成金)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。The plating adhesion layer 22 is made of nickel/gold (Ni/Au, which is formed by first forming nickel, then gold is formed), nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), and nickel-palladium immersion gold (Electroless Nickel/ Electroless Palladium/Immersion Gold, ENEPIG), Immersion Tin, and Direct Immersion Gold (DIG).

該焊接材料26係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。The solder material 26 is low in tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/Cu), tin-copper (Sn/Cu), tin (Sn), and lead-free solder. One of the melting point solders.

該金屬層25係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬其中一者。The metal layer 25 is one of copper (Cu), gold (Au), silver (Ag), and high-lead high melting point metals.

因此,本發明之具電性連接結構之封裝基板之製法,主要係在電性連接墊上先以化學沉積形成一化鍍接著層,接著於該化鍍接著層上、絕緣保護層之開孔側壁及絕緣保護層於該開孔外部之表面上,透過導電層以電鍍形成金屬層,俾使形成於該金屬層上表面之焊接材料在迴焊製程中,藉由該金屬層侷限液態焊接材料之流動,以避免該焊接材料產生溢流,進而得以提供細間距封裝基板之電性連接避免產生短路;且藉由該形成於電性連接墊及金屬層之化鍍接著層,以提高電性連接墊及金屬層之結合強度,以避免形成於金屬層上之焊接材料產生脫落。Therefore, the method for manufacturing the package substrate with the electrical connection structure of the present invention is mainly to form a plating adhesion layer on the electrical connection pad by chemical deposition, and then on the plating adhesion layer, the opening sidewall of the insulation protection layer. And an insulating protective layer on the surface of the outside of the opening, through the conductive layer to form a metal layer by electroplating, so that the solder material formed on the upper surface of the metal layer is in the reflow process, and the metal layer is limited by the liquid solder material Flowing to avoid overflow of the solder material, thereby providing electrical connection of the fine pitch package substrate to avoid short circuit; and improving the electrical connection by forming the adhesive layer formed on the electrical connection pad and the metal layer The bonding strength between the pad and the metal layer prevents the solder material formed on the metal layer from falling off.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10...封裝基板10. . . Package substrate

11、21...絕緣保護層11, 21. . . Insulating protective layer

11a、210...開孔11a, 210. . . Opening

12、200...電性連接墊12,200. . . Electrical connection pad

15...焊錫結構15. . . Solder structure

20...封裝基板本體20. . . Package substrate body

22...化鍍接著層twenty two. . . Plating layer

23...導電層twenty three. . . Conductive layer

24...阻層twenty four. . . Resistance layer

240...阻層開口240. . . Resistive layer opening

25...金屬層25. . . Metal layer

26、26’...焊接材料26, 26’. . . Welding materials

27、27’...表面處理層27, 27’. . . Surface treatment layer

C...角落C. . . corner

S...間隙S. . . gap

第1A及1B圖係顯示習知在封裝基板之電性連接墊上形成焊接材料之剖面示意圖;第2A至2E圖係為本發明之具電性連接結構之封裝基板及其製法的剖視示意圖;第3A圖係為第2E圖之另一實施結構;以及第3B圖係為第2E圖之又一實施結構。1A and 1B are schematic cross-sectional views showing the formation of a solder material on an electrical connection pad of a package substrate; and FIGS. 2A to 2E are cross-sectional views showing a package substrate having an electrical connection structure of the present invention and a method of manufacturing the same; Fig. 3A is another embodiment of Fig. 2E; and Fig. 3B is still another embodiment of Fig. 2E.

20...封裝基板本體20. . . Package substrate body

200...電性連接墊200. . . Electrical connection pad

21...絕緣保護層twenty one. . . Insulating protective layer

22...化鍍接著層twenty two. . . Plating layer

25...金屬層25. . . Metal layer

26...焊接材料26. . . Welding materials

Claims (22)

一種具電性連接結構之封裝基板,係包括:封裝基板本體,於其至少一表面具有複數電性連接墊,且於該表面及電性連接墊上具有一絕緣保護層,該絕緣保護層具有對應各該電性連接墊之開孔,以外露出該電性連接墊之部份表面;化鍍接著層,係位於該電性連接墊之外露表面上;導電層,係位於該化鍍接著層上、絕緣保護層之開孔側壁及絕緣保護層於該開孔周緣之表面上;以及金屬層,係位於該導電層上。 A package substrate having an electrical connection structure includes: a package substrate body having a plurality of electrical connection pads on at least one surface thereof, and an insulating protection layer on the surface and the electrical connection pad, the insulation protection layer having a corresponding Opening a hole of each of the electrical connection pads, exposing a portion of the surface of the electrical connection pad; depositing an adhesive layer on the exposed surface of the electrical connection pad; and electrically conducting the layer on the plating adhesion layer The sidewall of the insulating protective layer and the insulating protective layer are on the surface of the periphery of the opening; and the metal layer is located on the conductive layer. 如申請專利範圍第1項之具電性連接結構之封裝基板,其中,該化鍍接著層係為鎳/金層(Ni/Au)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。 The package substrate having an electrical connection structure according to claim 1, wherein the plating adhesion layer is a nickel/gold layer (Ni/Au), a nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), One of Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Immersion Tin, and Direct Immersion Gold (DIG). 如申請專利範圍第1項之具電性連接結構之封裝基板,復包括焊接材料,係位於該金屬層上表面。 A package substrate having an electrical connection structure according to claim 1 of the patent application, comprising a solder material, is located on an upper surface of the metal layer. 如申請專利範圍第3項之具電性連接結構之封裝基板,其中,該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。 A package substrate having an electrical connection structure according to claim 3, wherein the solder material is tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/Cu). One of the low melting point solders of tin-copper (Sn/Cu), tin (Sn) and lead-free solder. 如申請專利範圍第1項之具電性連接結構之封裝基板,其中,該金屬層係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬的其中一者。 A package substrate having an electrical connection structure according to claim 1, wherein the metal layer is a high melting point metal of copper (Cu), gold (Au), silver (Ag), and high lead (High Lead). One of them. 一種具電性連接結構之封裝基板,係包括:封裝基板本體,於其至少一表面具有複數電性連接墊,且於該表面及電性連接墊上具有一絕緣保護層,該絕緣保護層具有對應各該電性連接墊之開孔,以外露出該電性連接墊之部份表面;化鍍接著層,係位於該電性連接墊之外露表面上;金屬層,係位於該化鍍接著層上、絕緣保護層之開孔側壁及絕緣保護層於該開孔周緣之表面上;導電層,係位於該化鍍接著層上、絕緣保護層之開孔側壁及絕緣保護層於該開孔外部之表面上,並位於該金屬層之下表面;以及表面處理層,係位於該金屬層之上表面。 A package substrate having an electrical connection structure includes: a package substrate body having a plurality of electrical connection pads on at least one surface thereof, and an insulating protection layer on the surface and the electrical connection pad, the insulation protection layer having a corresponding Opening a hole of each of the electrical connection pads, exposing a portion of the surface of the electrical connection pad; depositing an adhesive layer on the exposed surface of the electrical connection pad; and the metal layer is on the plating adhesion layer The sidewall of the insulating protective layer and the insulating protective layer are on the surface of the periphery of the opening; the conductive layer is located on the plating subsequent layer, the sidewall of the insulating protective layer and the insulating protective layer are outside the opening The surface is located on the lower surface of the metal layer; and the surface treatment layer is located on the upper surface of the metal layer. 如申請專利範圍第6項之具電性連接結構之封裝基板,其中,該表面處理層復延伸至該金屬層之側表面上。 The package substrate having an electrical connection structure according to claim 6, wherein the surface treatment layer is extended to the side surface of the metal layer. 如申請專利範圍第6項之具電性連接結構之封裝基板,其中,該化鍍接著層係為鎳/金層(Ni/Au)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫 (Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。 The package substrate having an electrical connection structure according to claim 6 , wherein the plating adhesion layer is a nickel/gold layer (Ni/Au), a nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), chemical immersion tin (Immersion Tin), and one of Direct Immersion Gold (DIG). 如申請專利範圍第6項之具電性連接結構之封裝基板,其中,該金屬層係為銅(Cu)、金(Au)、銀(Ag)及高鉛(High Lead)之高熔點金屬的其中一者。 The package substrate having an electrical connection structure according to claim 6, wherein the metal layer is a high melting point metal of copper (Cu), gold (Au), silver (Ag) and high lead (High Lead). One of them. 如申請專利範圍第6項之具電性連接結構之封裝基板,其中,該表面處理層係為鎳/金層(Ni/Au)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin,IT)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。 The package substrate having an electrical connection structure according to the sixth aspect of the patent application, wherein the surface treatment layer is a nickel/gold layer (Ni/Au), a nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), One of Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Immersion Tin (IT), and Direct Immersion Gold (DIG). 如申請專利範圍第6項之具電性連接結構之封裝基板,復包括焊接材料,係位於該表面處理層上。 A package substrate having an electrical connection structure according to claim 6 of the patent application, comprising a solder material, is disposed on the surface treatment layer. 如申請專利範圍第11項之具電性連接結構之封裝基板,其中,該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。 A package substrate having an electrical connection structure according to claim 11 wherein the solder material is tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/Cu). One of the low melting point solders of tin-copper (Sn/Cu), tin (Sn) and lead-free solder. 一種具電性連接結構之封裝基板之製法,係包括:提供至少一表面形成有電性連接墊之封裝基板本體,且於該封裝基板本體上形成絕緣保護層,該絕緣保護層具有開孔以露出該電性連接墊之部份表面;於該電性連接墊之外露表面形成化鍍接著層; 於該化鍍接著層、絕緣保護層及其開孔側壁上形成一導電層;於該導電層上形成一阻層,且該阻層中對應該電性連接墊位置形成阻層開口,以外露出對應該電性連接墊及其周圍之絕緣保護層上之導電層;進行電鍍製程,以於該阻層開口中之導電層上形成一金屬層;以及移除該阻層及其所覆蓋之導電層以露出該金屬層。 A method for manufacturing a package substrate having an electrical connection structure, comprising: providing a package substrate body having at least one surface formed with an electrical connection pad, and forming an insulation protection layer on the package substrate body, the insulation protection layer having an opening Exposing a portion of the surface of the electrical connection pad; forming a plating adhesion layer on the exposed surface of the electrical connection pad; Forming a conductive layer on the plating adhesion layer, the insulating protective layer and the sidewalls thereof; forming a resist layer on the conductive layer, and forming a resist layer opening corresponding to the position of the electrical connection pad in the resist layer Corresponding to the conductive layer on the electrical connection pad and the insulating protective layer around it; performing an electroplating process to form a metal layer on the conductive layer in the opening of the resist layer; and removing the resist layer and the conductive layer covered thereby A layer to expose the metal layer. 如申請專利範圍第13項之具電性連接結構之封裝基板之製法,其中,該化鍍接著層係為鎳/金層(Ni/Au)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。 The method for manufacturing a package substrate having an electrical connection structure according to claim 13, wherein the plating adhesion layer is a nickel/gold layer (Ni/Au), and a nickel immersion gold (Electroless Ni & Immersion Gold, ENIG) ), one of Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Immersion Tin, and Direct Immersion Gold (DIG). 如申請專利範圍第13項之具電性連接結構之封裝基板之製法,復包括於該金屬層上表面形成焊接材料。 The method for manufacturing a package substrate having an electrical connection structure according to claim 13 of the patent application, comprising forming a solder material on an upper surface of the metal layer. 如申請專利範圍第15項之具電性連接結構之封裝基板之製法,其中,該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。 The method for manufacturing a package substrate having an electrical connection structure according to claim 15, wherein the solder material is tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/). One of Cu, tin-copper (Sn/Cu), tin (Sn), and low-melting solders of lead-free solder. 如申請專利範圍第13項之具電性連接結構之封裝基板之製法,其中,該金屬層係為銅(Cu)、金(Au)、銀 (Ag)及高鉛(High Lead)之高熔點金屬其中一者。 The method for manufacturing a package substrate having an electrical connection structure according to claim 13 , wherein the metal layer is copper (Cu), gold (Au), and silver. One of (Ag) and High Lead high melting point metals. 如申請專利範圍第13項之具電性連接結構之封裝基板之製法,復包括於該金屬層上表面形成表面處理層。 The method for manufacturing a package substrate having an electrical connection structure according to claim 13 of the patent application, comprising forming a surface treatment layer on the upper surface of the metal layer. 如申請專利範圍第13項之具電性連接結構之封裝基板之製法,復包括於該金屬層之上表面及側表面形成表面處理層。 The method for manufacturing a package substrate having an electrical connection structure according to claim 13 of the patent application, comprising forming a surface treatment layer on the upper surface and the side surface of the metal layer. 如申請專利範圍第18或19項之具電性連接結構之封裝基板之製法,其中,該表面處理層係為鎳/金層(Ni/Au)、化鎳浸金(Electroless Ni & Immersion Gold,ENIG)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、化學浸錫(Immersion Tin,IT)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。 The method for manufacturing a package substrate having an electrical connection structure according to claim 18 or 19, wherein the surface treatment layer is a nickel/gold layer (Ni/Au) or a nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Immersion Tin (IT), and Direct Immersion Gold (DIG). 如申請專利範圍第18或19項之具電性連接結構之封裝基板之製法,復包括於該表面處理層上形成焊接材料。 The method for manufacturing a package substrate having an electrical connection structure according to claim 18 or 19, further comprising forming a solder material on the surface treatment layer. 如申請專利範圍第21項之具電性連接結構之封裝基板之製法,其中,該焊接材料係為錫鉛(Sn/Pb)、錫銀(Sn/Ag)、錫銀銅(Sn/Ag/Cu)、錫銅(Sn/Cu)、錫(Sn)及無鉛焊料之低熔點焊料其中一者。 The method for manufacturing a package substrate having an electrical connection structure according to claim 21, wherein the solder material is tin-lead (Sn/Pb), tin-silver (Sn/Ag), tin-silver-copper (Sn/Ag/ One of Cu, tin-copper (Sn/Cu), tin (Sn), and low-melting solders of lead-free solder.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW579589B (en) * 2002-12-31 2004-03-11 Advanced Semiconductor Eng Substrate bonding pad structure
TWI237860B (en) * 2004-02-13 2005-08-11 Advanced Semiconductor Eng Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof
TWI240400B (en) * 2005-01-04 2005-09-21 Nan Ya Printed Circuit Board C Method for fabricating a packaging substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW579589B (en) * 2002-12-31 2004-03-11 Advanced Semiconductor Eng Substrate bonding pad structure
TWI237860B (en) * 2004-02-13 2005-08-11 Advanced Semiconductor Eng Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof
TWI240400B (en) * 2005-01-04 2005-09-21 Nan Ya Printed Circuit Board C Method for fabricating a packaging substrate

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