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TWI465388B - Method for manufacturing nano roughing array structure - Google Patents

Method for manufacturing nano roughing array structure Download PDF

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TWI465388B
TWI465388B TW101108892A TW101108892A TWI465388B TW I465388 B TWI465388 B TW I465388B TW 101108892 A TW101108892 A TW 101108892A TW 101108892 A TW101108892 A TW 101108892A TW I465388 B TWI465388 B TW I465388B
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array structure
metal
nano
manufacturing
carrier element
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TW101108892A
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TW201336776A (en
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Cheng Han Ho
Jr Hau Ho
Kun Yu Lai
Guan Jhong Lin
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Univ Nat Taiwan
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Description

奈米粗化陣列結構之製造方法Nano coarsening array structure manufacturing method

本發明係關於一種微結構的製造方法,特別是有關於一種奈米粗化陣列結構之製造方法。The present invention relates to a method of fabricating a microstructure, and more particularly to a method of fabricating a nano-roughened array structure.

在習知技術中,發光二極體以及太陽能電池的應用相當普及,然而發光二極體的光源由內部產生後,輸出至外部空氣介面的光取出效率(Light extraction efficiency)之低落,以及光線由空氣介面導入至太陽能電池之光電表面的光電轉換效率之低落,其原因可由司乃耳定律(Snell’s Law)得知,當光線入射到不同介質之界面會發生反射及折射的現象,從而使得光線在不同介質下無法有效的輸出或導入。In the prior art, the application of the light-emitting diode and the solar cell is quite popular. However, when the light source of the light-emitting diode is internally generated, the light extraction efficiency output to the external air interface is low, and the light is The low photoelectric conversion efficiency of the air interface introduced into the photovoltaic surface of the solar cell is known by Snell's Law, and when light is incident on the interface of different media, reflection and refraction occur, so that the light is Cannot be effectively output or imported under different media.

一般而言,為了增加發光二極體的光取出效率或是增加太陽能電池的光電轉換效率之方法,主要是在發光二極體的出光面或太陽能電池的入光面形成微奈米粗化結構。以發光二極體為例,微奈米粗化結構可以降低出光面之全反射現象,使得出光效率提高;而對於太陽能電池而言,微奈米粗化結構可以造成光線捕捉(Light trapping)效果,以提升光電轉換效率。In general, in order to increase the light extraction efficiency of the light-emitting diode or increase the photoelectric conversion efficiency of the solar cell, the micro-nano roughening structure is mainly formed on the light-emitting surface of the light-emitting diode or the light-incident surface of the solar cell. . Taking the light-emitting diode as an example, the micro-nano roughening structure can reduce the total reflection phenomenon of the light-emitting surface, thereby improving the light-emitting efficiency; and for the solar cell, the micro-nano roughening structure can cause the light trapping effect. To improve the photoelectric conversion efficiency.

上述微奈米粗化結構可由複數個奈米柱所構成,習知普遍係以黃光微影製程(Photolithography process)進行製作,其步驟大致為塗佈光阻於載體表面後,置入烤箱中加熱,使光阻中的溶劑揮發。將光罩置於其上方,於照射紫外線後,再放入烤箱中加熱,使光阻硬化,接續浸泡於顯影液中,去除特定光阻,以曝露下層之特定圖形,對下層曝露之表面進行蝕刻處理,最後浸泡於去光阻液中將光阻去除之。The micro-nano roughening structure may be composed of a plurality of nano-pillars, which are generally produced by a photolithography process, and the steps are generally applied to the surface of the carrier and then placed in an oven for heating. The solvent in the photoresist is volatilized. The photomask is placed on top of it, and after being irradiated with ultraviolet rays, it is heated in an oven to harden the photoresist, and then immersed in the developing solution to remove the specific photoresist to expose the specific pattern of the lower layer to expose the exposed surface of the lower layer. Etching treatment, and finally immersed in the photoresist to remove the photoresist.

上述製程所形成的結構雖然能夠改善反射及折射的現象,然而,其除了具有加工程序繁瑣、高生產成本的問題以外,更會造成微奈米粗化結構均勻度不佳等問題。因此,有必要提供一種新式的微奈米粗化結構之製造方法,以解決上述問題。Although the structure formed by the above process can improve the phenomenon of reflection and refraction, in addition to the problems of cumbersome processing procedures and high production cost, the problem of poor uniformity of the micronized rough structure is caused. Therefore, it is necessary to provide a new method of manufacturing a micro-nano roughening structure to solve the above problems.

有鑑於此,本發明提供一種奈米粗化陣列結構之製造方法,以改進先前技術中所存在的加工程序繁瑣、高生產成本及結構均勻度不佳等相關問題。In view of this, the present invention provides a method for fabricating a nano-roughened array structure to improve related problems such as cumbersome processing procedures, high production cost, and poor structural uniformity existing in the prior art.

為達成本發明之前述目的,本發明提供一種奈米粗化陣列結構之製造方法,其包括下列步驟:在一載體元件層上沉積一介電材料層;在該介電材料層上沉積一金屬薄膜;對該介電材料層、該金屬薄膜以及該載體元件層進行退火處理,以使該金屬薄膜形成複數個金屬球狀部,並且曝露該等金屬球狀部之間的該介電材料層;利用該等金屬球狀部作為遮罩,以對曝露的該介電材料層進行蝕刻直至曝露該載體元件層,以使未曝露的該介電材料層形成一複合柱狀體陣列結構;以及去除該複合柱狀體陣列結構上的該等金屬球狀部,以形成奈米粗化陣列結構。In order to achieve the foregoing object of the present invention, the present invention provides a method of fabricating a nano-roughened array structure comprising the steps of: depositing a layer of dielectric material on a layer of carrier material; depositing a metal on the layer of dielectric material a film; the dielectric material layer, the metal film, and the carrier element layer are annealed to form the metal film into a plurality of metal spherical portions, and exposing the dielectric material layer between the metal spherical portions Using the metal spherical portions as a mask to etch the exposed dielectric material layer until the carrier element layer is exposed such that the unexposed dielectric material layer forms a composite columnar array structure; The metal spheroids on the composite columnar array structure are removed to form a nano-roughened array structure.

在本發明的一實施例中,該介電材料係選自於二氧化矽及氮化矽所組成的族群。In an embodiment of the invention, the dielectric material is selected from the group consisting of cerium oxide and cerium nitride.

在本發明的一實施例中,該金屬係選自於銀、金、鎳、鎂、鋁、鋅、鉻、鐵、錫、鉛、銅、鉑、鈷及鈦所組成的族群。In an embodiment of the invention, the metal is selected from the group consisting of silver, gold, nickel, magnesium, aluminum, zinc, chromium, iron, tin, lead, copper, platinum, cobalt, and titanium.

在本發明的一實施例中,該退火處理步驟的溫度範圍介於250℃至310℃之間。In an embodiment of the invention, the temperature of the annealing step ranges from 250 ° C to 310 ° C.

在本發明的一實施例中,該退火處理步驟的加溫時間範圍介於1分鐘至30分鐘之間。In an embodiment of the invention, the annealing time of the annealing step ranges from 1 minute to 30 minutes.

在本發明的一實施例中,其中每一該等金屬球狀部的直徑介於10 nm至250 nm之間,較佳係介於100 nm至200 nm之間。In an embodiment of the invention, each of the metal spheres has a diameter between 10 nm and 250 nm, preferably between 100 nm and 200 nm.

在本發明的一實施例中,該奈米粗化陣列結構包含奈米柱陣列結構或奈米凹凸結構。In an embodiment of the invention, the nano-roughened array structure comprises a nano-pillar array structure or a nano-convex structure.

在本發明的一實施例中,其中該奈米柱陣列結構的每一該等奈米柱的直徑介於10 nm至250 nm之間,較佳係介於100 nm至200 nm之間。In an embodiment of the invention, each of the nano columns of the nano-pillar array structure has a diameter between 10 nm and 250 nm, preferably between 100 nm and 200 nm.

再者,本發明另提供一種奈米粗化陣列結構之製造方法,其包括下列步驟:在一載體元件層上沉積一金屬薄膜;對沉積有該金屬薄膜之該載體元件層進行退火處理,以使該金屬薄膜形成複數個金屬球狀部,並且曝露該等金屬球狀部之間的該載體元件層;利用該等金屬球狀部作為遮罩,以對曝露的該載體元件層進行蝕刻直至該載體元件層的表面產生高低差,以使該載體元件層的表面形成一複合柱狀體陣列結構;以及去除該複合柱狀體陣列結構上的該等金屬球狀部,以形成奈米粗化陣列結構。Furthermore, the present invention further provides a method for fabricating a nano-roughened array structure, comprising the steps of: depositing a metal thin film on a carrier element layer; annealing the carrier element layer on which the metal thin film is deposited, Forming a plurality of metal spherical portions on the metal thin film and exposing the carrier element layer between the metal spherical portions; using the metal spherical portions as a mask to etch the exposed carrier element layer until a surface of the carrier element layer is formed with a height difference such that a surface of the carrier element layer forms a composite columnar array structure; and the metal spherical portions on the composite columnar array structure are removed to form a nano-rough Array structure.

相較於先前技術,本發明具有明顯的優點和優益的功效。藉由上述技術手段,本發明的奈米粗化陣列結構之製造方法至少具有下列優點及功效:本發明係藉由對沉積有金屬薄膜及介電材料層之載體元件層進行退火處理所形成的複數個金屬球狀部作為後續蝕刻製程使用的遮罩,從而於該載體元件層之表面形成奈米粗化陣列結構。本發明除了具有加工程序簡易以外,更具有結構均勻度及穩定度佳之優勢,從而降低生產成本。Compared to the prior art, the present invention has significant advantages and advantageous effects. By the above technical means, the method for fabricating the nano-roughened array structure of the present invention has at least the following advantages and effects: the present invention is formed by annealing a carrier element layer on which a metal thin film and a dielectric material layer are deposited. A plurality of metal spherical portions are used as masks for the subsequent etching process to form a nano-roughened array structure on the surface of the carrier element layer. In addition to the simple processing procedure, the invention has the advantages of good structural uniformity and good stability, thereby reducing production costs.

為詳細說明本發明之技術內容、構造特徵、所達成目的及功效,以下茲舉例並配合圖式詳予說明。In order to explain the technical content, structural features, objectives and effects of the present invention in detail, the following detailed description is given by way of example.

請參閱第1圖及第2a圖至第2d圖,其係為本發明實施例中奈米粗化陣列結構之製造方法的步驟流程圖及其立體圖,其中第2b圖的箭頭係代表在具有複數個金屬球狀部30a之介電材料層20的表面21施以蝕刻處理,該製造方法包括下列步驟:Please refer to FIG. 1 and FIG. 2a to FIG. 2d, which are flowcharts and a perspective view of a method for manufacturing a nano-roughened array structure according to an embodiment of the present invention, wherein the arrow diagram of FIG. 2b represents a complex number. The surface 21 of the dielectric material layer 20 of the metal spherical portion 30a is subjected to an etching process, and the manufacturing method includes the following steps:

在步驟S11中,在一載體元件層10上沉積介電材料層20。在一實施例中,載體元件層10係為太陽能電池或發光二極體之結構中的透明導電氧化物(Transparent Conductive Oxide,TCO)薄膜,例如氧化銦錫(Indium Tin Oxide,ITO)薄膜。該介電材料層20的介電材料係選自於二氧化矽(SiO2 )及氮化矽(SiN)所組成的族群。其中沉積介電材料層20的方法包括電子束蒸鍍法、電漿化學氣相沉積法及濺鍍法等,該介電材料層20的厚度介於300奈米(nm)至600 nm之間,較佳係介於400 nm至500 nm之間,其最佳厚度的定義係依奈米粗化陣列結構之設計需求,或依蝕刻技術可蝕刻的厚度範圍定義之。In step S11, a layer of dielectric material 20 is deposited on a layer of carrier element 10. In one embodiment, the carrier element layer 10 is a transparent conductive oxide (TCO) film, such as an Indium Tin Oxide (ITO) film, in the structure of a solar cell or a light emitting diode. The dielectric material of the dielectric material layer 20 is selected from the group consisting of cerium oxide (SiO 2 ) and cerium nitride (SiN). The method for depositing the dielectric material layer 20 includes electron beam evaporation, plasma chemical vapor deposition, sputtering, etc., and the thickness of the dielectric material layer 20 is between 300 nm (nm) and 600 nm. Preferably, the system is between 400 nm and 500 nm, and the definition of the optimum thickness is defined by the design requirements of the inelized roughened array structure or the thickness range etchable by the etching technique.

在步驟S12中,在該介電材料層20上沉積金屬薄膜30。該金屬薄膜30的沉積方法係利用電子束蒸鍍法將金屬蒸發成氣態,並附著在介電材料層20上,形成具有良好附著性之金屬薄膜30,其厚度範圍介於10 nm至30 nm之間。其中,該金屬係選自於銀、金、鎳、鎂、鋁、鋅、鉻、鐵、錫、鉛、銅、鉑、鈷及鈦所組成的族群。In step S12, a metal thin film 30 is deposited on the dielectric material layer 20. The method for depositing the metal thin film 30 is to evaporate the metal into a gaseous state by electron beam evaporation, and adhere to the dielectric material layer 20 to form a metal film 30 having good adhesion ranging from 10 nm to 30 nm. between. The metal is selected from the group consisting of silver, gold, nickel, magnesium, aluminum, zinc, chromium, iron, tin, lead, copper, platinum, cobalt, and titanium.

在步驟S13中,對沉積有該介電材料層20及該金屬薄膜30的該載體元件層10進行退火處理,金屬薄膜30會因內聚力而自行凝聚成複數個金屬球狀部30a,並且曝露該等金屬球狀部之間的該介電材料層。該金屬球狀部30a的形成方式如第3a圖至第3c圖所示,前述退火處理係將金屬薄膜30加溫到高於再結晶溫度的一特定溫度並且維持此特定溫度一段時間,再將其緩慢冷卻,此時,第3a圖中的金屬薄膜30會因內聚力而逐漸變形成第3b圖中的金屬薄膜30,且自行凝聚成複數個金屬球狀部30a,故其條件主要包含溫度及加溫時間,溫度範圍係介於250℃至310℃之間;加溫時間範圍則係介於1分鐘至30分鐘之間。而自行凝聚成複數個金屬球狀部30a,其中每一金屬球狀部30a的直徑介於10 nm至250 nm之間,較佳係介於100 nm至200 nm之間。In step S13, the carrier element layer 10 on which the dielectric material layer 20 and the metal thin film 30 are deposited is annealed, and the metal thin film 30 is self-condensed into a plurality of metal spherical portions 30a due to cohesive force, and exposed. The layer of dielectric material between the metal spheres. The metal spherical portion 30a is formed in a manner as shown in FIGS. 3a to 3c. The annealing treatment heats the metal thin film 30 to a specific temperature higher than the recrystallization temperature and maintains the specific temperature for a while, and then The metal film 30 in FIG. 3a is gradually deformed into the metal thin film 30 in FIG. 3b due to the cohesive force, and is self-aggregated into a plurality of metal spherical portions 30a, so that the conditions mainly include temperature and During the heating time, the temperature range is between 250 ° C and 310 ° C; the heating time range is between 1 minute and 30 minutes. The self-condensed into a plurality of metal spherical portions 30a each having a diameter of between 10 nm and 250 nm, preferably between 100 nm and 200 nm.

在步驟S14中,利用該等金屬球狀部30a作為遮罩,以對曝露的該介電材料層20的表面21進行蝕刻直至曝露該載體元件層10,以使未曝露的該介電材料層20形成複合柱狀體陣列結構40。該等金屬球狀部30a作為遮罩,其在蝕刻過程中用以阻隔蝕刻對該等金屬球狀部30a下方的該介電材料層20之侵蝕,用以保留該等金屬球狀部30a下方的該介電材料層20。該蝕刻的方法係包括使用反應式離子蝕刻法(Reactive Ion Etching,RIE)及化學濕式蝕刻法(Chemical wet etching)其中之一者。In step S14, the metal spherical portions 30a are used as masks to etch the exposed surface 21 of the dielectric material layer 20 until the carrier element layer 10 is exposed to expose the unexposed dielectric material layer. 20 forms a composite columnar array structure 40. The metal spherical portions 30a serve as masks for resisting etching of the dielectric material layer 20 under the metal spherical portions 30a during etching to retain the metal spherical portions 30a. The layer of dielectric material 20 is. The etching method includes one of reactive ion etching (RIE) and chemical wet etching.

在步驟S15中,去除該複合柱狀體陣列結構40上的金屬球狀部30a,以形成奈米粗化陣列結構20a。該去除的方法係將複合柱狀體陣列結構40浸泡於酸性溶液中,以溶解該等金屬球狀部30a,其中該酸性溶液包含硝酸、鹽酸、硫酸、氫氟酸、過氯酸或其組合之酸性溶液。於此,各金屬元素係僅溶解於特定之酸性溶液中。前述所形成之奈米粗化陣列結構包含奈米柱陣列結構或奈米凹凸結構,其中該奈米柱陣列結構的每一該等奈米柱的直徑介於10 nm至250 nm之間,較佳係介於100 nm至200 nm之間。In step S15, the metal spherical portion 30a on the composite columnar array structure 40 is removed to form a nano-roughened array structure 20a. The removal method is to immerse the composite columnar array structure 40 in an acidic solution to dissolve the metal spherical portions 30a, wherein the acidic solution comprises nitric acid, hydrochloric acid, sulfuric acid, hydrofluoric acid, perchloric acid or a combination thereof. An acidic solution. Here, each metal element is dissolved only in a specific acidic solution. The nano-roughened array structure formed by the foregoing comprises a nano-pillar array structure or a nano-convex structure, wherein each of the nano-columns of the nano-column array structure has a diameter between 10 nm and 250 nm, The best is between 100 nm and 200 nm.

依上述實施例之製造方法,以金屬銀作為舉例對象,本發明提出下列具體實施方式:首先在一太陽能電池的氧化銦錫薄膜上以電子束蒸鍍機沉積一厚度約500 nm之二氧化矽層,而後於該二氧化矽層之上再以電子束蒸鍍機沉積一厚度約30 nm之銀薄膜。接續將沉積有該二氧化矽層及該銀薄膜之太陽能電池置入於爐管中,並以3分鐘300℃之條件執行退火處理,此時銀薄膜會因內聚力而自行凝聚成複數個奈米銀球狀物,且同時曝露該等奈米銀球狀物之間的二氧化矽層。以該等奈米銀球狀物作為遮罩,且對曝露的該二氧化矽層的表面進行反應式離子蝕刻,形成具有奈米銀球狀物之複合柱狀體陣列結構。最後浸泡於硝酸中,去除該複合柱狀體陣列結構上的該等奈米銀球狀物,以形成奈米粗化陣列結構。According to the manufacturing method of the above embodiment, metal silver is taken as an example, and the present invention proposes the following specific embodiments: first, a cerium oxide having a thickness of about 500 nm is deposited by an electron beam evaporation machine on an indium tin oxide film of a solar cell. A layer, and then a silver film having a thickness of about 30 nm is deposited on the ceria layer by an electron beam evaporation machine. Next, the solar cell in which the cerium oxide layer and the silver thin film are deposited is placed in a furnace tube, and annealing treatment is performed at 300 ° C for 3 minutes, at which time the silver film is self-condensed into a plurality of nanoparticles due to cohesive force. Silver spheres and simultaneously exposed to the ceria layer between the nano silver spheres. The nano silver spheres are used as a mask, and the surface of the exposed ceria layer is subjected to reactive ion etching to form a composite columnar array structure having nano silver spheres. Finally, the nano silver spheres on the composite columnar array structure are removed by immersion in nitric acid to form a nano-roughened array structure.

如上所述,本發明奈米粗化陣列結構之製造方法係藉由對沉積有金屬薄膜及介電材料層之載體元件層進行退火處理,該金屬薄膜會因內聚力而自行凝聚成複數個金屬球狀部,並以該等金屬球狀部作為一遮罩,接續對具有該等金屬球狀部之該介電材料層進行蝕刻,從而於該載體元件層之表面形成奈米粗化陣列結構。本發明除了具有加工程序簡易以外,更具有結構均勻度及穩定度佳之優勢,從而降低生產成本。As described above, the nano-roughening array structure of the present invention is formed by annealing a carrier element layer on which a metal thin film and a dielectric material layer are deposited, and the metal thin film is self-condensed into a plurality of metal balls due to cohesive force. And the metal spherical portion is used as a mask, and the dielectric material layer having the metal spherical portions is etched to form a nano-roughened array structure on the surface of the carrier element layer. In addition to the simple processing procedure, the invention has the advantages of good structural uniformity and good stability, thereby reducing production costs.

雖然本發明已用較佳實施例揭露如上,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

10‧‧‧載體元件層10‧‧‧ Carrier element layer

20‧‧‧介電材料層20‧‧‧ dielectric material layer

20a‧‧‧奈米粗化陣列結構20a‧‧‧Nean roughening array structure

21‧‧‧表面21‧‧‧ surface

30‧‧‧金屬薄膜30‧‧‧Metal film

30a‧‧‧金屬球狀部30a‧‧‧Metal Sphere

40‧‧‧複合柱狀體陣列結構40‧‧‧Composite columnar array structure

S11~S15‧‧‧步驟S11~S15‧‧‧Steps

第1圖為本發明實施例中奈米粗化陣列結構之製造方法的步驟流程圖。1 is a flow chart showing the steps of a method for fabricating a nano-roughened array structure according to an embodiment of the present invention.

第2a圖為本發明實施例中奈米粗化陣列結構的一實施方式之第一流程的立體圖。2a is a perspective view showing a first flow of an embodiment of a nano-roughened array structure in the embodiment of the present invention.

第2b圖為本發明實施例中奈米粗化陣列結構的一實施方式之第二流程的立體圖。Figure 2b is a perspective view showing a second flow of an embodiment of the nano-roughened array structure in the embodiment of the present invention.

第2c圖為本發明實施例中奈米粗化陣列結構的一實施方式之第三流程的立體圖。2c is a perspective view showing a third flow of an embodiment of the nano-roughened array structure in the embodiment of the present invention.

第2d圖為本發明實施例中奈米粗化陣列結構的一實施方式之第四流程的立體圖。Fig. 2d is a perspective view showing a fourth flow of an embodiment of the nano-roughened array structure in the embodiment of the present invention.

第3a圖為本發明實施例中沿第2a圖之A-A’剖面線所取之剖視圖。Fig. 3a is a cross-sectional view taken along line A-A' of Fig. 2a in the embodiment of the invention.

第3b圖為本發明實施例中第2a圖至第2b圖其金屬薄膜自行凝聚成複數個金屬球狀部的變化過程之剖視圖。Fig. 3b is a cross-sectional view showing a process in which the metal thin films themselves agglomerate into a plurality of metal spherical portions in Figs. 2a to 2b in the embodiment of the present invention.

第3c圖為本發明實施例中沿第2b圖之B-B’剖面線所取之剖視圖。Fig. 3c is a cross-sectional view taken along line B-B' of Fig. 2b in the embodiment of the present invention.

S11~S15...步驟S11~S15. . . step

Claims (14)

一種奈米粗化陣列結構的製造方法,包括下列步驟:形成太陽能電池的透明導電氧化物薄膜或發光二極體的透明導電氧化物薄膜以作為一載體元件層;在該載體元件層上沉積一介電材料層;在該介電材料層上沉積一金屬薄膜;對該介電材料層、該金屬薄膜以及該具透明導電氧化物薄膜之載體元件層在溫度範圍介於250℃至310℃之間進行退火處理,以使該金屬薄膜形成複數個金屬球狀部,並且曝露該等金屬球狀部之間的該介電材料層;利用該等金屬球狀部作為遮罩,以對曝露的該介電材料層進行蝕刻直至曝露該載體元件層,以使未曝露的該介電材料層形成一複合柱狀體陣列結構;以及去除該複合柱狀體陣列結構上的該等金屬球狀部,以形成奈米粗化陣列結構。 A method for fabricating a nano-roughened array structure, comprising the steps of: forming a transparent conductive oxide film of a solar cell or a transparent conductive oxide film of a light-emitting diode as a carrier element layer; depositing a layer on the carrier element layer a dielectric material layer; depositing a metal film on the dielectric material layer; the dielectric material layer, the metal film, and the carrier element layer having the transparent conductive oxide film at a temperature ranging from 250 ° C to 310 ° C Annealing treatment to form a plurality of metal spherical portions of the metal thin film and exposing the dielectric material layer between the metal spherical portions; using the metal spherical portions as a mask to expose the exposed The dielectric material layer is etched until the carrier element layer is exposed such that the unexposed dielectric material layer forms a composite columnar array structure; and the metal spheroids on the composite columnar array structure are removed To form a nano-roughened array structure. 如申請專利範圍第1項所述之製造方法,其中該介電材料係選自於二氧化矽及氮化矽所組成的族群。 The manufacturing method according to claim 1, wherein the dielectric material is selected from the group consisting of cerium oxide and cerium nitride. 如申請專利範圍第1項所述之製造方法,其中該金屬係選自於銀、金、鎳、鎂、鋁、鋅、鉻、鐵、錫、鉛、銅、鉑、鈷 及鈦所組成的族群。 The manufacturing method of claim 1, wherein the metal is selected from the group consisting of silver, gold, nickel, magnesium, aluminum, zinc, chromium, iron, tin, lead, copper, platinum, cobalt. And the group of titanium. 如申請專利範圍第1項所述之製造 方法,其中該介電材料層的沉積步驟係選自於電子束蒸鍍法、電漿化學氣相沉積法及濺鍍法所組成的族群。 Manufacturing as described in claim 1 The method wherein the step of depositing the layer of dielectric material is selected from the group consisting of electron beam evaporation, plasma chemical vapor deposition, and sputtering. 如申請專利範圍第1項所述之製造方法,其中該金屬薄膜的沉積步驟包括使用電子束蒸鍍法。 The manufacturing method according to claim 1, wherein the step of depositing the metal thin film comprises using an electron beam evaporation method. 如申請專利範圍第1項所述之製造方法,其中該退火處理步驟的加溫時間範圍介於1分鐘至30分鐘之間。 The manufacturing method of claim 1, wherein the annealing step has a heating time ranging from 1 minute to 30 minutes. 如申請專利範圍第1項所述之製造方法,其中每一該等金屬球狀部的直徑介於10奈米(nm)至250nm之間。 The manufacturing method of claim 1, wherein each of the metal spherical portions has a diameter of between 10 nanometers (nm) and 250 nm. 如申請專利範圍第7項所述之製造方法,其中每一該等金屬球狀部的直徑介於100nm至200nm之間。 The manufacturing method of claim 7, wherein each of the metal spherical portions has a diameter of between 100 nm and 200 nm. 如申請專利範圍第1項所述之製造方法,其中對曝露的該介電材料層進行蝕刻的步驟中,係包括使用反應式離子蝕刻法及化學濕式蝕刻法其中之一者。 The manufacturing method according to claim 1, wherein the step of etching the exposed dielectric material layer comprises using one of a reactive ion etching method and a chemical wet etching method. 如申請專利範圍第1項所述之製造方法,其中去除該複合柱狀體陣列結構上的該等金屬球狀部的步驟中,係將該複合柱狀體陣列結構浸泡於酸性溶液中,以溶解該等金屬球狀部。 The manufacturing method according to claim 1, wherein in the step of removing the metal spherical portions on the composite columnar array structure, the composite columnar array structure is immersed in an acidic solution to Dissolving the metal spheres. 如申請專利範圍第1項所述之製造方法,其中該奈米粗化陣列結構包含奈米柱陣列結構或奈米凹凸結構。 The manufacturing method of claim 1, wherein the nano-roughened array structure comprises a nano-pillar array structure or a nano-convex structure. 如申請專利範圍第11項所述之製造方法,其中該奈米柱陣列結構的每一該等奈米柱的直徑介於10nm至250nm之間。 The manufacturing method of claim 11, wherein each of the nano columns of the nano-pillar array structure has a diameter of between 10 nm and 250 nm. 如申請專利範圍第12項所述之製造方法,其中該奈米柱陣列結構的每一該等奈米柱的直徑介於100nm至200nm之間。 The manufacturing method of claim 12, wherein each of the nano columns of the nano-pillar array structure has a diameter of between 100 nm and 200 nm. 一種奈米粗化陣列結構的製造方法,包括下列步驟:形成太陽能電池的透明導電氧化物薄膜或發光二極體的透明導電氧化物薄膜以作為一載體元件層;在該載體元件層上沉積一金屬薄膜;對沉積有該金屬薄膜之該具透明導電氧化物薄膜之載體元件層在溫度範圍介於250℃至310℃之間進行退火處理,以使該金屬薄膜形成複數個金屬球狀部,並且曝露該等金屬球狀部之間的該載體元件層;利用該等金屬球狀部作為遮罩,以對曝露的該載體元件層進行蝕刻直至該載體元件層的表面產生高低差,以使該載體元件層的表面形成一複合柱狀體陣列結構;以及去除該複合柱狀體陣列結構上的該等金屬球狀部,以形成奈米粗化陣列結構。 A method for fabricating a nano-roughened array structure, comprising the steps of: forming a transparent conductive oxide film of a solar cell or a transparent conductive oxide film of a light-emitting diode as a carrier element layer; depositing a layer on the carrier element layer a metal thin film; the carrier element layer with the transparent conductive oxide film deposited on the metal film is annealed at a temperature ranging from 250 ° C to 310 ° C to form the metal thin film into a plurality of metal spherical portions, And exposing the carrier element layer between the metal spherical portions; using the metal spherical portions as a mask to etch the exposed carrier element layer until a height difference is generated on the surface of the carrier element layer, so that The surface of the carrier element layer forms a composite columnar array structure; and the metal spheroids on the composite columnar array structure are removed to form a nano-roughened array structure.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201117401A (en) * 2009-06-08 2011-05-16 Ibm Nano/microwire solar cell fabricated by nano/microsphere lithography
TW201130732A (en) * 2010-03-03 2011-09-16 Huang-Chung Cheng Method for fabricating nano-structure and application thereof to three-dimensional structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201117401A (en) * 2009-06-08 2011-05-16 Ibm Nano/microwire solar cell fabricated by nano/microsphere lithography
TW201130732A (en) * 2010-03-03 2011-09-16 Huang-Chung Cheng Method for fabricating nano-structure and application thereof to three-dimensional structure

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
翁紹蘭,"奈米球微影術製備大面積二維金屬矽化物、矽鍺化物奈米點陣列及規則奈米結構之研究",國立中央大學碩士論文,2009年01月06日 *
詹宗穎,"利用奈米圖型化基板製作高效率氮化鎵發光二極體",國立交通大學碩士論文,2011年01月12日 *
黃泓文,"奈米製程技術在氮化鎵相關發光元件之研究",國立交通大學博士論文,2008年08月06日 *

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