TWI462252B - Quad flat no-lead package - Google Patents
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- TWI462252B TWI462252B TW098101388A TW98101388A TWI462252B TW I462252 B TWI462252 B TW I462252B TW 098101388 A TW098101388 A TW 098101388A TW 98101388 A TW98101388 A TW 98101388A TW I462252 B TWI462252 B TW I462252B
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L2924/3025—Electromagnetic shielding
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Description
本發明是有關於一種晶片封裝，且特別是有關於一種四方扁平無引腳(Quad Flat Non-leaded，QFN)封裝。This invention relates to a chip package, and more particularly to a quad flat Non-leaded (QFN) package.
隨著半導體工業的高度發展，電子及半導體裝置廣泛地被應用於日常生活中，如娛樂、教育、交通運輸及家電用品等方面。電子產品朝向設計複雜、尺寸小、重量輕及人性化方面發展，以帶給使用者更多的方便。在封裝結構中，導線架是常用的元件之一且應用於多種封裝產品。以導線架的類型而言，四方扁平封裝(Quad Flat Package，QFP)可分為I型接腳之四方扁平封裝(quad flat package with”I”lead，QFI)、J型接腳之四方扁平晶片封裝(quad flat package with”J”lead，QFJ)及四方扁平無引腳(Quad Flat Non-leaded，QFN)封裝。四方扁平無引腳封裝之導線架的引腳不超出封裝結構的邊緣，故其具有較小的體積。此外，四方扁平無引腳封裝具有較短的訊號傳遞路徑及較快之訊號傳遞速度，因此一直是低腳位(low pin count)構裝型態的主流之一。With the rapid development of the semiconductor industry, electronic and semiconductor devices are widely used in daily life, such as entertainment, education, transportation, and home appliances. Electronic products are developed in terms of complex design, small size, light weight and humanity, so as to bring more convenience to users. In package structures, leadframes are one of the commonly used components and are used in a variety of packaged products. In terms of the type of lead frame, the Quad Flat Package (QFP) can be divided into quad flat package with "I" lead (QFI) and J-type flat chip. Quad flat package with "J" lead, QFJ) and Quad Flat Non-leaded (QFN) package. The lead frame of the quad flat no-lead package does not exceed the edge of the package structure, so it has a small volume. In addition, the quad flat no-lead package has a short signal transmission path and a fast signal transmission speed, so it has always been one of the mainstream of the low pin count configuration.
一般而言，在四方扁平無引腳封裝的製造過程中，會將多個晶片配置於導線架上，其中導線架包括多個相互連接的引腳組，且各晶片被一引腳組所環繞。各晶片透過打線製程電性連接於一引腳組。接著，形成用以包覆導線架、晶片及焊線的一封裝膠體。最後，透過單體化製程形成多個四方扁平無引腳封裝。Generally, in the manufacturing process of a quad flat no-lead package, a plurality of wafers are disposed on a lead frame, wherein the lead frame includes a plurality of interconnected pin groups, and each wafer is surrounded by a pin group. . Each wafer is electrically connected to a pin group through a wire bonding process. Next, an encapsulant for covering the lead frame, the wafer, and the bonding wire is formed. Finally, a plurality of quad flat no-lead packages are formed through the singulation process.
本發明提供一種四方扁平無引腳封裝，其具有較小的厚度。The present invention provides a quad flat no-lead package that has a small thickness.
本發明提出一種四方扁平無引腳封裝，包括一圖案化導電層、一第一焊罩層、一晶片、多條焊線及一封裝膠體。圖案化導電層具有一表面。第一焊罩層配置於表面，其中第一焊罩層暴露出部分表面。晶片配置於第一焊罩層，其中第一焊罩層位於圖案化導電層及晶片之間。焊線電性連接於晶片及第一焊罩層暴露出的圖案化導電層。封裝膠體包覆圖案化導電層、第一焊罩層、晶片及焊線。The invention provides a quad flat no-lead package comprising a patterned conductive layer, a first solder mask layer, a wafer, a plurality of bonding wires and an encapsulant. The patterned conductive layer has a surface. The first shroud layer is disposed on the surface, wherein the first shroud layer exposes a portion of the surface. The wafer is disposed on the first solder mask layer, wherein the first solder mask layer is between the patterned conductive layer and the wafer. The bonding wire is electrically connected to the wafer and the patterned conductive layer exposed by the first solder mask layer. The encapsulant encapsulates the patterned conductive layer, the first solder mask layer, the wafer, and the bonding wires.
在本發明之一實施例中，上述之晶片具有一主動表面、相對主動表面的一背面及配置於主動表面的多個焊墊，且晶片的背面與第一焊罩層接觸。In one embodiment of the invention, the wafer has an active surface, a back surface opposite the active surface, and a plurality of pads disposed on the active surface, and the back side of the wafer is in contact with the first solder mask layer.
在本發明之一實施例中，上述之四方扁平無引腳封裝更包括一黏著層，配置於第一焊罩層及晶片之間。In an embodiment of the invention, the quad flat no-lead package further includes an adhesive layer disposed between the first solder mask layer and the wafer.
本發明提出一種四方扁平無引腳封裝，包括一圖案化導電層、一第一焊罩、一晶片、多條焊線及一封裝膠體。圖案化導電層具有一表面。第一焊罩層配置於表面，其中第一焊罩層暴露出部分表面。晶片配置於第一焊罩層暴露出的部分表面。焊線電性連接於晶片及第一焊罩層暴露出的圖案化導電層。封裝膠體包覆圖案化導電層、第一焊罩層、晶片及焊線。The invention provides a quad flat no-lead package comprising a patterned conductive layer, a first solder mask, a wafer, a plurality of bonding wires and an encapsulant. The patterned conductive layer has a surface. The first shroud layer is disposed on the surface, wherein the first shroud layer exposes a portion of the surface. The wafer is disposed on a portion of the surface exposed by the first solder mask layer. The bonding wire is electrically connected to the wafer and the patterned conductive layer exposed by the first solder mask layer. The encapsulant encapsulates the patterned conductive layer, the first solder mask layer, the wafer, and the bonding wires.
在本發明之一實施例中，上述之圖案化導電層包括一晶片座及圍繞晶片座的多個引腳。In one embodiment of the invention, the patterned conductive layer includes a wafer holder and a plurality of leads surrounding the wafer holder.
在本發明之一實施例中，上述之第一焊罩層從圖案化導電層的表面延伸至晶片座及引腳之間的區域。In one embodiment of the invention, the first solder mask layer extends from the surface of the patterned conductive layer to a region between the wafer holder and the leads.
在本發明之一實施例中，上述之四方扁平無引腳封裝更包括一第二焊罩層，配置於晶片座及引腳之間。In an embodiment of the invention, the quad flat no-lead package further includes a second solder mask layer disposed between the wafer holder and the lead.
在本發明之一實施例中，上述之第二焊罩層不與第一焊罩層接觸。In an embodiment of the invention, the second solder mask layer is not in contact with the first solder mask layer.
在本發明之一實施例中，上述之晶片具有一主動表面、相對主動表面的一背面及配置於主動表面的多個焊墊，且晶片的背面與圖案化導電層的第一表面接觸。In one embodiment of the invention, the wafer has an active surface, a back surface opposite the active surface, and a plurality of pads disposed on the active surface, and the back surface of the wafer is in contact with the first surface of the patterned conductive layer.
在本發明之一實施例中，上述之四方扁平無引腳封裝更包括一黏著層，配置於圖案化導電層及晶片之間。In an embodiment of the invention, the quad flat no-lead package further includes an adhesive layer disposed between the patterned conductive layer and the wafer.
在本發明之一實施例中，上述之黏著層包括一B階黏著層。In an embodiment of the invention, the adhesive layer comprises a B-stage adhesive layer.
基於上述，本發明的四方扁平無引腳封裝具有用以強化其結構強度的焊罩層，以使得圖案化導電層可具有較小的厚度。Based on the above, the quad flat no-lead package of the present invention has a solder mask layer for enhancing its structural strength such that the patterned conductive layer can have a small thickness.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1G為本發明第一實施例之四方扁平無引腳封裝的製程剖視流程圖。請參考圖1A，提供具有一第一表面112及一第二表面114的導電層110。接著，部分地移除位於預定區域之導電層110，以在導電層110的第一表面112上形成多個凹槽R。在本實施例中，是透過半蝕刻(half-etching)製程形成凹槽R。1A to 1G are cross-sectional views showing a process of a quad flat no-lead package according to a first embodiment of the present invention. Referring to FIG. 1A, a conductive layer 110 having a first surface 112 and a second surface 114 is provided. Next, the conductive layer 110 located in the predetermined region is partially removed to form a plurality of grooves R on the first surface 112 of the conductive layer 110. In the present embodiment, the groove R is formed by a half-etching process.
請參考圖1B，形成一第一焊罩層120以完全覆蓋導電層110的第一表面112，以使得形成於導電層110的第一表面112之凹槽R被第一焊罩層120所填滿。在一較佳實施例中，更可在導電層110上進行棕化(brown oxidation)處理或黑化(black oxidation)處理，以增加導電層110之表面粗度，進而提升導電層110與第一焊罩層120之間的結合力。Referring to FIG. 1B, a first solder mask layer 120 is formed to completely cover the first surface 112 of the conductive layer 110 such that the recess R formed on the first surface 112 of the conductive layer 110 is filled by the first solder mask layer 120. full. In a preferred embodiment, a brown oxidation process or a black oxidation process may be performed on the conductive layer 110 to increase the surface roughness of the conductive layer 110, thereby improving the conductive layer 110 and the first layer. The bonding force between the solder mask layers 120.
接著，請參考圖1C，對第一焊罩層120進行圖案化以形成多個第一開口122，其中第一開口122暴露出部分第一表面112。換言之，形成於部分第一表面112的第一焊罩層120定義出多個第一焊墊118。Next, referring to FIG. 1C, the first solder mask layer 120 is patterned to form a plurality of first openings 122, wherein the first openings 122 expose a portion of the first surface 112. In other words, the first solder mask layer 120 formed on a portion of the first surface 112 defines a plurality of first pads 118.
在本實施例中，第一焊罩層120可為一固態狀焊罩膜，且第一開口122在第一焊罩層120被貼附於導電層110之前或之後被形成。在一可選擇的實施例中，可將一液態焊罩塗層塗佈在導電層110的第一表面112上，並將其固化及圖案化以形成第一焊罩層120。在本實施例中，第一焊罩層120例如是一感光B階膜(photosensitive B-staged film)。In the present embodiment, the first solder mask layer 120 may be a solid solder mask film, and the first opening 122 is formed before or after the first solder mask layer 120 is attached to the conductive layer 110. In an alternative embodiment, a liquid solder mask coating can be applied over the first surface 112 of the conductive layer 110 and cured and patterned to form the first solder mask layer 120. In the embodiment, the first solder mask layer 120 is, for example, a photosensitive B-staged film.
此外，在一較佳實施例中，可透過電鍍(plating)製程在第一焊墊118上形成一電鍍導電層(未繪示)。電鍍導電層可為鎳金疊層或其它適用的金屬層。值得注意的是，可在第一焊罩層120形成於導電層110之前或之後形成電鍍導電層。In addition, in a preferred embodiment, a plating conductive layer (not shown) may be formed on the first pad 118 through a plating process. The electroplated conductive layer can be a nickel gold laminate or other suitable metal layer. It is to be noted that the electroplated conductive layer may be formed before or after the first solder mask layer 120 is formed on the conductive layer 110.
請參考圖1D，將多個晶片130黏著於第一焊罩層120，接著並形成多條焊線150以電性連接晶片130及導電層110，其中各晶片130具有一主動表面132、相對主動表面132的一背面134及配置於主動表面132的多個第二焊墊136。各晶片130透過位於晶片130及導電層110之間的一黏著層140而黏著於第一焊罩層120，以使得第一焊罩層120位於導電層110及各晶片130之間。Referring to FIG. 1D, a plurality of wafers 130 are adhered to the first solder mask layer 120, and then a plurality of bonding wires 150 are formed to electrically connect the wafer 130 and the conductive layer 110. Each of the wafers 130 has an active surface 132 and is relatively active. A back surface 134 of the surface 132 and a plurality of second pads 136 disposed on the active surface 132. Each of the wafers 130 is adhered to the first solder mask layer 120 through an adhesive layer 140 between the wafer 130 and the conductive layer 110 such that the first solder mask layer 120 is located between the conductive layer 110 and each of the wafers 130.
在本實施例中，可透過打線(wire bonding)製程形成焊線150，以使得各焊線150電性連接於一第一焊墊118及一第二焊墊136之間。焊線150例如是金線。In this embodiment, the bonding wires 150 are formed through a wire bonding process such that the bonding wires 150 are electrically connected between a first bonding pad 118 and a second bonding pad 136. The bonding wire 150 is, for example, a gold wire.
在本實施中，黏著層140例如是一B階黏著層(B-staged adhesive layer)。B階黏著層140可為ABLESTIK的8008、8008HT、6200、6201、6202C或HITACHI Chemical CO., Ltd.提供的SA-200-6、SA-200-10。在本發明之一實施例中，B階黏著層140是被形成於一晶圓的背面。在切割晶圓之後可得到具有位於背面134之黏著層140的多個晶片130。因此，B階黏著層140適於大量生產。此外，可透過旋塗、印刷或其它適用的製程以形成B階黏著層140。黏著層140係預先被形成於晶片130的背面134。特別的是，可先提供具有陣列地排列之多個晶片130的一晶圓。接著，在晶片130的背面134形成一二階黏著層，並透過加熱(heating)或紫外線照射(UV irradiation)將其部分固化，以形成B階黏著層140。此外，亦可在晶片130被貼附於第一焊罩層120之前，在第一焊罩層120上形成B階黏著層140。In the present embodiment, the adhesive layer 140 is, for example, a B-staged adhesive layer. The B-stage adhesive layer 140 may be 800-800, 8008 HT, 6200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 supplied by HITACHI Chemical CO., Ltd. In one embodiment of the invention, the B-stage adhesive layer 140 is formed on the back side of a wafer. A plurality of wafers 130 having an adhesive layer 140 on the back side 134 can be obtained after dicing the wafer. Therefore, the B-stage adhesive layer 140 is suitable for mass production. Additionally, the B-stage adhesive layer 140 can be formed by spin coating, printing, or other suitable process. The adhesive layer 140 is formed in advance on the back surface 134 of the wafer 130. In particular, a wafer having a plurality of wafers 130 arranged in an array may be provided first. Next, a second-order adhesive layer is formed on the back surface 134 of the wafer 130, and partially cured by heat or ultraviolet irradiation to form a B-stage adhesive layer 140. In addition, a B-stage adhesive layer 140 may be formed on the first solder mask layer 120 before the wafer 130 is attached to the first solder mask layer 120.
在本實施例中，B階黏著層140是在晶片130被貼附於第一焊罩層120之後完全固化，或在之後透過後固化(post curing)處理而完全固化，或在被封裝膠體160包覆後完全固化。In the present embodiment, the B-stage adhesive layer 140 is completely cured after the wafer 130 is attached to the first solder mask layer 120, or is completely cured by post curing treatment, or in the encapsulated colloid 160. Completely cured after coating.
請參考圖1E，形成包覆導電層110、第一焊罩層120、晶片130及焊線150的一封裝膠體160。封裝膠體160的材質例如是環氧樹脂(epoxy resin)。Referring to FIG. 1E, an encapsulant 160 that encapsulates the conductive layer 110, the first solder mask layer 120, the wafer 130, and the bonding wires 150 is formed. The material of the encapsulant 160 is, for example, an epoxy resin.
請參考圖1F，對導電層110的第二表面114進行蝕刻(etching)以形成一圖案化導電層110’，其中圖案化導電層110’包括一晶片座110a及環繞晶片座110a的多個引腳110b。接著，透過單體化製程形成多個四方扁平無引腳封裝100。值得注意的是，可在於導電層110上形成第一焊罩層120之後的任何製程步驟中，從第二表面114將部分導電層110移除。從第二表面114將部分導電層110移除的方法例如是背蝕刻(back-side etching)製程。Referring to FIG. 1F, the second surface 114 of the conductive layer 110 is etched to form a patterned conductive layer 110'. The patterned conductive layer 110' includes a wafer holder 110a and a plurality of leads surrounding the wafer holder 110a. Foot 110b. Next, a plurality of quad flat no-lead packages 100 are formed through a singulation process. It is noted that a portion of the conductive layer 110 may be removed from the second surface 114 in any of the processing steps after the first solder mask layer 120 is formed on the conductive layer 110. A method of removing a portion of the conductive layer 110 from the second surface 114 is, for example, a back-side etching process.
如圖1F所繪示，本發明的四方扁平無引腳封裝100主要包括一圖案化導電層110’、一第一焊罩層120、一晶片130、多條焊線150及一封裝膠體160。圖案化導電層110’具有一第一表面112，其中圖案化導電層110’包括一晶片座110a及環繞晶片座110a的多個引腳110b，且第一焊罩層120從圖案化導電層110’的第一表面112延伸至晶片座110a及引腳110b之間的區域。第一焊罩層120配置於第一表面112，其中第一焊罩層120暴露出部分第一表面112。晶片130配置於第一焊罩層120，其中第一焊罩層120位於圖案化導電層110’及晶片130之間。焊線150電性連接於晶片130及第一焊罩層120暴露出的圖案化導電層110’。封裝膠體160包覆圖案化導電層110’、第一焊罩層120、晶片130及焊線150。As shown in FIG. 1F, the quad flat no-lead package 100 of the present invention mainly includes a patterned conductive layer 110', a first solder mask layer 120, a wafer 130, a plurality of bonding wires 150, and an encapsulant 160. The patterned conductive layer 110' has a first surface 112, wherein the patterned conductive layer 110' includes a wafer holder 110a and a plurality of pins 110b surrounding the wafer holder 110a, and the first solder mask layer 120 is from the patterned conductive layer 110. The first surface 112 of ' extends to the area between the wafer holder 110a and the pin 110b. The first solder mask layer 120 is disposed on the first surface 112, wherein the first solder mask layer 120 exposes a portion of the first surface 112. The wafer 130 is disposed on the first solder mask layer 120, wherein the first solder mask layer 120 is located between the patterned conductive layer 110' and the wafer 130. The bonding wire 150 is electrically connected to the wafer 130 and the patterned conductive layer 110' exposed by the first solder mask layer 120. The encapsulant 160 encloses the patterned conductive layer 110', the first solder mask layer 120, the wafer 130, and the bonding wires 150.
請參考圖1G，在一可選擇的實施例中，可在第一焊罩層120形成多個第二開口124，以使得各晶片130被配置於一第二開口124，且黏著於被第一焊罩層120暴露出的第一表面112上。Referring to FIG. 1G, in an alternative embodiment, a plurality of second openings 124 may be formed in the first solder mask layer 120 such that the wafers 130 are disposed on a second opening 124 and adhered to the first The solder mask layer 120 is exposed on the first surface 112.
圖2A至圖2H為本發明第二實施例之四方扁平無引腳封裝的製程剖視流程圖。請參考圖2A，提供具有一第一表面212及一第二表面214的導電層210，並部分地移除位於預定區域之導電層210，以在導電層210的第二表面214上形成多個凹槽R。在本實施例中，是透過半蝕刻(half-etching)製程形成凹槽R。2A to 2H are cross-sectional views showing a process of a quad flat no-lead package according to a second embodiment of the present invention. Referring to FIG. 2A, a conductive layer 210 having a first surface 212 and a second surface 214 is provided, and the conductive layer 210 located in the predetermined region is partially removed to form a plurality of layers on the second surface 214 of the conductive layer 210. Groove R. In the present embodiment, the groove R is formed by a half-etching process.
請參考圖2B，在導電層210的第二表面214上之凹槽R所在區域形成一第二焊罩層220，以使凹槽R被第二焊罩層220所填滿。接著，請參考圖2C，在導電層210的第一表面212形成具有多個第一開口232的一第一焊罩層230，其中各第一開口232對應於一凹槽R，且第一開口232暴露出部分第一表面212。Referring to FIG. 2B, a second solder mask layer 220 is formed on the second surface 214 of the conductive layer 210 in the region of the recess R so that the recess R is filled by the second solder mask layer 220. Next, referring to FIG. 2C, a first solder mask layer 230 having a plurality of first openings 232 is formed on the first surface 212 of the conductive layer 210, wherein each of the first openings 232 corresponds to a recess R, and the first opening 232 exposes a portion of the first surface 212.
請參考圖2D，對被第一開口232暴露出的導電層210進行蝕刻，以形成一圖案化導電層210’，其中圖案化導電層210’包括一晶片座210a及環繞晶片座210a的多個引腳210b。請參考圖2E，對第一焊罩層230進行圖案化以形成多個第二開口234，其中第二開口234暴露出部分第一表面212。換言之，形成於部分第一表面212的第一焊罩層230定義出多個第一焊墊216。Referring to FIG. 2D, the conductive layer 210 exposed by the first opening 232 is etched to form a patterned conductive layer 210'. The patterned conductive layer 210' includes a wafer holder 210a and a plurality of wafer holders 210a. Pin 210b. Referring to FIG. 2E, the first solder mask layer 230 is patterned to form a plurality of second openings 234, wherein the second openings 234 expose portions of the first surface 212. In other words, the first solder mask layer 230 formed on a portion of the first surface 212 defines a plurality of first pads 216.
在本實施例中，第一焊罩層230可為一固態狀焊罩膜，且第一開口232及第二開口234是在第一焊罩層230被貼附於導電層210之前或之後被形成。在一可選擇的實施例中，可將一液態焊罩塗層塗佈在導電層210的第一表面212上，並將其固化及圖案化以形成第一焊罩層230。在本實施例中，第一焊罩層230例如是一感光B階膜。In this embodiment, the first solder mask layer 230 can be a solid solder mask film, and the first opening 232 and the second opening 234 are before or after the first solder mask layer 230 is attached to the conductive layer 210. form. In an alternative embodiment, a liquid solder mask coating can be applied to the first surface 212 of the conductive layer 210 and cured and patterned to form the first solder mask layer 230. In the present embodiment, the first solder mask layer 230 is, for example, a photosensitive B-stage film.
此外，在一較佳實施例中，可透過電鍍製程在第一焊墊216上形成一電鍍導電層(未繪示)。電鍍導電層可為鎳金疊層或其它適用的金屬層。值得注意的是，可在於導電層210上形成第一焊罩層230之前或之後形成電鍍導電層。In addition, in a preferred embodiment, an electroplated conductive layer (not shown) is formed on the first pad 216 through an electroplating process. The electroplated conductive layer can be a nickel gold laminate or other suitable metal layer. It is to be noted that the electroplated conductive layer may be formed before or after the first solder mask layer 230 is formed on the conductive layer 210.
請參考圖2F，將多個晶片240黏著至第一焊罩層230，並接著形成多條焊線260以電性連接晶片240及圖案化導電層210’，其中各晶片240具有一主動表面242、相對主動表面242的一背面244及配置於主動表面242的多個第二焊墊246。各晶片240透過位於晶片240及圖案化導電層210’之間的一黏著層250而黏著於第一焊罩層230上，以使得第一焊罩層230位於圖案化導電層210’及各晶片240之間。Referring to FIG. 2F, a plurality of wafers 240 are adhered to the first solder mask layer 230, and then a plurality of bonding wires 260 are formed to electrically connect the wafer 240 and the patterned conductive layer 210'. Each of the wafers 240 has an active surface 242. A back surface 244 of the active surface 242 and a plurality of second pads 246 disposed on the active surface 242. Each of the wafers 240 is adhered to the first solder mask layer 230 through an adhesive layer 250 between the wafer 240 and the patterned conductive layer 210 ′ such that the first solder mask layer 230 is located on the patterned conductive layer 210 ′ and the respective wafers. Between 240.
在本實施例中，焊線260是透過打線製程被形成，以使得各焊線260電性連接於一第一焊墊216及一第二焊墊246之間。In the present embodiment, the bonding wires 260 are formed through a wire bonding process such that the bonding wires 260 are electrically connected between a first bonding pad 216 and a second bonding pad 246.
請參考圖2G，形成包覆圖案化導電層210’、第一焊罩層230、第二焊罩層220、晶片240及焊線260的一封裝膠體270。請參考圖2H，透過單體化製程形成多個四方扁平無引腳封裝200。Referring to FIG. 2G, an encapsulant 270 is formed over the patterned conductive layer 210', the first solder mask layer 230, the second solder mask layer 220, the wafer 240, and the bonding wires 260. Referring to FIG. 2H, a plurality of quad flat no-lead packages 200 are formed through a singulation process.
相較於圖1F之四方扁平無引腳封裝100，圖2H之四方扁平無引腳封裝200更包括配置於晶片座210a及引腳210b之間且不與第一焊罩層230接觸的一第二焊罩層220。Compared with the quad flat no-lead package 100 of FIG. 1F, the quad flat no-lead package 200 of FIG. 2H further includes a first portion disposed between the wafer holder 210a and the pin 210b and not in contact with the first solder mask layer 230. Second welding layer 220.
在一可選擇的實施例中，可在第一焊罩層230形成多個第三開口(未繪示)，以使各晶片240配置於一第三開口且黏著於被第一焊罩層230暴露出的第一表面212。In an alternative embodiment, a plurality of third openings (not shown) may be formed in the first solder mask layer 230 such that the wafers 240 are disposed on a third opening and adhered to the first solder mask layer 230. The exposed first surface 212.
圖3A至圖3F為本發明第三實施例之四方扁平無引腳封裝的製程剖視流程圖。請參考圖3A，提供一第一焊罩層320及具有一第一表面312及一第二表面314的一導電層310，且第一焊罩層320是透過模造(molding)或印刷(printing)而形成於第一表面312。3A to 3F are cross-sectional views showing a process of a quad flat no-lead package according to a third embodiment of the present invention. Referring to FIG. 3A, a first solder mask layer 320 and a conductive layer 310 having a first surface 312 and a second surface 314 are provided, and the first solder mask layer 320 is molded or printed. It is formed on the first surface 312.
接著，請參考圖3B，透過微影(photolithography)蝕刻製程形成一圖案化導電層310’，其中圖案化導電層310’包括一晶片座310a及環繞晶片座310a的多個引腳310b。Next, referring to FIG. 3B, a patterned conductive layer 310' is formed through a photolithography etching process, wherein the patterned conductive layer 310' includes a wafer holder 310a and a plurality of pins 310b surrounding the wafer holder 310a.
接著，請參考圖3C，對第一焊罩層320進行圖案化以形成多個第一開口322。換言之，形成於部分第一表面312的第一焊罩層320定義出多個第一焊墊316。值得注意的是，本發明並不限制用以形成圖案化導電層310’及第一焊罩層320的第一開口322之圖案化製程的順序。Next, referring to FIG. 3C, the first solder mask layer 320 is patterned to form a plurality of first openings 322. In other words, the first solder mask layer 320 formed on a portion of the first surface 312 defines a plurality of first pads 316. It should be noted that the present invention does not limit the order of the patterning process for forming the patterned conductive layer 310' and the first opening 322 of the first solder mask layer 320.
在本實施例中，第一焊罩層320可為一固態狀焊罩膜，且第一開口322在第一焊罩層320被貼附於導電層310之前或之後被形成。在一可選擇的實施例中，可將一液態焊罩塗層塗佈在導電層310的第一表面312上，並將其固化及圖案化以形成第一焊罩層320。在本實施例中，第一焊罩層320例如是一感光B階膜。In the present embodiment, the first solder mask layer 320 may be a solid solder mask film, and the first opening 322 is formed before or after the first solder mask layer 320 is attached to the conductive layer 310. In an alternative embodiment, a liquid solder mask coating can be applied over the first surface 312 of the conductive layer 310 and cured and patterned to form the first solder mask layer 320. In the present embodiment, the first solder mask layer 320 is, for example, a photosensitive B-stage film.
此外，在一較佳實施例中，可透過電鍍製程在第一焊墊316上形成一電鍍導電層(未繪示)。電鍍導電層可為一鎳金疊層或其它適用的金屬層。值得注意的是，可在於導電層310上形成第一焊罩層320之前或之後形成電鍍導電層。In addition, in a preferred embodiment, an electroplated conductive layer (not shown) is formed on the first pad 316 through an electroplating process. The electroplated conductive layer can be a nickel gold stack or other suitable metal layer. It is noted that the electroplated conductive layer may be formed before or after the first solder mask layer 320 is formed on the conductive layer 310.
請參考圖3D，將多個晶片330黏著至第一焊罩層320，並接著形成多條焊線350以電性連接晶片330及圖案化導電層310’，其中各晶片330具有一主動表面332、相對主動表面332的一背面334及配置於主動表面332上的多個第二焊墊336。各晶片330透過位於晶片330及圖案化導電層310’之間的一黏著層340而黏著於第一焊罩層320，以使得第一焊罩層320位於各晶片330及圖案化導電層310’之間。Referring to FIG. 3D, a plurality of wafers 330 are adhered to the first solder mask layer 320, and then a plurality of bonding wires 350 are formed to electrically connect the wafer 330 and the patterned conductive layer 310'. Each of the wafers 330 has an active surface 332. A back surface 334 of the active surface 332 and a plurality of second pads 336 disposed on the active surface 332. Each of the wafers 330 is adhered to the first solder mask layer 320 through an adhesive layer 340 between the wafer 330 and the patterned conductive layer 310' such that the first solder mask layer 320 is located on each of the wafers 330 and the patterned conductive layer 310'. between.
在本實施例中，焊線350是透過打線製程被形成，以使得各焊線350電性連接於一第一焊墊316及一第二焊墊336之間。In the present embodiment, the bonding wires 350 are formed through a wire bonding process such that the bonding wires 350 are electrically connected between a first bonding pad 316 and a second bonding pad 336.
請參考圖3E，形成包覆圖案化導電層310’、第一焊罩層320、晶片330及焊線350的一封裝膠體360。請參考圖3F，透過單體化製程形成多個四方扁平無引腳封裝300。Referring to FIG. 3E, an encapsulant 360 is formed over the patterned conductive layer 310', the first solder mask layer 320, the wafer 330, and the bonding wires 350. Referring to FIG. 3F, a plurality of quad flat no-lead packages 300 are formed through a singulation process.
相較於圖1之四方扁平無引腳封裝100，圖3F之四方扁平無引腳封裝300不從圖案化導電層310’的第一表面312延伸至晶片座310a及引腳310b之間的區域，且晶片座310a及引腳310b之間的區域被封裝膠體360所填滿。Compared to the quad flat no-lead package 100 of FIG. 1, the quad flat no-lead package 300 of FIG. 3F does not extend from the first surface 312 of the patterned conductive layer 310' to the area between the wafer holder 310a and the pin 310b. And the area between the wafer holder 310a and the lead 310b is filled with the encapsulant 360.
在一可選擇的實施例中，可在第一焊罩層320形成多個第二開口(未繪示)，以使各晶片330配置於一第二開口且黏著於被第一焊罩層320暴露出的第一表面312。In an alternative embodiment, a plurality of second openings (not shown) may be formed in the first solder mask layer 320 such that the wafers 330 are disposed on a second opening and adhered to the first solder mask layer 320. The exposed first surface 312.
綜上所述，相較於傳統之四方扁平無引腳封裝，本發明之四方扁平無引腳封裝具有用以強化其結構強度的焊罩層，以使圖案化導電層可具有較小的厚度。此外，四方扁平無引腳封裝具有較小的整體厚度及較低的製造成本，以使產能(throughput)獲得提升。In summary, the quad flat no-lead package of the present invention has a solder mask layer for strengthening the structural strength thereof, so that the patterned conductive layer can have a smaller thickness than a conventional quad flat no-lead package. . In addition, the quad flat no-lead package has a smaller overall thickness and lower manufacturing cost to increase throughput.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、200、300．．．四方扁平無引腳封裝100, 200, 300. . . Quad flat no-lead package
110、210、310．．．導電層110, 210, 310. . . Conductive layer
110’、210’、310’．．．圖案化導電層110', 210', 310'. . . Patterned conductive layer
110a、210a、310a．．．晶片座110a, 210a, 310a. . . Wafer holder
110b、210b、310b．．．引腳110b, 210b, 310b. . . Pin
112、212、312．．．第一表面112, 212, 312. . . First surface
114、214、314．．．第二表面114, 214, 314. . . Second surface
118、216、316．．．第一焊墊118, 216, 316. . . First pad
120、230、320．．．第一焊罩層120, 230, 320. . . First welding layer
122、232、322．．．第一開口122, 232, 322. . . First opening
124、234．．．第二開口124, 234. . . Second opening
130、240、330．．．晶片130, 240, 330. . . Wafer
132、242、332．．．主動表面132, 242, 332. . . Active surface
134、244、334．．．背面134, 244, 334. . . back
136、246、336．．．第二焊墊136, 246, 336. . . Second pad
140、250、340．．．黏著層140, 250, 340. . . Adhesive layer
150、260、350．．．焊線150, 260, 350. . . Welding wire
160、270．．．封裝膠體160, 270. . . Encapsulant
220．．．第二焊罩層220. . . Second welding layer
R．．．凹槽R. . . Groove
圖1A至圖1G為本發明第一實施例之四方扁平無引腳封裝的製程剖視流程圖。1A to 1G are cross-sectional views showing a process of a quad flat no-lead package according to a first embodiment of the present invention.
圖2A至圖2H為本發明第二實施例之四方扁平無引腳封裝的製程剖視流程圖。2A to 2H are cross-sectional views showing a process of a quad flat no-lead package according to a second embodiment of the present invention.
圖3A至圖3F為本發明第三實施例之四方扁平無引腳封裝的製程剖視流程圖。3A to 3F are cross-sectional views showing a process of a quad flat no-lead package according to a third embodiment of the present invention.
100．．．四方扁平無引腳封裝100. . . Quad flat no-lead package
110’．．．圖案化導電層110’. . . Patterned conductive layer
110a．．．晶片座110a. . . Wafer holder
110b．．．引腳110b. . . Pin
112．．．第一表面112. . . First surface
118．．．第一焊墊118. . . First pad
120．．．第一焊罩層120. . . First welding layer
122．．．第一開口122. . . First opening
130．．．晶片130. . . Wafer
132．．．主動表面132. . . Active surface
134．．．背面134. . . back
136．．．第二焊墊136. . . Second pad
140．．．黏著層140. . . Adhesive layer
150．．．焊線150. . . Welding wire
160．．．封裝膠體160. . . Encapsulant
Claims (14)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/201,236 US7851896B2 (en) | 2005-07-14 | 2008-08-29 | Quad flat non-leaded chip package |
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| TW201010035A TW201010035A (en) | 2010-03-01 |
| TWI462252B true TWI462252B (en) | 2014-11-21 |
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| TW098101388A TWI462252B (en) | 2008-08-29 | 2009-01-15 | Quad flat no-lead package |
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| TW (1) | TWI462252B (en) |
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|---|---|---|---|---|
| CN102201348A (en) * | 2010-03-26 | 2011-09-28 | 力成科技股份有限公司 | Array Dicing Quad Flat No Leads Packaging Method |
| CN103050415A (en) * | 2012-12-10 | 2013-04-17 | 华天科技（西安）有限公司 | Sequential browning and green paint brushing-based flat package manufacturing process |
| TWI556359B (en) * | 2015-03-31 | 2016-11-01 | 南茂科技股份有限公司 | Quad flat no-lead package structure and quad flat no-lead package leadframe structure |
| TWI688057B (en) * | 2018-12-11 | 2020-03-11 | 南茂科技股份有限公司 | Semiconductor package structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-sealed semiconductor device |
| TW200307359A (en) * | 2002-05-23 | 2003-12-01 | Renesas Tech Corp | Semiconductor device and electronic apparatus |
| TW200601472A (en) * | 2004-06-29 | 2006-01-01 | Advanced Semiconductor Eng | Leadframe for leadless flip-chip package and method for manufacturing the same |
-
2009
- 2009-01-15 TW TW098101388A patent/TWI462252B/en not_active IP Right Cessation
- 2009-02-12 CN CN2009100044085A patent/CN101661918B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-sealed semiconductor device |
| TW200307359A (en) * | 2002-05-23 | 2003-12-01 | Renesas Tech Corp | Semiconductor device and electronic apparatus |
| TW200601472A (en) * | 2004-06-29 | 2006-01-01 | Advanced Semiconductor Eng | Leadframe for leadless flip-chip package and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101661918B (en) | 2011-10-05 |
| CN101661918A (en) | 2010-03-03 |
| TW201010035A (en) | 2010-03-01 |
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