Claims (10)
一種三維網路晶片拓樸合成方法，其包含：產生通訊軌跡圖步驟，其於數個源頭節點及數個目的節點之間進行通訊關係分析，以獲得數個源頭元件及數個目的元件，並產生一通訊軌跡圖；二維轉換三維步驟，其於該源頭元件及目的元件之間利用通訊雙分轉換方式進行轉換，以便由該通訊軌跡圖轉換獲得一通訊雙分圖，且該通訊雙分圖具有該源頭元件及目的元件之通訊關係；建立連線容錯步驟，其在每一顆路由器都產生一第二條路由器間的連線，因此當某一條連線發生故障時，尚能利用該第二條連線作為訊號傳輸的取代路徑，使得通訊仍能夠正常運作；及路由器無死結架構步驟，其採用一個無死結的路由器架構。
A three-dimensional network wafer topology synthesis method includes: generating a communication trace diagram step, performing communication relationship analysis between a plurality of source nodes and a plurality of destination nodes to obtain a plurality of source components and a plurality of destination components, and Generating a communication trajectory map; a two-dimensional conversion three-dimensional step, converting between the source component and the destination component by using a communication binary conversion mode, so as to obtain a communication bipartite graph by the communication trajectory map conversion, and the communication bipartite The figure has a communication relationship between the source element and the destination element; establishing a connection fault tolerance step, which generates a connection between the second routers in each router, so when a connection fails, the figure can still be utilized. The second connection is used as a replacement path for signal transmission, so that communication can still operate normally; and the router has no dead-end architecture steps, and it adopts a deadlock-free router architecture.
一種三維網路晶片拓樸合成方法，其包含：在一電路上尋找數個源頭節點及數個目的節點；於該數個源頭節點及數個目的節點之間進行通訊關係分析，以便組合獲得數個源頭元件及數個目的元件；於該源頭元件及目的元件之間利用通訊雙分轉換方式進行轉換，以獲得一通訊雙分圖，且該通訊雙分圖具有該源頭元件及目的元件之通訊關係；依該通訊雙分圖進行通訊雙分切割演算，以獲得一預定層數量，且獲得一預定矽穿孔數量連接於該預定層之間；依該預定層數量將該電路切割形成預定數量之群體；及將該群體利用層排序分配方式進行排列，以獲得一3D架構。
A three-dimensional network wafer topology synthesis method includes: searching for a plurality of source nodes and a plurality of destination nodes on a circuit; performing communication relationship analysis between the plurality of source nodes and the plurality of destination nodes, so as to obtain a number a source component and a plurality of destination components; converting between the source component and the destination component by using a communication binary conversion method to obtain a communication bipartite graph, wherein the communication bipartite graph has communication between the source component and the destination component Relationship; performing a communication double-cutting calculation according to the communication bipartite graph to obtain a predetermined number of layers, and obtaining a predetermined number of perforations perforated between the predetermined layers; cutting the circuit to form a predetermined number according to the predetermined number of layers Groups; and arranging the groups by layer sorting to obtain a 3D architecture.
依申請專利範圍第2項所述之三維網路晶片拓樸合成方法，其中該電路由二維轉換至三維網路晶片。
The three-dimensional network wafer topology synthesis method according to claim 2, wherein the circuit is converted from two-dimensional to a three-dimensional network wafer.
依申請專利範圍第1或2項所述之三維網路晶片拓樸合成方法，其中該通訊雙分切割演算係屬max-flow min-cut演算法。
The three-dimensional network wafer topology synthesis method according to claim 1 or 2, wherein the communication double-cutting algorithm is a max-flow min-cut algorithm.
依申請專利範圍第2項所述之三維網路晶片拓樸合成方法，其中在利用層排序分配方式進行排列時，計算該群體之間的連接相關性個數及連線個數，以計算連接成本函數。
The method for synthesizing a three-dimensional network chip topology according to item 2 of the patent application scope, wherein when the layer sorting allocation method is used for arranging, the number of connection correlations and the number of connections between the groups are calculated to calculate a connection. Cost function.
依申請專利範圍第5項所述之三維網路晶片拓樸合成方法，其中利用該連接成本函數之高低進行層排序。
The three-dimensional network wafer topology synthesis method according to claim 5, wherein the layer ordering is performed by using the connection cost function.
依申請專利範圍第1或2項所述之三維網路晶片拓樸合成方法，其採用Bin-Packing演算法在每層內部進行組分群及De Bruijn演算法建立連線容錯的拓樸。
According to the three-dimensional network wafer topology synthesis method described in claim 1 or 2, the Bin-Packing algorithm is used to perform the component fault group and the De Bruijn algorithm in each layer to establish a topology of connection fault tolerance.
依申請專利範圍第1或2項所述之三維網路晶片拓樸合成方法，其採用Floyd-Warshall演算法作為路徑選擇演算法，以決定路由器封包傳送方向或路徑。
According to the three-dimensional network chip topology synthesis method described in claim 1 or 2, the Floyd-Warshall algorithm is used as a path selection algorithm to determine the direction or path of the router packet transmission.
依申請專利範圍第1或2項所述之三維網路晶片拓樸合成方法，其採用傳送緩衝器及重傳緩衝器形成無死結路由器架構。
According to the three-dimensional network chip topology synthesis method described in claim 1 or 2, the transmission buffer and the retransmission buffer are used to form a deadlockless router architecture.
依申請專利範圍第1或2項所述之三維網路晶片拓樸合成方法，其採用快速退火模擬演算法，以獲得一平面規劃，且該平面規劃採用成本函數，以取得較短的繞線長度且面積較小的平面規劃。
According to the three-dimensional network wafer topology synthesis method described in claim 1 or 2, the rapid annealing simulation algorithm is adopted to obtain a plane plan, and the plane plan adopts a cost function to obtain a shorter winding. Plane with a small length and a small area.