TWI454066B - Multiplying digital-to-analog converter for use in a pipelined analog-to-digital converter - Google Patents

Description

Product Digital to Analog Converter for Pipeline Analog to Digital Converter

The present invention relates to a product digital to analog converter for a pipeline analog to digital converter, and more particularly to a product digital to analog converter for a pipeline analog to digital converter that utilizes a compensation capacitor to reduce power consumption.

The pipeline analog-to-digital converter combines the advantages of high sampling rate and high resolution, and is often used in video imaging systems, digital subscriber loops, and ultrasonic medical imaging applications. Digital receiver, fast Ethernet, or wireless communication system. In general, the operation of a pipeline analog to digital converter includes two stages of sampling and hold, often implemented by switching capacitor technology.

FIG. 1 is a functional block diagram of a pipeline analog to digital converter 100. The pipeline analog to digital converter 100 includes a sample-and-hold amplifier SHA, a plurality of pipeline stage circuits ST ₁ to ST _n (n is a positive integer), and a logic correction circuit. 10. The pipeline analog to digital converter 100 converts a analog input signal D _IN into a digital output signal D _OUT . If the resolution of the pipeline analog to digital converter 100 is N bits, the representative digital output signal D _OUT is N-bit data, and the number of required pipeline stage circuits ST1 to STn is related to its precision.

The sample and hold amplifier SHA is a pipeline analog to the initial stage of the digital converter 100, and is used for sampling the analog input signal D _IN , and then outputting the sampled analog input signal V ₁ to the first stage pipeline stage circuit ST ₁ for use. Its input signal. According to its preset accuracy, each stage pipeline stage circuit generates an analog input signal of the next stage pipeline stage circuit according to its analog input signal, and outputs a digital code corresponding to its analog input signal to the logic correction circuit 10. Taking the accuracy of N-2 as an example, the j-th pipeline stage circuit ST _j first digitizes the analog input signal V _j , subtracts two bits and then converts the residual value to the next-level analog input signal V. _j+1 (j+1 is a positive integer between 1 and n), and the subtracted two-digit number bit code M _{j is} output to the logic correction circuit 10, wherein one bit is used for parsing, and the other One element is used as a bug fix. And so on, the n-stage pipeline stage _n ST circuit analog input signal V will first number of _n bits, then two yuan subtracting digit code of M _n to the logic output correction circuit 10, where as the analysis only one yuan And another bit is used as a bug fix.

2 is a functional block diagram of a j-th stage pipeline stage circuit ST _j for one of the pipeline analog to digital converters 100. The pipeline stage ST _j includes a multiplying digital-to-analog converter MDAC and a sub analog-to-digital converter S_ADC. The product digital to analog converter MDAC includes a sub digital-to-analog converter S_DAC, an operational amplifier OP, and a logic operation unit 20. The sub- analog to digital converter S_ADC converts the analog input signal V _j into a two-digit digital code M _j , and then outputs the two-digit digital code M _j to the sub-digit to the analog converter S_DAC and the logic correction in FIG. Circuit 10 (not shown in Figure 2). The sub-digit to analog converter S_DAC can convert the two-digit number bit code M _j into an analog reference signal VR _j and output it to the logic operation unit 20. The analog operation signal 20 can obtain the analog input signal V _j minus the value of the analog reference signal VR _j , so that the operational amplifier OP can generate the analogy required for the operation of the (j+1)-stage pipeline stage circuit ST _j+1 . Enter the signal V _j+1 . The functions, structures and operations of the other stages of the pipeline stages in Figure 1 are the same, and are not described here.

The prior art multiplier-to-analog converter MDAC includes a feedback capacitor C _F , an input capacitor C _I and an operational amplifier OP. Figure 3A is an equivalent circuit diagram of the prior art multiplier-to-analog converter MDAC operating in the sampling phase, in which the positive input and the negative input of the operational amplifier OP are coupled to a common signal V _COM , and the feedback capacitor Both the C _F and the input capacitor C _{I are} coupled between the analog input signal V _j and the negative input terminal of the operational amplifier OP. Therefore, the feedback capacitor C _F and the input capacitor C _I sample the analog input signal V _j . Assuming that the common signal V _COM is the ground potential, the value of the charge Q _S stored in the sampling phase is as follows:

Q _S =V _j *(C _F +C _I )

Figure 3B is an equivalent circuit diagram of the prior art multiplier-to-analog converter MDAC operating in the hold phase, where the feedback capacitor C _{F is} coupled between the negative input and the output of the operational amplifier OP, and the input capacitor C _{I is} coupled between the analog reference signal VR _j and the negative input terminal of the operational amplifier OP. When operating in the hold phase, the negative input of the op amp OP can be considered a virtual ground potential, so the value of the stored charge Q _H during the hold phase is as follows:

Q _H =Y _j+1 *C _F +VR _j *C _I

According to the principle of energy balance, Q _S =Q _H , therefore:

V _j+1 =[V _j *(C _F +C _I )-VR _j *C _I ]/C _F

If C _F =C _I

V _j+1 =2V _j -VR _j

In general, the multiplier-to-analog converter MDAC uses the feedback capacitor C _F and the input capacitor C _{I of the} same capacitance value, so the feedback factor of the op amp OP is only about 0.5, and the op amp is often required. The unit-gain bandwidth of the OP is designed to be large, but this increases the power consumption of the pipeline analog to digital converter.

The present invention provides a multiplying-to-analog converter for use in a pipeline analog to digital converter, the multiplying digital to analog converter comprising an amplifier including a first input and a first output a first feedback capacitor having a first end selectively coupled to a first input signal or a first output of the amplifier, and a second end coupled to the first input of the amplifier or a common a first input capacitor, the first end of which is selectively coupled to the first input signal or the common signal, and the second end of which is selectively electrically coupled to the first input of the amplifier or the common The first compensation terminal has a first end selectively coupled to a first reference signal or the common signal, and a second end coupled to the second end of the first input capacitor. The first feedback capacitor is coupled between the first input signal and the common signal, and the first input capacitor is coupled between the first input signal and the common signal. The first compensation capacitor is coupled to the common signal to reset the first compensation capacitor. In a second sampling phase, the first feedback capacitor is coupled to the first input signal and The first input capacitor is coupled between the first input signal and the common signal, and the first end of the first compensation capacitor is coupled to the first reference signal; The first feedback capacitor is coupled between the first input end of the amplifier and the first output end of the amplifier, and the first end of the first input capacitor is coupled to the common signal, and The first input capacitor is coupled to the first input end of the amplifier by a first switch, and the first compensation capacitor is coupled to the first input capacitor; and in a second hold phase The first feedback capacitor is coupled to the first input of the amplifier The first end of the first input capacitor is coupled to the common signal, and the second end of the first input capacitor is coupled to the amplifier by the first switch An input is electrically separated, and the first compensation capacitor is connected in parallel to the first input capacitor.

The multiplier-to-analog converter of the present invention can be used in the j-stage pipeline stage circuit STj of the pipeline analog-to-digital converter 100, and includes a feedback capacitor C _F , an input capacitor C _I , and a compensation capacitor C _{P .} , and an operational amplifier OP. The cycle of each stage of the pipeline stage circuit comprises four phases: a first sampling phase, a second sampling phase, a first holding phase, and a second holding phase.

4A is an equivalent circuit diagram of the multi-digit to analog converter MDAC in the first sampling phase of the present invention, wherein the feedback capacitor C _F and the input capacitor C _{I are} coupled to the analog input signal V _j and the operational amplifier OP The compensation capacitor C _{P is} coupled between a common signal V _COM and a negative input terminal of the operational amplifier OP, and the positive input terminal and the negative input terminal of the operational amplifier OP are coupled to the common signal V _COM . During the first sampling phase, the compensation capacitor C _P is reset, so that the memory charge of the compensation capacitor C _P can be cleared, and the feedback capacitor C _F and the input capacitor C _I sample the analog input signal V _j .

4B is an equivalent circuit diagram of the multi-digit to analog converter MDAC in the second sampling stage of the present invention, in which the feedback capacitor C _F and the input capacitor C _{I are} coupled to the analog input signal V _j and the operational amplifier OP Between the negative input terminals, the compensation capacitor C _{P is} coupled between the reference signal VR _j and the negative input terminal of the operational amplifier OP, and the positive input terminal and the negative input terminal of the operational amplifier OP are coupled to the common signal V _COM . A sub-analog-to-digital converter S_ADC (FIG. 2) to convert the analog input signal V _j into a digital code M _j, the sub-analog-to-digital converter S_DAC then based on the digital code M _j to generate a reference signal VR _j. The reference signal VR _j may select a voltage from a set of voltages (+ΔV, VCOM, -ΔV) according to the digital code as the reference signal VR _j (as shown in FIG. 6). In the second sampling phase, the reference signal VR _j charges or discharges the compensation capacitor C _P , and the feedback capacitor C _F and the input capacitor C _I sample the analog input signal V _j . Assuming that the common signal V _COM is the ground potential, the value of the stored charge Q _S ' in the second sampling phase is as follows:

Q _S '=V _j *(C _F +C _I )+VR _j *C _P

4C is an equivalent circuit diagram of the multi-digit to analog converter MDAC in the first hold phase of the present invention, wherein the feedback capacitor C _{F is} coupled between the negative input terminal and the output terminal of the operational amplifier OP, and the input capacitor Both C _I and the compensation capacitor C _{P are} coupled between the common signal V _COM and the negative input terminal of the operational amplifier OP. During the first hold phase, the negative input of the operational amplifier OP can be regarded as a virtual ground potential, so the memory charge of the input capacitor C _I and the compensation capacitor C _P is transferred to the feedback capacitor C _F for charging.

4D is an equivalent circuit diagram of the multi-digit to analog converter MDAC in the second hold phase of the present invention, wherein the feedback capacitor C _{F is} coupled between the negative input terminal and the output terminal of the operational amplifier OP, and the input capacitor C _I and the compensation capacitor C _P are connected in parallel with each other but are electrically separated from the negative input terminal of the operational amplifier OP (which can be electrically separated by a switch). Thus, the feedback charge capacitance C _F of the memory provides the first (j + 1) stage of the pipeline stage ST _{j + 1} required for the circuit operation of the analog input signal V _{j + 1,} wherein Q _H the charge stored in the second holding stage ' The values are as follows:

Q _H '=V _j+1 *C _F

According to the principle of energy balance, Q _S '=Q _H ', therefore:

V _j+1 =V _j *(C _F +C _I )/C _F +VR _j *C _P /C _F

As shown above, the multiplier-to-analog converter of the present invention can utilize the compensation capacitor C _P to increase the feedback factor of the operational amplifier OP (β=1) and reduce the unity gain bandwidth required by the operational amplifier OP, thereby reducing Pipeline analog to power consumption of digital converters.

Figure 5 is a schematic diagram of a multiplicative digital to analog converter MDAC in accordance with one embodiment of the present invention. By turning the corresponding switch on or off at different points in time, the four stages shown in Figures 4A through 4D can be achieved. Fig. 5 is only an embodiment of the multiplicative digital to analog converter MDAC of the present invention, and does not limit the scope of the present invention.

In other embodiments of the present invention, the multiplicative digital to analog converter MDAC can also be a differential switched capacitor voltage doubler that utilizes two sets of feedback capacitors, two sets of input capacitors, and two sets of compensation. The capacitor converts a differential analog input signal V _jP and V _jN into differential digital output signals V _j+1P and V _j+1N (as shown in FIG. 7 ), wherein the reference voltages VR _jP and VR _jN are in a conjugate relationship.

In summary, the multiplier-to-analog converter of the present invention can switch the four-stage operation by using the feedback capacitor C _F , the input capacitor C _I and the compensation capacitor C _P , and can improve the operation by using the compensation capacitor C _P . The feedback factor of the amplifier OP reduces the power consumption of the pipeline analog to digital converter.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Logic correction circuit

20. . . Logical unit

100. . . Pipeline analog to digital converter

OP. . . Operational Amplifier

C _F . . . Feedback capacitor

C _I . . . Input capacitance

C _P . . . Compensation capacitor

SHA. . . Sample and hold amplifier

MDAC. . . Product digit to analog converter

S_ADC. . . Sub-class to digital converter

S_DAC. . . Sub-digit to analog converter

ST _j , ST ₁ to ST _n . . . Pipeline phase circuit

Figure 1 is a functional block diagram of a pipeline analog to digital converter.

Figure 2 is a functional block diagram of a pipeline stage circuit for a pipeline analog to digital converter.

Figure 3A is an equivalent circuit diagram of the prior art multiplier to analog converter operating during the sampling phase.

Figure 3B is an equivalent circuit diagram of the prior art multiplier to analog converter operating in the hold phase.

Figure 4A is an equivalent circuit diagram of the multiplicative digital to analog converter of the present invention operating in the first sampling phase.

Figure 4B is an equivalent circuit diagram of the multiplicative digital to analog converter of the present invention operating in the second sampling stage.

Figure 4C is an equivalent circuit diagram of the multiplicative digital to analog converter of the present invention operating in the second hold phase.

Figure 4D is an equivalent circuit diagram of the multiplicative digital to analog converter of the present invention operating in the second hold phase.

Figure 5 is a schematic diagram of a multiplicative digital to analog converter in accordance with one embodiment of the present invention.

Figure 6 is a schematic diagram of a neutron analog to digital converter of the present invention.

Figure 7 is a schematic diagram of a multiplicative digital to analog converter in accordance with one embodiment of the present invention. Device.

OP. . . Operational Amplifier

C _F . . . Feedback capacitor

C _I . . . Input capacitance

C _P . . . Compensation capacitor

S_DAC. . . Sub-digit to analog converter

Claims (6)

A multiplying digital-to-analog converter (MDAC) for use in a pipelined analog-to-digital converter, the multiplier-to-analog converter The method includes an amplifier including a first input end and a first output end, and a first feedback capacitor, the first end of which is selectively coupled to a first input signal or the first output end of the amplifier And the second end is coupled to the first input end of the amplifier or a common signal; a first input capacitor, the first end of which is selectively coupled to the first input signal or the common signal, and the first The second end is selectively electrically coupled to the first input of the amplifier or the common signal; and a first compensation capacitor, the first end of which is selectively coupled to a first reference signal or the common signal, and The second end is coupled to the second end of the first input capacitor, wherein the first feedback capacitor is coupled between the first input signal and the common signal during a first sampling phase, the first An input capacitor is coupled to the first input Between the signal and the common signal, the first end of the first compensation capacitor is coupled to the common signal to reset the first compensation capacitor; and in a second sampling phase, the first feedback capacitor is coupled Between the first input signal and the common signal, the first input capacitor is coupled between the first input signal and the common signal, and the first end of the first compensation capacitor is coupled to the first a first feedback capacitor is coupled between the first input end of the amplifier and the first output end of the amplifier, and the first end of the first input capacitor is coupled Connected to the common signal, and the second end of the first input capacitor is coupled to the first input end of the amplifier by a first switch, and the first compensation capacitor is connected in parallel with the first input capacitor; The first feedback capacitor is coupled between the first input end of the amplifier and the first output end of the amplifier, and the first end of the first input capacitor is coupled to the first input capacitor a common signal, and the first input capacitor is used by the first switch Ends with a first input terminal of the amplifier is electrically isolated, and the first compensation capacitor connected in parallel to the first line input capacitance. The multiplied digit to the analog converter as claimed in claim 1, wherein the first reference signal is determined according to an output result of a sub analog-to-digital converter, wherein the sub-class is The digital converter is configured to convert the first input signal into a digital code, and then generate the first reference signal according to the digital code. The multiplicative digits of claim 1 to the analog converter, wherein the values of the first feedback capacitor, the first compensation capacitor, and the first input capacitor are substantially equal. The multiplying digit to the analog converter of claim 1, wherein the amplifier further comprises a second input end and a second output end, and the first input end and the second input end of the amplifier are corresponding differentials Input, the first output end and the second output end of the amplifier are corresponding differential outputs, and the multiplying digital to analog converter further comprises: a second feedback capacitor, the first end of which is selectively coupled a second input signal or a second output of the amplifier, and a second end coupled to the second input of the amplifier or the common signal, wherein the first input signal and the second input signal are phase Corresponding differential signal, and the sub-class to digital converter is further configured to convert the second input signal into a second digit code, and generate a second reference signal according to the second digit code; a second input capacitor The first end is selectively coupled to the second input signal or the common signal, and the second end thereof is selectively electrically connected to the second input end of the amplifier or the common signal; and a second compensation Capacitor, its first end selectivity The ground is coupled to the second reference signal or the common signal, and the second end is coupled to the second end of the second input capacitor, wherein: the second feedback capacitor is coupled to the first sampling phase Connected between the second input signal and the common signal, the second input capacitor is coupled between the second input signal and the common signal, and the first end of the second compensation capacitor is coupled to the common The signal is used to reset the second compensation capacitor. The second feedback capacitor is coupled between the second input signal and the common signal. The second input capacitor is coupled to the second input capacitor. The first end of the second compensating capacitor is coupled to the second reference signal. The second feedback capacitor is coupled to the amplifier during the first holding phase. Between the second input end and the second output end of the amplifier, the first end of the second input capacitor is coupled to the common signal, and the second end of the second input capacitor is coupled by a second switch Coupled to a second input of the amplifier, and the second compensation capacitor is coupled The second input capacitor is coupled to the second input end of the amplifier and the second output end of the amplifier, and the second input capacitor is coupled to the second input capacitor. The first end is coupled to the common signal, and the second end of the second input capacitor is electrically separated from the second input end of the amplifier by the second switch, and the second compensation capacitor is connected in parallel The second input capacitor. The multiplied digit to the analog converter of claim 4, wherein the value of the second feedback capacitor and the value of the second input capacitor are substantially equal. The multiplicative digit to the analog converter of claim 5, wherein the value of the first feedback capacitor and the value of the second feedback capacitor are substantially equal.