TWI453654B - Storage and method for performing data backup - Google Patents

Description

Storage and data backup method thereof

The invention relates to a storage device design method, in particular to a storage device and a data backup method thereof.

The data backup technology after the sudden power outage of the computer system has been widely used in the field of storage design. Referring to FIG. 1, for the conventional memory design, after the computer system is powered off, the system control chip 16 directly copies the data in the memory 10 to the flash memory 18, when the computer system resumes power supply. The data in the flash memory 18 is then transmitted back to the memory 10. However, this method of data backup is to store the data in the flash memory 18, and the data confidentiality is insufficient. At the same time, in order to ensure the integrity of the data backup, the storage capacity of the flash memory 18 must be greater than or equal to the storage capacity of the memory 10, resulting in the usage rate of the flash memory 18 is too low (1:1), which increases the data backup cost. .

In view of the above, it is necessary to provide a storage device that can encode and compress the data in the memory and store it in the flash memory after the electronic device is powered off, and then flash the memory when the electronic device resumes power supply. The data in the decoding is passed back to the memory.

In view of the above, it is also necessary to provide a method for backing up data by using the above storage device, which can encode and compress the data in the memory and store it in the flash memory after the electronic device is powered off, and restore the power supply when the electronic device resumes power supply. After that, the flash memory will be The data in the body is decoded back to the memory.

The storage device includes a backup power supply, a power controller, a power control program, a system control chip, and a flash memory. The power controller is connected to a backup power supply and a power control program, and the system controls the connection between the chip and the power controller. A field programmable gate array is connected between the system control chip and the flash memory.

The method for backing up data by using the foregoing storage device includes the following steps: when the electronic device is powered off, starting the backup power supply; the system control chip reads the data in the memory and writes the data into the field programmable gate array; The gate array encodes the data and stores the encoded data in flash memory.

Compared with the prior art, the storage data backup method and the corresponding storage device encode the data in the memory to the flash memory after the electronic device is powered off, and when the electronic device resumes power supply, Then decode the data in the flash memory back to the memory. Since the data stored in the flash memory is encoded and protected, the security of the data backup is improved. In addition, since the encoded data is compressed, the flash memory can back up more data than the memory capacity, reducing the cost of data backup.

10‧‧‧ memory

11‧‧‧ North Bridge

12‧‧‧Connector

13‧‧‧Backup power supply

14‧‧‧Power Controller

15‧‧‧Power Control Program

16‧‧‧System Control Wafer

17‧‧‧FPGA

18‧‧‧Flash memory

19‧‧‧POL

20‧‧‧DDR2 DIMM

S1‧‧‧ When the power is off, start the backup power supply

The S2‧‧‧ system control chip reads the data in the memory and writes it to the FPGA.

S3‧‧‧FPGA encodes the data and stores it in flash memory

S4‧‧‧ When the power is restored, the FPGA decodes the data in the flash memory and transmits it to the system control chip.

The S5‧‧‧ system control chip transfers the decoded data back to the memory

Figure 1 is a hardware architecture diagram of a prior art memory.

2 is a hardware architecture diagram of a memory used in the data backup method of the present invention.

3 is a logic diagram of a field programmable gate array in the memory of FIG. 2.

4 is a flow chart of a preferred embodiment of the data backup method of the present invention.

Referring to FIG. 2, the hardware frame of the storage used in the data backup method of the present invention is shown. Composition. The memory 5 is connected to the north bridge 11 through a connector (such as a PCI-E interface) 12, and the north bridge 11 is connected to the memory 10 through a data line (such as a DDR2 data line). The storage device 5 includes: a backup power supply 13, a power controller 14, a power control program 15, a system control chip (such as a System-on-Chip, SoC) 16, and a Field Programmable Gate Array (FPGA). 17) Flash memory 18, step-down line (such as Point of Load, POL line) 19, memory module 20, and the like. In the embodiment, the memory module 20 is: DDR2 DIMMs (Dual In-line Memory Modules), and the power control program 15 can be solidified in a chip, such as PROM (Programmable Read-Only Memory).

The system control chip 16 is connected to the connector 12 through a data line (such as a PCI-E data line). The power controller 14 is connected to the backup power source 13 and the power control program 15 through the data line. The power control program 15 transmits the data line and the step-down circuit. 19, the power controller 14 and the power control program 15 are connected to the connector 12 through a data line (such as an Inter Integrated Circuit, I2C data line), and the system control chip 16 is connected to the memory module 20 through the data line. The system control chip 16 is directly connected to the flash memory 18 compared to the prior art memory 5 (see FIG. 1), while the system control chip 16 of FIG. 2 is passed through the field programmable gate array 17 and flash memory. The body 18 is connected, and the logic circuit diagram of the field programmable gate array 17 is shown in FIG.

Referring to Figure 3, a logic circuit diagram of the field programmable gate array 17 in the memory 5 of Figure 2 is shown. In the present embodiment, the field programmable gate array 17 includes a probability operation unit 21, a buffer area 22, an interval circuit 23, a binary unit 24, a delay area 25, an address resizing unit 26, and the like. Wherein, the buffer area 22 and the probability operation unit 21 and the area The inter-circuit circuit 23 is connected, and the interval circuit 23 is connected to the probability operation unit 21, the binary unit 24, and the address re-determination unit 26, and the delay region 25 is connected to the address re-determination unit 26. The specific function of the field programmable gate array 17 is described in the description of step S3 in FIG.

Referring to FIG. 4, it is a flow chart of a preferred embodiment of the data backup method of the present invention.

In step S1, when the electronic device (such as a computer) is powered off, the power control program 15 sends a power control command to the power controller 14, and then the power controller 14 activates the backup power source 13 according to the power control command. Thereafter, power is supplied from the backup power source 13 to the memory 10 and the system control chip 16 to ensure that the data in the memory 10 is temporarily not lost.

In step S2, the system control chip 16 reads the data in the memory 10 through the north bridge 11 and the connector 12, and writes the data into the field programmable gate array 17.

In step S3, the field programmable gate array 17 encodes the data and stores the encoded data in the flash memory 18. Since the data encoded by the field programmable gate array 17 is compressed, the occupied bits are less, and the flash memory 18 can back up more data than the memory 10, thereby improving the utilization of the flash memory 18. Rate, reducing the cost of data backup. In addition, since the data stored in the flash memory 18 is encoded and protected, important operational data can be prevented from being directly exposed to the flash memory 18, thereby increasing data confidentiality.

As described below, it is a specific process in which the field programmable gate array 17 encodes data.

(1) The probability operation unit 21 of the field programmable gate array 17 uses the lossless data encoding algorithm to calculate the cumulative occurrence probability of each character in the character sequence (such as 256 characters in the ASCII code), and the word is generated. The cumulative occurrence probability of each character in the meta-sequence is stored in the buffer area 22. In this embodiment, the lossless data encoding algorithm is arithmetic programming Code (Arithmetic Coding).

(2) When the cumulative occurrence probability of all the characters in the character sequence has been calculated, the probability operation unit 21 issues an encoding instruction (indicated by Ae) to the buffer area 22, and accumulates each character in the buffer area 22. The probability of occurrence is transmitted to the interval circuit 23.

(3) The interval circuit 23 calculates the coding interval of each character in the character sequence according to the cumulative occurrence probability of each character in the character sequence, and acquires the data to be encoded from the probability operation unit 21 (indicated by Data, For example, "ABBAC"), the coding interval of the last character in the data to be encoded is calculated according to the coding interval of each character in the character sequence.

(4) The section circuit 23 transmits the size of the encoding section (indicated by Count) of the last character in the data to be encoded to the address resizing unit 26. At the same time, the interval circuit 23 transmits the coding interval of the last character in the data to be encoded to the binary unit 24. The address resizing unit 26 extracts the address (indicated by Address) before encoding the data to be encoded from the delay region 25, and relocates the address of the data to be encoded according to the size of the encoding interval of the last character in the data to be encoded, and The address after re-positioning of the data to be encoded is transmitted to the flash memory 18. At the same time, the binary unit 24 converts the coding interval of the last character in the data to be encoded into binary data and transmits it to the flash memory 18.

(5) After the coding interval of the last character in the data to be encoded is converted into binary data, the enable signal (indicated by Signal) is transmitted from the delay zone 25 to the flash memory 18.

The following example illustrates the process of encoding data using arithmetic coding: Suppose there is a word consisting of five characters with equal probability of A, B, C, D, and E. The initial probability of A, B, C, D, E is as follows: A: 0 → 1/5, B: 1/5 → 2/5, C: 2/5 → 3/5, D: 3/ 5→4/5, E:4/5→1.

Assuming that the code to be encoded is “ABBAC”, the cumulative probability of A, B, C, D, E is: A: 1/5 → 2/6 → 2/7 → 2/8 → 3/9 → 3/ 10; B: 1/5 → 1/6 → 2/7 → 3/8 → 3/9 → 3/10; C: 1/5 → 1/6 → 1/7 → 1/8 → 1/9 → 2/10; D: 1/5 → 1/6 → 1/7 → 1/8 → 1/9 → 1/10; E: 1/5 → 1/6 → 1/7 → 1/8 → 1 9→1/10.

According to the cumulative probability of A, B, C, D, E, the coding intervals of A, B, C, D, and E are calculated as: A: [0, 3/10); B: [3/10, 6/10 ); C: [6/10, 8/10); D: [8/10, 9/10); E: [9/10, 1).

Then, the coding interval of the last character "C" in the data to be encoded "ABBAC" is calculated according to the coding interval of the character sequence A, B, C, D, E: A: [0, 3/10); B: [0+3/10*3/10, 0+3/10*6/10)=[9/100,18/100); B:[9/100+9/100*3/10,9 /100+9/100*6/10)=[117/1000,144/1000); A:[117/1000+27/1000*0,117/1000+27/1000*3/10)=[1170 /10000,1251/10000);C:[1170/10000+81/10000*6/10,1170/10000+81/10000*8/10)=[12186/100000,12348/100000)=[0.12186,0.12348 ).

Therefore, the coding interval of the last character "C" in the data to be encoded "ABBAC" is: [0.12186, 0.12348), and the conversion of "12186 (decimal number)" into a binary digit is: 10111110011010. The compression ratio of the data to be encoded "ABBAC" is: (1-14/20)* 100%=30%. The more data to be encoded, the better the compression ratio.

In step S4, when the electronic device power is restored, the FPGA field programmable gate array 17 decodes the data in the flash memory 18 and transmits it to the system control chip 16. The process of data decoding is the inverse of the data encoding process. Refer to the description of the data encoding process in step S3, and details are not described herein.

In step S5, the system control chip 16 transmits the decoded data back to the memory 10 through the connector 12 and the north bridge 11.

It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and the present invention is not limited thereto. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that Modifications or equivalents are made without departing from the spirit and scope of the invention.

S1‧‧‧ When the power is off, start the backup power supply

The S2‧‧‧ system control chip reads the data in the memory and writes it to the FPGA.

S3‧‧‧FPGA encodes the data and stores it in flash memory

S4‧‧‧ When the power is restored, the FPGA decodes the data in the flash memory and transmits it to the system control chip.

The S5‧‧‧ system control chip transfers the decoded data back to the memory

Claims (8)

A storage device includes a backup power supply, a power controller, a power control program, a system control chip, and a flash memory. The power controller is coupled to a backup power supply and a power control program. The system controls the chip to be connected to the power controller, wherein: A field programmable gate array is connected between the system control chip and the flash memory, and the field programmable gate array includes: a probability operation unit, a buffer area, an interval circuit, a binary unit, a delay area, and an address resizing unit. The probability operation unit is configured to calculate an accumulated occurrence probability of each character in the character sequence and store it in a buffer area; the probability operation unit is further configured to use all of the character sequence When the cumulative occurrence probability of the character has been calculated, the cumulative occurrence probability of each character in the buffer area is transmitted to the interval circuit; the interval circuit is configured to generate an occurrence probability according to each character in the character sequence Calculating a coding interval of each character in the sequence of characters; the interval circuit is further configured to obtain the data to be encoded from the probability operation unit, according to The coding interval of each character in the character sequence calculates the coding interval of the last character in the data to be encoded, and transmits the coding interval of the last character in the data to be encoded to the address resizing unit, and is to be encoded. The coding interval of the last character in the data is transmitted to the binary unit; the address resizing unit is configured to reposition the address of the data to be encoded according to the coding interval size of the last character in the data to be encoded, and The address of the data to be encoded is relocated to the flash memory; the binary unit is configured to convert the coding interval of the last character in the data to be encoded into binary data and transmit the data to the flash memory. And when the coding interval of the last character in the data to be encoded is converted into binary data, enable the message The number is transferred from the delay zone to the flash memory. The storage device of claim 1, wherein the reservoir is connected to the memory through a connector and a north bridge. The storage device of claim 2, wherein the connector is a PCI-E interface. A method for backing up data by using the storage in the first item of the patent application scope, the method comprising the steps of: starting the backup power supply when the electronic device is powered off; the system control chip reads the data in the memory and writes the data to the site. a programmable gate array; the field programmable gate array encodes the data, and stores the encoded data into the flash memory; wherein the step of the field programmable gate array encodes the data includes: the probability operation unit utilizes the lossless a data encoding algorithm that calculates an accumulative probability of occurrence of each character in the sequence of characters, and stores the cumulative occurrence probability of each character in the sequence of characters in the buffer; when all characters in the sequence of characters When the cumulative occurrence probability has been calculated, the probability operation unit sends an encoding instruction to the buffer area, and the cumulative occurrence probability of each character in the buffer area is transmitted to the interval circuit; the interval circuit accumulates each character according to the character sequence. The probability of occurrence calculates the coding interval of each character in the character sequence, and obtains the data to be encoded from the probability operation unit, according to the word The coding interval of each character in the meta-sequence calculates the coding interval of the last character in the data to be encoded; the interval circuit transmits the coding interval size of the last character in the data to be encoded to the address re-revision unit, and at the same time, The coding interval of the last character in the encoded data is transmitted to the binary unit; the address resizing unit is reset according to the coding interval of the last character in the data to be encoded. The address of the data to be encoded is transmitted to the flash memory, and the address of the last character in the data to be encoded is converted into binary data and transmitted. For the flash memory; and when the coding interval of the last character in the data to be encoded is converted into binary data, the enable signal is transmitted from the delay zone to the flash memory. The storage device data backup method of claim 4, wherein the method further comprises the step of: when the electronic device power is restored, the field programmable gate array decodes the data in the flash memory and transmits the data to the system. The control chip; and the system control chip transfers the decoded data back to the memory. The storage device data backup method of claim 4, wherein the step of starting the backup power supply comprises: the power control program sending a power control command to the power controller; and the power controller starting the backup power according to the power control command . The storage data backup method of claim 4, wherein the character sequence is 256 characters in ASCII code. The storage data backup method of claim 7, wherein the lossless data encoding algorithm is arithmetic coding.