TWI451432B - System and method for controlling output voltage slope in a semiconductor device - Google Patents

Description

System and method for controlling output voltage slope in a semiconductor device

The present invention provides a system and method for controlling the output voltage value driving capability in a semiconductor memory device.

It is well known that semiconductor memory devices can store data bits in a memory array. For example, a NAND flash memory stores data in a memory array. FIG. 1A shows a block diagram of the basic components of a typical NAND flash memory device 100. The memory device 100 includes a memory array 102 including a number of "i" memory strings MS1-MSi therein. Each of the memory strings MS1-MSi includes "j" memory cells of respective groups, connected in series between a common source line and respective bit lines BL1-BLi. Thus, this memory array 102 includes ixj memory cell arrays, where i and j are integers associated with memory array 102 capacity.

Each memory string MS1-MSi includes the same number of "j" series of floating gate transistors (not shown), each of which constitutes its respective memory cell. Each of the gate word lines WL1-WLj of the floating gate transistor is controlled by a signal from the column decoder 104. The word lines WL1-WLj are connected to all of the memory strings MS1-MSi; the word lines WL1-WLj control the gates of each of the floating gate transistors MS1-MSi.

A serial selection line SSL and a ground selection line GSL are also connected to all of the memory strings MS1-MSi. Each of the memory strings MS1-MSi includes a respective serial selection transistor (not shown). The tandem select line SSL controls the tandem select transistor of the memory train MS1-MSi; and the ground select line GSL controls the ground select transistor of the memory train MS1-MSi. The serial selection transistor controls the connection between the memory string MS1-MSi and its respective bit line BL1-BLi; and the ground selection transistor control is between the memory string MS1-MSi and the common source line The connection between the two.

The voltage value of this source line is controlled by the source line control circuit 106. The voltage values corresponding to the bit lines BL1-BLi are controlled by the respective sense amplifiers 108a-108i and the clamp transistors CT1-CTi. The applied voltage value also needs to be changed depending on the different operations performed by the memory cell. Examples of typical operations include read and write operations, where the write operation can vary depending on whether the memory cell is programmed or erased.

In order to perform the different modes of operation of the memory array 102, it is necessary to bring each control line to the voltage required for operation, which often takes some time. Therefore, in order to reduce the time required for different operations, the device bit lines BL1-BLi need to be maintained at some minimum allowable voltage value. However, power consumption is an important issue for many electronic devices. Maintaining the lowest allowable operating voltage value at all times can improve operating speed, but it has the disadvantage of consuming extra power. Therefore, for devices that are primarily powered by batteries, increasing power consumption may improve speed, but at the expense of reduced battery life.

These problems are well known and the solution is to take advantage of the "standby" mode mechanism to reduce power consumption and pre-charge different control lines while the action is in progress. For example, as in the memory device shown in FIG. 1A, the one-bit line driver 110 provides a one-line clamp signal BLCLAMP to the clamp transistors CT1-CTi. Corresponding to a read operation, respective sense amplifiers 108a-108i provide voltage pre-charging of bit lines BL1-BLi. The sense amplifiers 108a-108i selectively apply the voltage source V _DD to the respective bit lines BL1-BLi according to the state of the respective clamp transistors CT1-CTi.

Referring to FIG. 1B, before the one-line BL is pre-charged, the sense amplifier terminal (such as the drain) of the clamp transistor CT is located at V _DD , and the gate is at 0 V and the bit line end (such as the source). It is at 0V or floating. As shown in Figure 1C, it is known that each MOSFET transistor has a stray coupling capacitance, such as the gate-to-source capacitance labeled C _GS in Figure 1C. The bit line clamp signal BLCLAMP and the generated bit line voltage are shown in FIG. 1D. If the signal has a very steep transition, it will cause a fast precharge of the bit line. At the same time, the gate-to-source stray capacitance C _GS also causes a slight reverse coupling of this bit line clamp signal BLCLAMP. Therefore, the actual BLCLAMP voltage value (shown as a dashed line) will be higher than the expected voltage value (shown as a solid line). In addition, as shown in FIG. 1D, the bit line precharge value (shown as a dashed line) will therefore stay higher than the design value (shown as a solid line). Therefore, the coupling capacitance of the MOSFET transistor causes the memory device to generate an unintended voltage value during pre-charging, resulting in a memory operation error.

In addition, depending on the operation, the voltage values of adjacent bit lines BL1-BLi may be different. For example, in a read operation, one bit line is boosted to 0.7V and the adjacent bit line is grounded (0V). When a semiconductor device is scaled down, the distance between adjacent bit lines is also reduced. Therefore, the voltage difference between adjacent bit lines can cause a coupling effect, basically representing that the voltage on one bit line affects the voltage on other bit lines. Since the coupling effect causes errors in the reading and writing of the memory, it is desirable to avoid the occurrence of the effect when the memory device operates.

Therefore, there is a need to seek to reduce or eliminate unplanned results due to coupling capacitances in MOSFET transistors, such as adjacent control lines.

The present invention discloses a system and method for controlling the rate of rise of a bit line precharge voltage of a memory device. The systems and methods disclosed herein may include embodiments that allow for varying rate of rise. For example, according to some embodiments, the voltage driving circuit includes a current bias generating unit and a voltage driving unit. The voltage driving unit is coupled to the current bias generating unit. The current bias generating unit receives a mode signal and generates a mode selection current. The voltage driving unit receives the mode selection current and drives the output voltage according to the driving capability set by the mode selection current.

According to some embodiments, the mode signal comprises n bits, where n is an integer greater than one. In some embodiments, the voltage driving unit receives the mode signal, and the voltage driving unit drives the output voltage according to the driving capability determined by one of the n operating modes, wherein the n driving modes correspond to n driving modes ability.

In some embodiments, the current bias generating unit includes a control voltage unit, a mode selection unit, and a current driving unit. The control voltage unit generates a drive current and a control voltage. The mode selection unit receives the mode signal and outputs a mode selection signal. The current driving unit receives the mode selection signal, and selects to generate a mode selection current according to the mode selection signal. In some embodiments, the plurality of mode selection currents comprise first and second mode selection currents, wherein the current drive unit comprises first and second transistors having respective first and second aspect ratios, wherein the The first and second transistors drive a respective one of the first and second mode selection currents. The control voltage unit includes a current mirror circuit to generate the drive current. In addition, the first and second mode selection current magnitudes and the magnitude of the driving current are related to the first and second aspect ratios of the respective first and second transistors.

In some embodiments, the voltage drive unit includes a current mirror operational amplifier based regulator. In some embodiments, the voltage drive unit includes a plurality of stages, wherein the drive capability is determined by the level at which the mode signal is initiated.

In some embodiments, the voltage driving circuit further includes a second voltage driving unit. The second voltage driving unit is also coupled to the current bias generating unit, wherein the current bias generating unit generates a second mode selection current according to the mode signal, wherein the second voltage driving unit receives the second mode selection And outputting a current according to a second driving capability set by the second mode selection current.

In some embodiments, the voltage drive unit includes a plurality of stages, each of which drives an output voltage based on a respective mode signal, the resulting different drive capability.

Systems and methods for controlling the boosting speed in a bit line precharge operation in a semiconductor device are disclosed herein. Embodiments and methods disclosed herein may include embodiments that allow for varying rate of rise. The systems and methods disclosed herein include embodiments that allow for varying the rate of boost. Reducing the boost rate of the bit line precharge voltage value provides an effective way to reduce the unwanted coupling effect between the bit lines, thereby reducing or eliminating unintended voltage increases as shown in FIG. 1D. However, reducing the bit line precharge speed in order to reduce the undesired coupling effect between the bit lines also represents a slowdown in the operation speed of the memory. Therefore, if the coupling effect in operation is not a big problem or not a problem at all, the precharge speed can be increased. In the operation of the coupling effect, the pre-charging speed can be reduced.

2 is a block diagram showing an output voltage driving circuit 200 of a semiconductor memory device. In FIG. 2, the voltage driving circuit 200 includes a current bias generating unit 300 and a voltage driving unit 400.

The current bias generating unit 300 includes a plurality of mode selection currents I_SEL<1:n>. The mode selection current I_SEL<1:n> and the mode signal MODE<1:n> are one-to-one correspondence. Where n is an integer, preferably greater than one, and has at least two modes of operation. The operation mode represented by the mode signals MODE<1:n> corresponds to different driving capabilities to drive a precharge voltage V_pre. Therefore, the n operating modes can provide n different driving capabilities to drive the corresponding pre-charge voltage V_pre.

The voltage driving unit 400 receives the current output of the current bias generating unit 300, and outputs a precharge voltage V_pre according to the driving capability corresponding to the current of the current bias generating unit 300.

Figure 3 is a block diagram of a current bias generating unit that can be applied to the device of Figure 2. In FIG. 3, the current bias generating unit 300 may include a control voltage unit 310, a mode selecting unit 320, and a current driving unit 330.

The control voltage unit 310 provides a fixed control voltage V _CTL to the current drive unit 330. The mode selection unit 320 receives the mode signals MODE<1:n> and outputs the mode selection signals MODE_SEL<1:n> (OK). In some embodiments, the mode signal MODE<1:n> is an n-bit parallel data signal. In an alternate embodiment, the mode signals MODE<1:n> are a list of data. In some embodiments, current bias generation unit 300 can include circuitry to convert the serial pattern data into parallel pattern data.

The current driving unit 330 can receive a fixed control voltage V _CTL from the control voltage unit 310 and receive the mode selection signal MODE_SEL<1:n> from the mode selection unit 320. The current driving unit 330 can output a mode selection current I_SEL<1:n> and respond to a mode selection signal MODE_SEL<1:n> in a one-to-one correspondence. The current driving unit 330 may output a mode selection current I_SEL having one of a plurality of current classes corresponding to n types and each of the different current values corresponding to one of the n modes. Therefore, the current driving unit 330 detects which one of the n modes is selected based on the mode selection signal MODE_SEL<1:n>, and outputs its corresponding mode selection current I_SEL.

Fig. 4 is a circuit diagram of a current bias generating unit which can be applied to the apparatus of Fig. 3.

The control voltage unit 310 includes PMOS transistors Q1 and Q2, NMOS transistors Q3 and Q4, and a resistor R1. The sources of the PMOS transistors Q1 and Q2 are connected to a voltage source V _DD . The gate of transistor Q1 is coupled to the gate of transistor Q2 and to the output node of output voltage V _CTL . The gate of transistor Q2 is also coupled to the drain of transistor Q2. The drains of the NMOS transistors Q3 and Q4 are coupled to the drains of the transistors Q1 and Q2, respectively. The source of the transistor Q3 is coupled to the ground potential. The source of transistor Q4 is coupled to resistor R1, which is then coupled to ground potential.

In this embodiment, the ratio of width to length (W/L) is also referred to herein as the aspect ratio, and the width to length ratio of the transistor Q4 is larger than the width to length ratio (W/L) of the transistor Q3, assuming electricity The ratio of the width to length ratio (W _Q4 /L _Q4 ) of the crystal _{Q4 to} the width to length ratio (W _Q3 /L _Q3 ) of the transistor Q3 is K.

K=(W _Q4 /L _Q4 )/(W _Q3 /L _Q3 ) (1)

The width to length ratio (W/L) of the transistor Q3 is the same as the width to length ratio of the transistors Q1 and Q2.

When the PMOS transistors Q1 and Q2 match, the drive current Is is the same and can be expressed by equation (2)

Is=(VGS _Q3 -VGS _Q4 )/R (2)

In equation (2), VGS _Q3 is the gate-source voltage of transistor Q3, VGS _Q4 is the gate-source voltage of transistor Q4, and R is the resistance of resistor R1.

When the width to length ratio (W/L) of the transistor Q4 is larger than the aspect ratio (W/L) of the transistor Q3, and the ratio is K, according to the equation (2), the driving current Is can be further deduced as equation (3)

Is=(ζV _T )(lnK)/R (3)

In equation (3), ζ is a non-ideal parameter, which is the coincidence coefficient of the MOSFET when operating in the subcritical region. V _T is the thermal voltage (kT/q), where K is the Boltzmann coefficient, T is the absolute temperature, and k is The magnitude of the electron charge (Coulomb), K is the aspect ratio in equation (1), and R is the resistance value of resistor R1.

Thus, in this embodiment, control voltage unit 310 includes an NMOS current mirror comprised of NMOS transistors Q3 and Q4 that are coupled to a positive feedback loop comprised of PMOS transistors Q1 and Q2. The current mirror generates a drive current Is, which is determined according to the resistance value of R1 and the width to length ratio of the transistors Q4 and Q3. The control voltage unit 310 outputs a control voltage V _CTL , which is connected to the gates of the transistors Q1 and Q2 , and the current is controlled by the current Is. The current mirror in the current driving unit 330 provides different magnitudes of driving current output, and the details will be This is described in more detail below. Alternative embodiments may include other types of current drivers, such as other current mirror circuits.

This mode selection unit 320 includes first to nth mode switching transistors Q5 ₁ to Q5 _n using PMOS switching. The sources of the mode switching transistors Q5 ₁ to Q5 _n are connected to the voltage source V _DD . The drains of the mode switching transistors Q5 ₁ to Q5 _n provide mode selection signals MODE_SEL<1:n> to the current driving unit 330. The gate of the mode switching transistors Q5 ₁ to Q5 _n receives the mode signal MODE<1:n>. The mode signal MODE<1:n> controls the mode switching of the gates of the transistors Q5 ₁ to Q5 _n . For example, if MODE<1> is set to logic level "0", mode switching transistor Q5 ₁ will be turned on. If MODE<1> is set to logic level "1", mode switching transistor Q5 ₁ will shut down.

The current driving unit 330 includes first to nth current driving transistors Q6 ₁ to Q6 _n , using PMOS, and first to nth NMOS transistors Q7 ₁ to Q7 _n connected by a diode. The sources of the current drive transistors Q6 ₁ to Q6 _n are connected to the mode selection signals MODE_SEL<1:n> from the mode selection unit 320. The drains of the current drive transistors Q6 ₁ to Q6 _n are connected to the gates of the transistors Q7 ₁ to Q7 _n and the gates, respectively. The sources of the transistors Q7 ₁ to Q7 _n are coupled to the ground potential.

The gates of the current drive transistors Q6 ₁ through Q6 _n receive the control voltage V _CTL from the control voltage unit 310. Thus, each of the current drive transistors Q6 ₁ to Q6 _n outputs a respective mode selection current I_SEL<1:n>, which is mirrored with the drive current Is of the control voltage unit 310 according to the respective different ratios. In this embodiment, the ratio is controlled according to the respective aspect ratios of the current driving transistors Q6 ₁ to Q6 _n . That is, the width to length ratio (W/L) of each of the current driving transistors Q6 ₁ to Q6 _n can be designed such that the mode selection current I_SEL<1:n> is a certain ratio of the driving current Is. Therefore, the mode selection current I_SEL<1:n> can be adjusted to I_SEL<1>=(K ₁ )(Is), I_SEL<2>=(K ₂ )(Is), ,,,I_SEL<n>=(K _n ) (Is), get n different K _n values, 1>K>0.

The operation of the current bias generating unit 300 will be described below using an embodiment having four modes (e.g., n = 4), and the description is also applicable to other more or less modes. In the four mode examples, the mode signals MODE<1:n> are represented by a four-bit mode signal MODE<1:4>, and the mode selection unit 320 includes four mode switching transistors Q5 ₁ to Q5. ₄ . Further, the current driving unit 330 includes four current driving transistors Q6 ₁ to Q6 ₄ and four diode-connected transistors Q7 ₁ to Q7 ₄ .

Operating in a parallel manner, the gate of the first mode switching transistor Q5 ₁ receives the first bit MODE<1>, and the gate of the second mode switching transistor Q5 ₂ receives the second bit MODE<2>, the third The gate of the mode switching transistor Q5 ₃ receives the third bit MODE<3> and the gate of the fourth mode switching transistor Q5 ₄ receives the fourth bit MODE<4>.

In this embodiment, the received one of the mode signals MODE<1:4> may be "0111", such that the gate of the first mode switching transistor Q5 ₁ receives "0" as the first bit MODE<1>, The gate of the second mode switching transistor Q5 ₂ receives "1" as the second bit MODE<2>, and the gate of the third mode switching transistor Q5 ₃ receives "1" as the third bit MODE<3> and The gate of the fourth mode switching transistor Q5 ₄ receives "1" as the fourth bit MODE<4>. In this example, the first mode switching transistor Q5 ₁ will be turned on and the remaining mode switching transistors Q5 ₂ to Q5 ₄ will be turned off. More or fewer mode switching transistors Q5 may be included in alternative embodiments.

At the same time, the control voltage unit 310 receives the voltage source V _DD and outputs the control voltage V _CTL to the gates of the current drive transistors Q6 ₁ to Q6 _n . However, since only one mode switching transistor Q5 ₁ is turned on, only the mode selection current I_SEL<1> is generated. The current value of the mode selection current I_SEL<1> is a certain ratio of the drive current Is, which is set according to the width to length ratio of the current drive transistor Q6 ₁ . According to the desired output current value, in the same way, the mode signals MODE<1:4> can select the mode selection current I_SEL<1:4>, respectively.

Fig. 5 is a circuit diagram of a voltage driving unit 400, which can be applied to the apparatus of Fig. 2. The circuit shown in Figure 5 includes a current mirror op amp based regulator. In an alternate embodiment, voltage drive unit 400 can also be an operational amplifier based on a folded-cascode operational amplifier or other similar configuration.

The voltage driving unit 400 includes a plurality of transistor groups Q8 to Q21. The transistor groups Q8 to Q21 include PMOS transistors Q8 _1-n , Q9 _1-n , Q12 _1-n , Q13 _1-n , Q15 _1-n , Q16 _1-n , Q18 _{1-n ,} and Q19 _{1-n .} And NMOS transistors Q10 _1-n , Q11 _1-n , Q14 _1-n , Q17 _1-n , Q20 _{1-n ,} and Q21 _1-n . Each of the transistor groups Q8 to Q21 has n transistors in which n and n bit mode signals MODE<1:n> and mode selection currents I_SEL<1:n> are the same.

The gate reception mode signals MODE<1:n> of the transistors Q8 _1-n , Q11 _1-n , Q12 _1-n , Q13 _1-n , Q15 _1-n , Q18 _{1-n ,} and Q21 _1-n . The connection is as follows, each of the gates of the transistors Q8 _1-n receives a corresponding mode signal MODE<1:n> bits, and each of the gates of the transistors Q11 _1-n receives a corresponding mode signal MODE <1:n> bit, each gate of the transistors Q12 _1-n receives a corresponding mode signal MODE<1:n> bit, and each of the transistors Q15 _1-n receives a corresponding one The mode signal MODE<1:n> bits, each of the transistors Q18 _1-n receives a corresponding mode signal MODE<1:n> bit and each of the transistors Q21 _1-n The pole receives a corresponding mode signal MODE<1:n> bit.

The gates of transistors Q9 _1-n are connected to the gates of transistors Q13 _1-n and also to the drains of transistors Q13 _1-n . The drains of the transistors Q13 _1-n are also connected to the drains of the transistors Q14 _1-n . The gates of transistors Q10 _1-n are connected to the gates of transistors Q20 _1-n and also to the drains of transistors Q10 _1-n . The sources of the transistors Q10 _1-n are connected to the drains of the transistors Q11 _1-n . The gates of transistors Q14 _1-n are connected to an output node between the drains of transistors Q19 _{1-n and} the drains of transistors Q20 _1-n . The gates of transistors Q16 _1-n are connected to the gates of transistors Q19 _1-n and also to the drains of transistors Q16 _1-n . The drain of the transistor Q16 _1-n is also connected to the drain of the transistor Q17 _1-n .

The gate of the transistor Q17 _1-n receives a reference voltage V_ref. This may be the same reference voltage V_ref expected output voltage V_ _Pre. This reference voltage V_ref can be generated using an energy gap or other type of voltage reference circuit.

The sources of transistors Q14 _1-n and Q17 _1-n are connected to a current source CS, which represents the mode selection current I_SEL<1:n>. In other words, the sources of transistors Q14 ₁ and Q17 ₁ are connected and receive I_SEL<1>, the sources of transistors Q14 ₂ and Q17 ₂ are connected and receive I_SEL<2>, and so on to the remaining n transistors. And current source.

Like the transistors of the current drive unit 330, the voltage drive unit also has many different aspect ratios. In particular, therefore, each of the transistors 1-8 in the transistor groups Q8 to Q21 may have respective aspect ratios, providing respective output driving conditions I _out /C _out , where I _out is the output current And C _out is the output load capacitance. The voltage V_pre driven at the output node is driven with a different driving capability SR according to the 1-n different stages activated by the mode signals MODE<1:n>. In some embodiments, the voltage V_pre can be a voltage used to precharge a memory device control line. For example, voltage V_pre can be a control voltage used to precharge a bit line in a flash memory device. Each level 1-n provides one of the different currents I _out1-n at the output node. The driving capability of the output voltage V_pre can thus be expressed as I _out /C _out , where I _out is the same as one of the currents I _out1-n depending on which stage is activated. Therefore, if the coupling effect is less important or not a problem at all in the operation of the memory device, by increasing _Iout , the driving ability of the voltage V_pre can be increased, resulting in a transition having a generally steeper degree as in the 1D. Conversely, when the operational coupling effect of the memory device is to be considered, the driving ability of the voltage V_pre can be lowered by the control mode signal MODE<1:n>, which can result in a transition that is generally slower as in FIG. Reduce or eliminate unintended voltage values as shown in Figure 1D

The corresponding current I _{out1-n of} each stage 1-n of the voltage driving unit 400 can be changed according to the aspect ratio of the respective transistors in 1-n. That is, the W/L ratio of each of the current driving transistors Q<8-21> ₁ to Q<8-21> _n is designed such that each of the output currents I _out1-n is the driving current Is of the control voltage unit 310, respectively. a certain percentage.

It is to be understood that many different alternative embodiments can be practiced without departing from the spirit of the invention. For example, referring to FIG. 7, an alternative voltage drive circuit 200' is shown that is substantially similar to the previously described voltage drive circuit 200 except that the voltage drive circuit 200' includes a multiple voltage drive unit 400'a to 400'n outside. These voltage driving units 400'a to 400'n receive one bit corresponding to the respective mode signal MODE<1:n>. Further, each of the voltage driving units 400'a to 400'n receives one of the respective mode selection currents I_SEL<1:n>. These voltage drive units 400'a through 400'n operations may operate similar to the previous voltage drive unit 400 except that these voltage drive units 400'a through 400'n are single stage multiple rather than a single multiple stage. Further, each of the voltage driving units 400'a to 400'n includes a group of transistors corresponding to each having a different aspect ratio. Therefore, in the embodiment shown in Fig. 7, the multiple voltage driving units 400'a to 400'n are included instead of the single one voltage driving unit 400. Since each of the voltage driving units 400'a to 400'n respectively includes a group of transistors each having a different aspect ratio, the voltage driving units 400'a to 400'n of each can output voltages having different driving capabilities. V_pre. These voltage driving units 400'a to 400'n are activated by respective corresponding bits in the mode signals MODE<1:n>, and output a voltage V_pre. The outputs of these voltage driving units 400'a through 400'n are coupled to an output buffer 500 to output a voltage V_pre received from any one of the voltage driving units 400'a through 400'n. This output buffer 500 can include a serial three-state output buffer that is sufficient to receive and output signals from any of the voltage drive units 400'a through 400'n.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the details thereof. Other alternatives and modifications may be contemplated by those skilled in the art. In particular, all of the components that are substantially identical to the present invention are combined to achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to fall within the scope of the invention as defined by the appended claims and their equivalents.

100. . . Flash memory device

102. . . Memory array

104. . . Column decoder

106. . . Source line control circuit

108. . . Sense amplifier

110. . . Bit line driver

200. . . Voltage drive circuit

300. . . Current bias generating unit

310. . . Control voltage unit

320. . . Mode selection unit

330. . . Current drive unit

400. . . Voltage drive unit

500. . . Output buffer

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments will be described in the following sections of the embodiments, in which:

Figure 1A is a block diagram of a typical NAND flash memory device.

Figures 1B and 1C show the clamped transistors used in the pre-charge and sense amplification of the NAND flash memory device shown in Figure 1A.

Figure 1D shows the signals associated with the clamped transistors shown in Figures 1B and 1C.

2 is a block diagram of an output voltage driving circuit of a semiconductor memory device.

Figure 3 is a block diagram of a current bias generating unit that can be applied to the device of Figure 2.

Fig. 4 is a circuit diagram of a current bias generating unit which can be applied to the apparatus of Fig. 3.

Fig. 5 is a circuit diagram of a voltage driving unit, which can be applied to the device of Fig. 2.

Figure 6 shows the signals associated with the clamped transistors driven by the output voltage drive circuit shown in Figure 2.

Figure 7 is a block diagram of an output voltage driving circuit of a semiconductor memory device in accordance with an alternative embodiment.

200. . . Voltage drive circuit

300. . . Current bias generating unit

400. . . Voltage drive unit

Claims (21)

A voltage driving circuit includes: a current bias generating unit that receives a mode signal and generates a mode selection current in response to the mode signal; and a voltage driving unit coupled to the current bias generating unit, the voltage driving unit The mode select current is received and a drive capability set by the current is selected to drive the output voltage. The circuit of claim 1, wherein the mode signal comprises n bits, where n is an integer greater than one. The circuit of claim 2, wherein the voltage driving unit further receives the mode signal. The circuit of claim 3, wherein the voltage driving unit receives the mode selection current and drives the output voltage according to the driving capability determined by one of n operating modes, wherein each of the n operating modes Have a separate drive capability. The circuit of claim 1, wherein the current bias generating unit comprises: a control voltage unit that generates a driving current and a control voltage; and a mode selecting unit that receives the mode signal and outputs a mode selection signal And a current driving unit that receives the mode selection signal and selects one of a plurality of possible mode selection currents based on the mode selection signal selection. The circuit of claim 5, wherein the plurality of mode selection currents include And a second mode select current, wherein the current drive unit comprises first and second transistors having respective first and second aspect ratios, wherein each of the first and second transistors is configured to be driven One of the respective first and second mode selection currents. The circuit of claim 6, wherein the control voltage unit comprises a current mirror circuit to generate the drive current. The circuit of claim 7, wherein each of the first and second mode selection currents has a magnitude of the drive current and the first and second widths of the respective first and second transistors Longer than related. The circuit of claim 1, wherein the voltage driving unit comprises a current mirror operational amplifier based voltage regulator. The circuit of claim 9, wherein the voltage driving unit comprises a plurality of stages, wherein the driving capability is determined by a level at which the mode signal is activated. The circuit of claim 1, further comprising a second voltage driving unit coupled to the current bias generating unit, wherein the current bias generating unit further generates a second mode selection current according to the mode signal. The second voltage driving unit receives the second mode selection current and drives the output voltage according to a second driving capability set by the second mode selection current. A voltage driving circuit comprising: a current bias generating unit that receives a mode signal and generates a mode selection current in response to the mode signal; A voltage driving unit is coupled to the current bias generating unit, the voltage driving unit comprising a plurality of stages, each stage driving the output voltage according to the mode selection signal in one of a plurality of different driving capacities. The circuit of claim 12, wherein the mode signal comprises n bits, where n is an integer greater than one. The circuit of claim 13, wherein the voltage driving unit receives the mode signal. The circuit of claim 14, wherein the voltage driving unit drives the output voltage according to one of n different driving capabilities, wherein each bit of the mode signal and one of the n different driving capabilities correspond. The circuit of claim 12, wherein the current bias generating unit comprises: a control voltage unit that generates a driving current and a control voltage; and a mode selecting unit that receives the mode signal and outputs a mode selection signal And a current driving unit that receives the mode selection signal and selects one of a plurality of possible mode selection currents based on the mode selection signal selection. The circuit of claim 16, wherein the plurality of mode selection currents comprise first and second mode selection currents, wherein the current drive unit comprises a first and a first and a second aspect ratio a second transistor, wherein each of the first and second transistors drives a respective one of the first and second mode selection currents. The circuit of claim 17, wherein the control voltage unit comprises a current The mirror circuit generates the drive current. The circuit of claim 18, wherein each of the first and second mode selection currents has a magnitude of the drive current and the first and second widths of the respective first and second transistors Longer than related. The circuit of claim 12, wherein the voltage driving unit comprises a current mirror operational amplifier based voltage regulator. The circuit of claim 20, wherein each stage of the voltage driving unit comprises at least one transistor having a respective different aspect ratio, wherein the driving capability of each stage and the respective one of the at least one transistor The width to length ratio is related.