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TWI326113B - A method of forming a silicon oxynitride film with tensile stress - Google Patents

A method of forming a silicon oxynitride film with tensile stress Download PDF

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Publication number
TWI326113B
TWI326113B TW095134919A TW95134919A TWI326113B TW I326113 B TWI326113 B TW I326113B TW 095134919 A TW095134919 A TW 095134919A TW 95134919 A TW95134919 A TW 95134919A TW I326113 B TWI326113 B TW I326113B
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Taiwan
Prior art keywords
film
forming
sinc
substrate
porous
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TW095134919A
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English (en)
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TW200717653A (en
Inventor
John Gumpher
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Tokyo Electron Ltd
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/308—Oxynitrides
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36—Carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
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    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
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    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
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    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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Description

1326113 九、發明說明： 【發明所屬之技術領域】 ，發_於半輯縣，尤其_在薄财具有高 g乳切膜及包含高拉伸應力氮氧化賴之半導體裝=开】成 【先前技術】 體雷ϊΐ'駭氮切基細e廣泛驗料财置與超大型積 ，電路中。例如’氮化石夕膜已廣泛使用於半導體裝置中^ ^ 2擴散阻障層、作為在微細特徵部之蝴期間的ϋ、 作為封裝製造裝置之最後鈍化膜等。 r膜、 I利用各種處理魏與處理氣體、在低壓或絲壓力下 Ϊ將^ °例如’這些處理系統可進行熱化學氣相沉積dD)、 ，水==ir^(PECVD)、或遠端PECVD。在遠端pe⑽ :待處理之基板並未設置成直接與㈣接觸 =下二處。例如裝置品質氮化_由 丄、= 之PECVD、或利用二氯石夕垸(SiH2Cl2)與NH3之敎 況。已之氮化頻財歧壓縮錄伸應力情 It 應力自難健CVD(LPCVD)膜之約 Γ帕斯卡)的拉伸性變化至PECVD及具有高摻 雜質濃度之低溫膜的壓縮性。 發明補式金屬氧化物半導體(CMC)S)電晶體效能之新近 與現行超大型積體電路(ulsi)技術相容之應力陶兗層 而言’負金屬氧化物半導體卿0s)電晶體之通 322=可經由在M0S電晶體之通道區域上導入拉伸單轴 二ί古·予以增加。典型上，此舉已藉由在源極/汲極區域上 =，、U力氮化梦以作為罩蓋層加以實現。為了達成期望應 或等於約UGPa之拉伸級應力等級。如此沉積之氮 力更可藉由曝露於紫外(UV)光而增加，但此法需 硬體以便處理這些薄膜。雖然可開發適合此應用之其 5 113 113 之 材料’但由於氮化矽與氮化矽基底材料與現行製造處理 祁谷性，所以係為較佳材料。 【發明内容】 ⑸mtt㈣之—實施射，綱具有高⑽應力讀氧化賴 赤非、τ .的形成方法。本發明所產生之氮氧化矽膜可為平面型 ^非平_’例如在半導财置之MQS_上卿成的氮氧化石夕
廿胺本發明之一方法包含在基板上沉積一多孔SiNC:Ii膜， =將^夕孔SiNC:H膜暴露於含氧氣體以將氧植人該沉積SiNC:H 、而形成密度大於該多孔SiNC:H膜的緻密Si〇NC:H膜。在 之—實施例中’緻密Si〇NC:H膜之拉伸應力係料或大於 约 1.5GPa 〇 根據本發明之一實施例，可從包含雙（第三丁 ，)(btBAS)與_H3)之處理氣體來沉積多孔siNc:H膜，且^ f孔slNC:H膜暴露於含氧氣體，同時使基板溫度維持在約 500 C與約800X之間，例如55(rc。 寸Μ ，，發明之另-實施例’緻密Si〇NC:H膜可在包含半導體 2 土板上加以形成，因而形成包含緻密8ίΟΝ(：··Η膜之半導濟 ^置。該緻密SiO肥Η膜可具有等於或大於約丨鳥 =
Si〇NC:H膜之基板更可包含形成於基板 摻雜區域與閘極堆疊。 v 祕tfl解本發明之前述大略說明與下列詳細說明皆為示範 性，並非本發明之限制。 πτ乾 當由參考下列詳細說明而結合附圖加以考慮時，將 對本發明之更完整了解及其許多伴暖點。 又亏 【實施方式】 了促進對本發明之完整了解’以及就 之目的而非限制性者’將提出特定細節如 定結構、批次處理系統之幾何、以及各種元件之說
LU ^應了解本發明可在與特定細節不同之其他實_中加以施 如在此所使时，氮切_為_ 包含石、氮⑼、碳(C)、及酬。^ = 5 自前趨物與—含氮氣體加以也Ϊ =該siNC:H膜可自含有bis(第三丁基 t:，情況’氮氧化頻在此稱為‘ Η =二 與=ο>^、=、〇、^τΗ疋素的原子漢度上變化。該記號SiNC:H “雜質人旦偷為例’係存在於那些膜層中的摻雜質。Η 發f f Γ 例如’ 10至25原子百分比的氫。本 ϊ石f氮氧化石夕膜亦可為僅具有微量氯之薄膜。 圖/ΐί目ΐ : ϋ相同參考符號代表貫穿數張圖示，尤其是 圖之相冋、或相付合之元件，圖i係根據 ：^^〇S/；〇£〇 Si〇NC：H ^ 122 之衣置100，除了該緻緻密Si〇NC:I^ 122之外，還包含 雜區域113與114(如源極與汲極）、一閉極堆 二 間1W件12卜例如，基板112可為Si、Ge、Si/Ge、 j GaAs^板晶圓。基板112可為任意大小，例如細麵基板、 300mm基板、或甚至更大基板。 入带，極堆4 120包含一介電層116,位於通道區域115上。例如， :甘/ i】6可包含二氧化石夕層(如Si〇2)、氮化石夕層、氮氧化石夕層、 、或其他任意適合材料。介電層116更可包含-高介電 ㊉數Ο-k)介電材料。例如，高士介電材料可包含金屬氧化物與1 =夕酸鹽’包含·· Ta2〇5、Ti〇2、Zr02、Ai203、Y2〇3、HfSi〇x、Hf〇2、 f02、ZrSiOx、TaSiOx、SrOx、SrSiOx、LaOx、LaSiOx、Y〇x、或 YSiOx、或其兩者或更多組合。 ； 在本發明之一實施例令，在介電層116上形成一導電層117(如 1326113 卹^ / 7電祖。可將罩蓋層119設置於閘極堆疊120之了音 I2G。例如，罩蓋層⑽可為氮切(如_4、' 1·Η)或氮氧^矽(如 Si〇N、Si〇NC:H)層。 ^本發明之—實施例中，導電層117可為摻雜多晶 二11’石夕化物層118可為石夕酸鶴。根據本發明，閘極堆疊120 g =不同於圖i所示或比圖i少或更多的膜層。在一
金屬閘極層取代層117及/或118。圖1更顯示出間隔件J 沪^成於閘極堆疊丨20之每一側上，以便保護閘極堆疊120免於 ^傷且確侧極之電缝。此外，可利關 ^: :以=s裝請之源極與及極113、114。或者為在更： 之一實施例中，可使用一個以上之間隔件121。 月 在本發明之-實施例中，農置100可為一 NM0S 中-緻緻密SiONC:H膜m經由在該通道區域115上引 ^ 力而增加通道載子遷料。舰密Si〇NC:H ^ ⑽的鈍倾.根據本發狀—實_，舰密 122具有等於或大於約匕咖之拉伸應力。根據本發明之另一* 施例，該SiONC:H膜122具有大於約但小於約3 〇哪二 拉伸應力。在'緻密SiONC:H膜中的拉伸應力之變化可為+八〇1側。 圖2係根據本發明之-實施例，形成具有拉伸應力之化 :膜，，：圖3A至3C說明就SiNC:H膜沉積之做為處理時 間函數之基板溫度㈣化H㈣在隨後形成具 緻密SiONC:H膜。 浅'狀 現參考圖2與圖3A，處理200包含步驟2〇2，該步驟 理系統之處理室中設置-基板。例如，該處理系統可為一圖 示之批次處理系統卜或者’該處理系統可為—單晶處理系統 如，該基板可為-半導體基板’如#基板、鍺化魏板 、 玻璃基板、LCD基板、或一複合半導體基板，如GaAs。兮^ 包含各種主動裝置及/或隔離區域。再者，該基板可包含^孔或 8 1326113 溝渠或其組合。根據本發明之一實施例，該基板可包含一閘極堆 疊，如圖1所示之閘極堆疊1Π與118。
在步驟202中’在處理室中設置該基板，在圖3A之時段期 間將该基板加熱至第一基板溫度T!。可考慮整體熱預算與考慮具 有期望性質之SiNC:H膜的實際沉積速率來選擇第一基板溫度 Τι，戎期望性質包含多孔性、元素的構成、密度等。根據本發明 之一實施例，第一基板溫度丁丨可介於約500°C與約80(TC之間。 用於沉積SiNC:H膜之溫度變化可小於+/_2〇°c。或者，第一基板 溫度T!可介於約525°c與約575〇c之間，例如55(Γ(：。如圖3A
所示，時段tl可為一轉換步驟，例如可具有介於約2min盥約丨5min 之間的期間。 ~ .隹步驟204中，在時段b期間，在LPCVD製程中，將一多孔 膜沉積在基板上。根據本發明之一實施例，可藉由將基板 暴露於有機矽烷氣體與含氮氣體之處理氣體來沉積SiNC:H膜。根 據本，明^一實施例’該有機矽烷氣體可為例如上述之btbas氣 體’该含氮氣體可為例如叫。該處理氣體可包含 =比例大於的BTBAS與_。在本發明之另一實施 例中’BTBAS. NH3比例可介於約2:1與約8:1之間。在BTBAS: ，，變化可為仏5%。上述BTBAS:NH3比例僅為示範性，且 f生其他btbas: NH3比例。由於期望沉積具多孔 mu，性緻密化的氮化賴，雖然上述既定比例較 ί可，多孔漏c:h膜沉積之任意比例的有機 /況孔體，、3亂軋體一般而言均可採用。 ^驟2(H期間’可將處理室壓力維持在約。。5 τ。讀約2〇〇 〇ΓΓ a可就批次與單晶元處理兩者使用此處理室壓力範圍。 S在=處1系統中或在單晶圓處理系統中的處=可 f f約饥⑽與約抓⑽之間’例如約O.STorr。在SiNC:H膜 間之處理㈣力的變化可為+/_5%。處規 定處理狀況下純妨—段日Η1喊生财射厚it 9 1326113 把戸、把例中’直接進行貫驗及/或藉由實驗設計法 (DOE)可精調用以沉積多孔siNC:H膜之製程處方。 雖然對本發明並非必要，但在本發明之—實施例中，在義板 膜之後’在步驟2〇6中，在時段^期間將基板自 Τ ίίΓί Tl加熱至大於第—基板溫度Tl之第二基板溫度 I。根據本發明之一實施例，第二基板溫度I可介於約·。c斑 ^間。或者’第二基板溫度丁2可介於約525°C與約57^ 1之間。在一例子中，乃與I可約55(rc。在 積SiNCH膜期間所用的溫度變化可為+M(rc、▲氧退二 則溫度變化為+/_5。(：。 在本發明之一實施例中，在時段^之前或期間 =以自處理室移除CVD步驟綱之處理氣體 步驟’且取決於系統設計與沉積步驟204在第—H3产為τ ^ ί^Γ$-τ=Βΐ；Γ處理溫度差異’而可加以變化時間1短。根 =Τ2，如，時段t3 可介 必要者。 ^物&在本發权各種實蘭中並非 -人ίΓίί6::在第二基板溫度丁2將多孔siNc:H膜暴露於 膜i敏密Si〇ic:I^4在一 密度大於該多孔別腦 SiONC:H膜具有大於約〗5Γ X之^戶'施例中，所產生之緻密 例，含氧氣體ί為空氣/二之在拉根據本發明之—實施 於含氧氣體，俾使該膜氧中’將該夕孔SiNc:H膜暴露 加拉伸應力。 、乳化…致岔化，因而在所產生之薄膜中增 處理室壓力變化可為⑶NC:H膜期間所用的 在規定處赚況Tit行―p t板暴路魏化處理氣體之步驟可 仃奴％間，而產生具有期望拉伸應力等級 1326113 之 SiONC:H 膜。 根據本發明之-實施例，可在沒有錢之情 5=1此舉允許接近閘極堆疊之通道區域之拉伸應力 明之二口 -而無來自電毁之潛在基板損傷及/或充電效應。在本發 m m發明之另-實施例，可湘遠端賴源進行氧化步驟 二包基?f ^祕觸編爾置， 系統係繪城電_之示範性批次處理 ^有期望拉伸應力之Si0NC:H膜已形成於 來’隨後自處理室移除該基板。在自處理室 板後’測量所產生之緻密Si0NC:H膜之拉伸應力。如同 =又_^ t3 ’日守段t5為一轉換步驟且可變化時間長短。例如 =於約2min與i5min之間’但這在本發明之實施例中並非 雖ϊϊ示於圖2中，可在處理之步驟間進行沖洗步驟。 扞产王驟204與暴露步驟206之間的時段。期間，可進 潘二f之!Γί:以自處理室移除沉積氣體而使基板表面保持乾 者二二體可包含4、惰性氣體如Ν2、或稀有氣體。再 驟。° H先氣體流動之泵抽步驟取代或補充—或更多沖洗步 八施2之處理流程中的每—步驟或階段，皆可内含一或更多 j步驟及/或操作。因此，吾人不應將在步驟2〇2、綱、施中 ，引用之3項步驟限為本發明所僅使用者。而且，每—代表 或階段202、204、206並不應限為單一處理。 j據本發明之-實施例’可將步驟2〇4與施以所需而加以 重複數次，以形成必要厚度之Si〇N〇H膜。例如，可施行一次步 1326113 驟204與j〇6以提供具有厚度介於約5nm與約5〇nm之間的第一 Sl〇NC:H膜。然後再重複步驟204與206以在第一 SiONC:H膜上 形1第二Si〇NC:H膜。藉由重複步驟204與206，可將SiONC:H 膜製成任意厚度，如約l〇nm至約i〇〇〇nm。所產生之si〇NC:H膜 之厚度變化可為+/_5〇/〇。 _圖3B係就SiNC:H膜沉積與就隨後形成緻密SiONCH膜而 . S，做，處理時間函數之基板溫度的變化圖。根據圖3B所示之實 施例，第二基板溫度A大於第一基板溫度Τι。在圖3β中，由於 基板溫度在步驟204與206之間增加之故，轉換時段t3可長於圖 _ 3A中的轉換時段V例如’ΤΊ可約為500°C而T2可約為550°C。 在另一例中，Τι可約為550°C而&可約為60(TC。在沉積步驟期 j，在處理SiNC:H膜與所產生之Si〇NC:H膜之溫度期間的基板 溫度變化可為+/·1〇γ，而在氧退火期間之基板溫度變化可為+/·5。 C 〇 _圖、3C係就SiNC:H膜沉積與就隨後形成緻密Si0NC:H膜而 5，做為處理時間函數之基板溫度的變化圖。根據圖3C所示之實 施例，第二基板溫度丁2低於第一基板溫度Tl。在圖3C中，由於 基板溫度在步驟204與206之間降低之故，轉換時段〖3可長於圖 3A中的轉換時段t；}。例如，T,可約為600°C而T2可約為550°C。 • 在另一例中，t可約為55(TC而1：2可約為5〇0°C。 示範性範例： ,在本發明之緻密薄膜的一範例中，SiNC 膜係藉由在LPC VD _ 製程中將基板暴露於BTBAS與NH3而加以沉積。此例之沉積壓 • 力為0.5ΤΟΠ·。BTBAS:NH3氣流比例為4:1與8:卜就4:1流量比而 。’ BTBAS流1為lOOsccm而NH3流量為25sccm。就8:1流量比 而言’ BTBAS流量為lOOsccm而ΝΉ3流量為ujsccm。將該基板 維持在550°C之溫度。該沉積SiNC:H臈呈現範圍自約57〇MPa 至約760MPa之中等壓縮應力。接著，在或接近55(rc之SiNC:H 膜沉積溫度下，將該沉積SiNC:H膜暴露於空氣，以形成緻密 >丄丄j 射係數列，，但在暴露於空氣時，薄膜折 為減少微孔之氧植 化學f互相侧，造成其作用 強化，將產⑽職網絡緻密化與 緻密SiONC:H膜 力4級乾圍自約“咖至約2觀的 中將厚之SiNC__由在lpcvd製程 之j Ϊ暴露於BTBAS與丽3而加以沉積。此例 NH ^曰AS:NH3氣體流量比為1:2(亦即相對高
BTBAS ^4) ° -BTBAS 二iiiii f之’:11膜(八膜）’表示較少補獲之沉 $ 2與較大之膜密度。SiNC:H膜之沉積及隨後將siNc:H膜 暴路於工糾形成SiONC:H難在55(TC之基板溫度下進行。 ^SlC>NC.H膜之二次離子㈣儀(SIMS)深度輪廓顯示 4A(亦即A膜者；)與圖犯(亦即B膜者〕。圖4八顯示A膜之〇 信號510、Η信號512、及〇信號514 ;圖4B顯示B膜之c信號 520、Η信號522、及〇信號524。A膜具有12GPa之拉伸應力， 而B膜具有2_3GPa之較大拉伸應力。比較圖4A之氧信號514與 圖4B之氧信號524發現：在空氣暴露期間，多孔B膜^具°有較/高 氧水平與較高氧濃度梯度輪廓(亦即參見區域516)，而較少多孔A 膜則顯示較少氧植入(亦即參見區域526)。 本發明人發現：由多孔SiNC:H膜所形成之緻密si〇NC:H膜 會受到多孔SiONC:H膜内之氧擴散之影響；再者，本發明人發現： 在罪近SiONC:H膜表面約50nm區域中，氧會更有效地植入由 BTBAS與NH3所沉積的SiNC:H膜内。然而，根據本發明之一實 施例’厚度大於約50nm之高應力SiONC:H膜可經由多沉積/氧化 循環加以形成。
丄丄丄J 製造所採用::2=1施⑦j行，體電路(ics)之
"υΓί J 系統的簡單方塊圖，處雜板狀批次處理 理系統i包含-所示，批次處 排氣管80之上端23、及〇/1 s 25，處理官25具有連接於 管2的庐甚n 及下知24，以密封方式接合於圓柱形歧 i 88 lf/么排氣f 8G自處理管25將氣體排至—真空泵抽ί 力。用來支^ 中轉—規定域壓或低於大氣壓之壓 板(晶圓)4G之基板支座35係以層疊方式(以 逵上，該旋轉擾係絲於一穿過遮蓋27且由馬 之旋轉軸21上。旋轉檯26可在處理_加以旋轉， 遮案均勻性’或者，旋轉檯可在處理綱保持靜止。 3ίΓα! ' 升降11 22上，用以使基板支座35自處理管25 t f出。*遮蓋27係處於其最高位置時，遮蓋27係用來關閉 歧官2之開口端。 如圖5所示’一氣體輸送系統97係用以將氣體通入處理室1〇 =—。y將複數個氣體供應管繞著歧管2加以排列，以將複數氣 體經，該氣體供應管供人處理管25。在圖5巾，僅顯示複個氣體 管中的—氣體供應管45。所顯示的氣體供應管45係連接於第 :氣體源94。一般而言，第一氣體源94可供應處理基板4〇用之 ^體’包含⑴有機矽烷氣體與含氮氣體，用以將多孔SiNC:H膜 此積至基板40上，以及包含(2)含氧氣體，如空氣、〇2、h2〇、或 〇3，用以氧化多孔SiNC:H膜。 或者或此外，可自（遠端)電漿源95供應一或更多氣體，將該 電襞源95運作為藉由氣體供應管45而連接於第二氣體源96與處 理室10。藉由氣體供應管45將電漿激化氣體通入處理管25。例 如，電漿源95可為一微波電漿源、一射頻(RF)電漿源、或由光照 14 1326113 射啟動之電漿源。在微波電聚源之例子中 fs(3w〇r r:v?(w)^ ^--- «料為由位於 源，型號為ΑΧ蘭。，職之嶋儀器所製造的下游電漿 叫射鏡Γ ’以便覆蓋處理管25。熱反射鏡 頂部加熱器、及排氣管===== 加熱器65、 =卻水，顯示)係形成於 =〇射之 、及15可織4G之就特在例如約20 力控制器(Wt ’直ί |:1686、— 八_、及-自動廢 每秒厕G升(或更^乾泵抽，高達 =系統97之氣體供應管45將氣體通入處:室 ===以前驅物材料與副產物自處理 粒计數态。控制器9〇可包令料虛甲哭 ’貝曰饿 ί：?；；Γ"4ίΙ"^1 系統97、控f广絲接於氣體輸送 及真空泵以:…、 PRECISION WORKSTATioN^；!^^ 腦底處理器、數位信號處理器等加以“，其使ί 驟’執行包含於電腦可讀媒體巾之—或H =步 令。電腦可讀媒體或記憶體制以保留根據本發明之教^而= 1326113 ί=?ίΗ:Λ用，儲存資料結構、表格、記錄或在此所述之 ^辟、可5胃媒體之範例為辆、硬碟、軟碟、卡帶、磁 Λ M + S PR〇M、EEPR〇M、快閃 EPROM)、DRAM、SRAM、 體、，Y、f ί磁性媒體、光碟(如CD_R〇M)、或任何其他光媒 哎任了叮豆；:氏帶、或其他具有孔洞、載波(以下說明)之物理媒體、 或任何其他電腦可自其讀取之媒體。 7^^控制器9〇相對於處理系統1而局部性地加以設置、或可 路或内部網路而相對於處理系統1加以遠端設置。因 一 斋9〇可利用直接連線、内部網路、及網際網路其中至少 ^裝/製=^^料_；1使控制器90與客戶端之内部網路 商專連線、或與設備商之内部網路(亦即設備製造 "二/再者，使另一電腦(亦即控制器、伺服器等)透過直接連 ί換=網路、及網際網路其巾至少—者而得轉取控制器90以 顧-應=崎於圖5之批次處理系統1僅以示範性目的而加以 ίΓ L為可彻特定硬體之許多變化來施行本發明。例如，圖5 ΐίΐί =小之基板’如2GG_基板、細臟 或f至更大之基板。再者，處理系統！可同時處理多達約· 土扳或更多基板。或者’處理系統可同時處理多達約25片基板。 廡六可根據本發明之實施例、利用單晶沉積系統來形土成高 應力虱氧化矽膜。單晶沉積系統之一例係說明於2〇〇4年9月％ 日提出申請之美國專利”㈣11/711721號 METHOD F0R forming a THIN c〇^ ^mviTY祖〖冨咖」，物_併 可依照以上教示進行本發明之各種修改與變化。因此，五人 需了解在所附申請專利範圍之範疇内，本發明可以有別於在&所 特別說明者加以施行。 16 【圖式簡單說明】 ，1係根據本發明之—實施例，概略顯示包含具有拉 之亂乳化石夕膜之MOS裝置的橫剖面圖。 甲-力 欲根據本發明之—實施例，縣具有拉伸應力之氮氧化 矽犋的處理流程圖。 右含f 3A、3B及3C係根據本發明之各種實施例，顯示就形成具 U拉伸應力之氮氧化矽膜而言，做為處理時間函數之基板溫度 的變化圖。 圖4A/與4B係顯示氮氧化矽膜用 之SIMS深度輪廓圖。
圖5係根據本發明之一實施例之批次處理系統的概略圖。 【主要元件符號說明】 1〜批次處理系統 2〜歧管 10〜處理室 15〜頂部加熱器 20〜主加熱器 21〜旋轉軸 22〜升降機 23〜上端
24〜下端 25〜處理管 26〜旋轉檯 27〜遮蓋 28〜馬達 30〜熱反射器 35〜基板支座 40〜基板 45〜氣體供應管 65〜底部加熱器 17 1326113 75〜感應器 80〜排氣管 82〜自動壓力控制器(APC) 84〜阱 86〜真空幫浦 88〜真空泵抽系統 90〜控制器 • 92〜製程監測系統 94〜第一氣體源 95〜電漿源 • 96〜第二氣體源 97〜氣體輸送系統 100〜MOS裝置 112〜基板 113〜摻雜區域 114〜摻雜區域 115〜通道區域 116〜介電層 117〜導電層 ^ 118〜矽化物層 119〜罩蓋層 120〜閘極堆疊 ” 121〜間隔件 122〜緻密SiONC:H膜 200〜處理 202〜步驟 204〜步驟 206〜步驟

Claims (2)

1326113 十、申請專利範圍： 1. 一種氮氧化矽膜之形成方法，包含以下步驟： 在基板上沉積一多孔SiNC:H膜；及 ^將ΐ多孔SlNC:H膜暴露於含氧氣體，以形成具有密度大於 S玄夕孔SiNO.H膜之緻密si〇NC:H膜。 專利範圍第1項之氣氧化石夕膜之形成方法，其中將該多孔 SiNC:H膜暴露於含氧氣體之步驟包含： ^生拉伸應力等於或大於約丨5GPa之緻密Si〇NC H膜。 3·如專利範圍第1項之氮氧化石夕膜之形成方法，其中該 沉積步驟包含： =忒基板暴露於包含有機矽烷氣體與含氮氣體之處 理氣體。 Hi i利範圍第1項之氣氧化石夕膜之形成方法，其中該沉積 梦驟包含： 露於包含職s雙（第三丁基胺基械)與 利範圍第4項之氮氧化销之形成方法，其中該暴露 步驟包含： 供應BTBAS:NH3比例大於〇.5:1之該處理氣體。 範圍第4項之氮氧化頻之形成方法，其中該暴露 步驟包含： 供應BTBAS:NH31；匕例介於約2:1與約8:1之間的該處理氣 體。 7.ii請專利範圍第4項之氮氧化賴之職方法，其中如冗積 步驟更包含： 將該基板維持在約50(TC與約8〇(rc之間的溫度。 8.如申μ專利關第4項之錄切膜之形成方法，其中 步驟更包含： 將戎基板維持在約525°C與約575。(：之間的溫度。 19 1326113 9.如申晴專概圍第丨項之氮氧化賴之形成方法，其中該沉積 步驟更包含： 將處理室壓力維持在約0.05 Ton*與約200 Torr之間。 1〇.如申請翻範圍第1項之H氧化频之形成方法 ，其中該沉積 步驟更包含： =處理室壓力維持在約0.3 Torr與約1〇 Torr之間。 U·^申請專利範圍第1項之氮氧化頻之形成方法，其中該沉積 步驟包含： a =戎Sl0NC:H膜沉積至介於約5nm與約50nm之間的厚度。 •如申凊專利範圍第1項之氮氧化賴之形成方法，其中將該多 孔SiNC:H膜暴露於含氧氣體之步驟包含： 將該多孔SiNC:H膜暴露於空氣。 13·，申μ專利範圍第1項之氮氧化⑪膜之形成方法’其中將該多 孑SiNC:H膜暴露於含氧氣體之步驟包含： 將該多孔SiNC:H膜暴露於〇2、h2〇、〇3或其組合其中至 少一者。 Η夕如申4專利翻第13項之氮氧化賴之形成方法，其中將該 夕孔SiNC:H膜暴露於含氧氣體之步驟包含： 將該處理室壓力維持在約1 Torr與約1〇〇〇 Torr之間。 睛專纖®第1項之錄化㈣之軸方法，更包含以下 含氧Ϊΐϊΐί孔伽⑶膜之該步驟及將該娜⑶膜暴露於 3氧^脰的该步驟，直到該Si〇NC:H膜具有規定厚度為止。 .申凊專利範圍帛15項之氮氧化石夕膜之形成方法 >儿積多^ SiNC:H膜的該步驟包含： T直複 繼續該重複步驟，直_ s趟C:H膜具有約⑴ lOOOnm之間的厚度為止。 一 17.如，請專纖圍第丨項之錄化賴之形成方法，其中在 上>儿積多孔SiNCiH膜之該步驟包含： 土 20 丄 疊之裝ΐ^。、有形成於°亥基板上的至少一掺雜區域及一閘極堆 18 土=以===，積 度、或高於該暴露步驟之溫度门下之進;度、低於該暴露步驟之溫 臟，其中瓣 產生拉伸應力等於或大於約1.5GPa彳 密SiONC:H膜。 ra仁小於約3.0GPa的緻 20. —種半導體裝置，包含： 一基板； 祕:f^C:H膜’沉積於該基板上，具有至少約1.5GPa之 膜且^ 膜係藉由在該基板上沉積一多孔SiNC:H sinc.hL二麟露於—含氧氣體而形成，以使該多孔 SiNC.H肤緻岔化而形成該Si〇NC:H膜。 21. 如申^專利範圍第2〇項之半導體裂置，其中該基板更包含： 堆聂、置，具有形成於該基板上的至少一摻雜區域與一閘極 22/f如痒申yT專利範圍第2〇項之半導體裝置，其中該Si0NC:H膜之 厚度；I於約l〇nm與約1〇〇〇nm之間。 23. —種氮氧化矽膜之形成系統，包含： 沉積裝置，用以在基板上沉積多孔SiNC:H膜；及 暴露裝置，用以將該SiNC:H膜暴露於含氧氣體而將氧植入 该SlNC:H膜，並形成密度大於該多孔SiNC:H膜之緻密 SiONC:H 膜。 、
24. Jtn申請專利範圍帛23項之氮氧化石夕膜之形成系統，其中該暴 路裝置產生拉伸應力等於或大於約1 5GPa之緻密Si〇NC:H膜。 25·如申請專利範圍第23項之氮氧化矽膜之形成系統，其中該沉 積裝置包含低壓化學氣相沉積系統(LPCVD)系統。 21 1326113 26. 如申請專利範圍第25項之氮氧化矽膜之形成系統，其中該 LPCVD系統係用以在介於約1 Torr與約1000 Torr之間的壓力 下操作。 27. 如申請專利範圍第23項之氮氧化矽膜之形成系統，其中該暴 露裝置包含一遠端電漿源。 ‘ 28. 如申請專利範圍第23項之氮氧化矽膜之形成系統，其中該暴 露裝置包含〇2、Η20、〇3或其組合其中至少一者之來源。 十一、圖式：
22
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Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8294224B2 (en) * 2006-04-06 2012-10-23 Micron Technology, Inc. Devices and methods to improve carrier mobility
US7825038B2 (en) * 2006-05-30 2010-11-02 Applied Materials, Inc. Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US7902080B2 (en) * 2006-05-30 2011-03-08 Applied Materials, Inc. Deposition-plasma cure cycle process to enhance film quality of silicon dioxide
US20070277734A1 (en) * 2006-05-30 2007-12-06 Applied Materials, Inc. Process chamber for dielectric gapfill
US7790634B2 (en) * 2006-05-30 2010-09-07 Applied Materials, Inc Method for depositing and curing low-k films for gapfill and conformal film applications
US8232176B2 (en) * 2006-06-22 2012-07-31 Applied Materials, Inc. Dielectric deposition and etch back processes for bottom up gapfill
US8168548B2 (en) * 2006-09-29 2012-05-01 Tokyo Electron Limited UV-assisted dielectric formation for devices with strained germanium-containing layers
US7491585B2 (en) 2006-10-19 2009-02-17 International Business Machines Corporation Electrical fuse and method of making
US20080116525A1 (en) * 2006-11-16 2008-05-22 United Microelectronics Corp. Complementary metal-oxide-semiconductor device
US20080153236A1 (en) * 2006-12-22 2008-06-26 Ning Cheng Flash memory devices and methods for fabricating the same
US7745352B2 (en) * 2007-08-27 2010-06-29 Applied Materials, Inc. Curing methods for silicon dioxide thin films deposited from alkoxysilane precursor with harp II process
US7867923B2 (en) * 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US7943531B2 (en) 2007-10-22 2011-05-17 Applied Materials, Inc. Methods for forming a silicon oxide layer over a substrate
US7803722B2 (en) * 2007-10-22 2010-09-28 Applied Materials, Inc Methods for forming a dielectric layer within trenches
JP4852016B2 (ja) * 2007-10-29 2012-01-11 株式会社東芝 半導体装置及びその製造方法
US8119540B2 (en) * 2008-03-28 2012-02-21 Tokyo Electron Limited Method of forming a stressed passivation film using a microwave-assisted oxidation process
US7807586B2 (en) * 2008-03-28 2010-10-05 Tokyo Electron Limited Method of forming a stressed passivation film using a non-ionizing electromagnetic radiation-assisted oxidation process
US8357435B2 (en) * 2008-05-09 2013-01-22 Applied Materials, Inc. Flowable dielectric equipment and processes
US20100081293A1 (en) * 2008-10-01 2010-04-01 Applied Materials, Inc. Methods for forming silicon nitride based film or silicon carbon based film
US8980382B2 (en) 2009-12-02 2015-03-17 Applied Materials, Inc. Oxygen-doping for non-carbon radical-component CVD films
US7935643B2 (en) * 2009-08-06 2011-05-03 Applied Materials, Inc. Stress management for tensile films
US8741788B2 (en) 2009-08-06 2014-06-03 Applied Materials, Inc. Formation of silicon oxide using non-carbon flowable CVD processes
US7989365B2 (en) * 2009-08-18 2011-08-02 Applied Materials, Inc. Remote plasma source seasoning
US20110136347A1 (en) * 2009-10-21 2011-06-09 Applied Materials, Inc. Point-of-use silylamine generation
US8449942B2 (en) 2009-11-12 2013-05-28 Applied Materials, Inc. Methods of curing non-carbon flowable CVD films
JP5421736B2 (ja) * 2009-11-13 2014-02-19 株式会社日立国際電気 半導体装置の製造方法、基板処理装置、及びプログラム
JP2013516763A (ja) 2009-12-30 2013-05-13 アプライド マテリアルズ インコーポレイテッド フレキシブルな窒素／水素比を使用して生成されるラジカルを用いる誘電体膜成長
US8329262B2 (en) * 2010-01-05 2012-12-11 Applied Materials, Inc. Dielectric film formation using inert gas excitation
KR101528832B1 (ko) 2010-01-06 2015-06-15 어플라이드 머티어리얼스, 인코포레이티드 유동성 유전체 층의 형성 방법
SG182333A1 (en) 2010-01-07 2012-08-30 Applied Materials Inc In-situ ozone cure for radical-component cvd
KR101853802B1 (ko) * 2010-03-05 2018-05-02 어플라이드 머티어리얼스, 인코포레이티드 라디칼­성분 ｃｖｄ에 의한 컨포멀 층들
US8236708B2 (en) 2010-03-09 2012-08-07 Applied Materials, Inc. Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor
US7994019B1 (en) 2010-04-01 2011-08-09 Applied Materials, Inc. Silicon-ozone CVD with reduced pattern loading using incubation period deposition
US8476142B2 (en) 2010-04-12 2013-07-02 Applied Materials, Inc. Preferential dielectric gapfill
US8524004B2 (en) 2010-06-16 2013-09-03 Applied Materials, Inc. Loadlock batch ozone cure
US8318584B2 (en) 2010-07-30 2012-11-27 Applied Materials, Inc. Oxide-rich liner layer for flowable CVD gapfill
US9285168B2 (en) 2010-10-05 2016-03-15 Applied Materials, Inc. Module for ozone cure and post-cure moisture treatment
US8664127B2 (en) 2010-10-15 2014-03-04 Applied Materials, Inc. Two silicon-containing precursors for gapfill enhancing dielectric liner
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8450191B2 (en) 2011-01-24 2013-05-28 Applied Materials, Inc. Polysilicon films by HDP-CVD
US8716154B2 (en) 2011-03-04 2014-05-06 Applied Materials, Inc. Reduced pattern loading using silicon oxide multi-layers
US8445078B2 (en) 2011-04-20 2013-05-21 Applied Materials, Inc. Low temperature silicon oxide conversion
US8466073B2 (en) 2011-06-03 2013-06-18 Applied Materials, Inc. Capping layer for reduced outgassing
US9404178B2 (en) 2011-07-15 2016-08-02 Applied Materials, Inc. Surface treatment and deposition for reduced outgassing
US8617989B2 (en) 2011-09-26 2013-12-31 Applied Materials, Inc. Liner property improvement
US8551891B2 (en) 2011-10-04 2013-10-08 Applied Materials, Inc. Remote plasma burn-in
US8889566B2 (en) 2012-09-11 2014-11-18 Applied Materials, Inc. Low cost flowable dielectric films
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films
US9412581B2 (en) 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US9711351B2 (en) * 2014-09-11 2017-07-18 Asm Ip Holding B.V. Process for densifying nitride film
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
JPWO2019087445A1 (ja) * 2017-10-31 2020-04-09 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置、およびプログラム
US10559470B2 (en) * 2018-01-22 2020-02-11 Globalfoundries Inc. Capping structure
US10950731B1 (en) * 2019-09-17 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Inner spacers for gate-all-around semiconductor devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232170A (ja) * 1993-01-29 1994-08-19 Mitsubishi Electric Corp 電界効果トランジスタ及びその製造方法
US5514908A (en) * 1994-04-29 1996-05-07 Sgs-Thomson Microelectronics, Inc. Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
JP4493779B2 (ja) * 2000-01-31 2010-06-30 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US6803289B1 (en) * 2002-06-28 2004-10-12 Cypress Semiconductor Corp. Bipolar transistor and method for making the same
JP2004153066A (ja) * 2002-10-31 2004-05-27 Fujitsu Ltd 半導体装置の製造方法
US7365029B2 (en) * 2002-12-20 2008-04-29 Applied Materials, Inc. Method for silicon nitride chemical vapor deposition
US7238604B2 (en) * 2003-04-24 2007-07-03 Intel Corporation Forming thin hard mask over air gap or porous dielectric
US6902440B2 (en) * 2003-10-21 2005-06-07 Freescale Semiconductor, Inc. Method of forming a low K dielectric in a semiconductor manufacturing process
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber

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