TWI324383B - Electrostatic discharge protection device and layout thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an electrostatic protection device and a layout thereof, and more particularly to an equal-substrate-potential technique. Electrostatic protection device and its layout. [Prior Art] Electricity is produced in a continuous manner.

^You ^ cell 霄 suffers from electrostatic discharge...~ Generally speaking, the electrostatic discharge (ESD) impact,,, The degree of voltage generated by the discharge can be divided into Human-Body Modd (HBM), Mechanical Model 'MM (Machine Model ' MM), and Charge-Device Model (CDM). When an electrostatic discharge occurs, this electrostatic discharge current is likely to burn the component. Therefore, some electrostatic discharge protection measures must be taken in the circuit to effectively isolate the electrostatic discharge current and prevent component damage.

The most common practice is to design an ESD protection device between the core circuit and the pad (PAD) to protect its internal circuitry. The ESD protection device has several modes, namely PD, PS, =, NS mode, wherein the PD/ND mode is to input positive pulse, & rush, and direct the electrostatic discharge current to the system voltage VDD. Wire; nuclear type is the conductor of the positive pulse 7 negative pulse, the static electricity discharge electric discharge & to the ground voltage VSS. Block diagram of non-electrostatic discharge protection circuit. Referring to FIG. 1, when the mode is to input a positive pulse 1〇5 from the pad 101, the electrostatic protection device 5 22247twf.doc/n 102 is used. Called ^ 电压 system voltage line VDD to protect the core power protection county set m 1G1 input 贞 pulse 1%, use static to protect the core power slightly = current guide to the ground voltage trajectory vss for n & and so on The ps, ND mode operation circuit 104 may also accumulate static charge when operating, so the core circuit 104 a - y J u move, H) 3 lead discharge discharge static charge can also be electrostatic discharge through the electrostatic discharge device ^ * The protection circuit is implemented by a transistor that is grounded by N-type gold oxides. nηίΐ€<1 n"Channel metal-〇xide-semic〇nductor, ^N^S). Figure 2 shows that the solid-state electrostatic discharge of the n-type "oxygen semi-transistor with a gate is grounded normally. When r4 is operating normally, the N-type MOS transistor is grounded. The cut-off state will not occur when static electricity occurs, the high voltage 2〇5 enters from the 烊 pad 2〇1. When this = voltage 2〇5 exceeds the N-type MOS semi-transistor's immersion and body collapse voltage ¥ causes N-type money and a half The electric (4) secret and the body collapse generate the base _ current 'trigger the parasitic transistor in the N-type MOS transistor to guide the electrostatic discharge current. Since the ESD protection circuit is subject to high voltage electrostatic discharge, it takes several hundred micrometers in layout. The width of the channel is therefore multi-fmger type layout, so as to reduce the area occupied by the 矽. However, this layout will cause internal lateral parasitic N-type MOS transistors. (parasitic) The base resistance of the junction transistor (BJT) is different, that is, the closer to the center 22247twf.doc/n 22247twf.doc/n, the larger the base resistance of the parasitic transistor When the middle of the ΐΐΠ body occurs suddenly (Snapbac k) In the crash state, the ESD electrical interface transistor is guided to the η 曰 曰 向 向 向 寄生 寄生 寄生 寄生 寄生 至 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 So that this electrostatic discharge pulse may be electrically ===he_gold oxide semi-transistor, causing the lead electrostatic discharge::彡=生==protection ability attenuation, the above question (1)乂7 Beiqi Qiqi electricity day and body base The pole resistance is approximately the same. Figure 3A shows a top view of the layout of the ESD protection circuit of US Pat. No. 5,811,856. Figure 3B shows the layout of the ESD protection circuit of the patent No. 5811856. Referring to FIG. 3A and FIG. 3B, the ESD protection circuit of the ESD protection device 103 of FIG. 1 has a guard-ring formed by the p+ doping region 3〇1 to avoid electrostatic discharge current leakage/3〇2 The N+ doped regions 303, 304 form a gate grounded N-type gold oxide (GGNMOS) transistor, and the N+ doped regions 303, 3〇4 and the substrate 3〇8 form a parasitic transistor 309 'doped positive 307, 311 And the substrate 3〇8-shaped mistletoe transistor 312. Further, the N+ doping regions 305, 307 and the substrate 3〇8 form parasitic electricity The crystal 310. The method for solving the problem of guiding the electrostatic discharge current non-uniformity is to embed the grounded p+ diffusion region 306 ' in the source 304 adjacent to the N-type MOS transistor to make the parasitic transistor 3〇9, The base resistances of 31〇 and 312 are approximately the same, whereby the parasitic transistor can be triggered simultaneously to guide the electrostatic discharge current. However, the layout of the embedded P+ diffusion region 306 not only increases the area of the 1324383 22247twf.doc/n area but also In the deep-submicron complementary metal-oxide-semiconductor (CMOS) process, the substrate resistance of the N-type MOS transistor is too small, which makes the internal parasitic transistor difficult. Triggered, unable to guide the ESD current in time to protect the core circuit. Figure 4 shows M, D. Ker, C.-H. Chuang and W.-Y. Lo in "Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-um Salicided CMOS Process (Proc. IEEE Int. Symp. Electronics, Circuits and Systems, 2001, pp. 361-364). Referring to FIG. 4, another method for solving the problem of non-uniformity of the ESD current is to connect the sensing circuit to the gate of the MOS transistor. This sensing circuit is typically composed of a resistor RP1 (or RN1) and a capacitor 〇>1 (or CN1). When the sensing circuit senses that an electrostatic discharge event occurs, the sensing circuit provides a bias voltage to the gates of the MOS transistors 1 and ΜΡ2 (or MNi and) to simultaneously turn on the transistors Μρι and MP2 ( Or MNi and _2) to derive the electrostatic discharge current. The p-type MOS transistor MP2, the capacitor CP1 and the resistor RP1 can be regarded as the internal components of the electrostatic protection device 102 of the above FIG. 1; the N-type MOS semi-transistor MN1, MN2, the capacitor CN1 and the resistor RN1 can be regarded as the above-mentioned static electricity of FIG. The internal components of the guard 103. The adjustment resistor (10), Rpi, and the capacitors CN1, CP1' are used to provide a bias voltage to the gate of the metal oxide semi-electrode _b and the P-type MOS transistor MP1, MP2, thereby reducing the N-type gold oxide. The trigger voltage of the semi-transistor stomach and the bismuth-type gold-oxygen semi-transistor "卩 8 8 1324383 22247twf.doc/i MP2. When the electrostatic discharge occurs, the N-type oxy-half can be triggered in time with a small trigger voltage. The transistor MN1, _2 or the p-type MOS transistor MPb is used to guide the electrostatic discharge current. However, the gate of the N-metal oxide semi-transistor MN1/P-type MOS transistor is added. The bias voltage will generate more channel current, and the higher electric field may break through the gate-oxic layer to reduce the electrostatic protection capability. In addition, the resistance of the general sensing circuit, RP1, is extremely high. It is also an increase in the layout area. Figure 5 shows the electrostatic anti-smash circuit of U.S. Patent No. 5,631,793. Please refer to Figure 5, N-type gold oxide semi-transistor_丨The resistor RN1 and the capacitor CN1 are the internal components of the electrostatic discharge protection device 1〇3 of FIG. 1 described above. The method for solving the problem of guiding the electrostatic discharge current non-uniformity is to electrically connect the sensing circuit to the base of the gate grounded N-type gold-oxygen semi-transistor (GGNm〇s) and _2. The sensing circuit is composed of the resistor RN1 and Capacitor CN1 is composed of electric resistance t' by adjusting resistor RN1 and capacitor cni to make internal parasitic Raydan County hot-printed to earth_

The bungee's extra channel current causes the electrostatic protection to be additionally added to the resistor RN1 and the capacitor CN1 to still voltage, parasitic BB body (ie, the gate is grounded to the N-type MOS MN1 and MN2 # base), thereby increasing parasitic The base voltage of the transistor, 2 reduces the problem of non-uniformity of the trigger flow of the gate-grounded N-type MOS transistor. The gates of the bodies MN1 and MN2 have a reduced monthly force. However, the extra area is increased. 22247 twf.doc/n Figure 6 shows the static anti-5 蒦 circuit of U.S. Patent No. 5,568,751. Referring to Figure 6, the technique for guiding the ESD current non-uniformity is to use a domino to trigger the N-type MOS transistor of each finger. In Figure 6, Rdl~Rdi are N-type MOS transistors, and the ballasting resistors of the poles, Rsl~Rsi, and MOS-type semi-electrode _丨~_丨 source. The n-type gold oxide half crystals 1 to tear and the resistors Rd1 to Rdi, Rs1 to Rsi are the internal components of the electrostatic protection device 103 described above. When an electrostatic discharge occurs, as long as the N-type MOS transistor (for example, N-type MOS transistor 1) is triggered, the ESD current will supply a voltage to the N-type gold through the stabilization resistor Rsl. The gate of the oxygen semiconductor MN2. The triggered ^^ type gold^semiconductor MN2 will cause the electrostatic discharge current to pass through the stabilization resistor Rs2 to supply a voltage to the gate of the (4) MOS transistor MN3. With such a kind of touch, the type of gold oxide semi-transistor is 3...MNi. However, although this prior art can solve the problem of guiding the non-uniformity of the electrostatic discharge current, it adds complexity. SUMMARY OF THE INVENTION The present invention provides an electrostatic discharge protection device that enables multiple electrostatic discharge protection units to be simultaneously triggered, that is, directs an electrostatic discharge current to avoid conduction 5|electrostatic discharge current in the case of high voltage electrostatic discharge. Uneven sentence problem. 3 In addition, 'When the smaller supply is used, the T-test circuit is input and the input pad', and the input interface of the 1% voltage operation (I/O丨攸 two (5) simultaneously cooperates with the operation of the electrostatic discharge protection device. The mixed voltage-mixed operation can also operate normally. 22247twf.d〇c/n The present invention provides an output buffer for electrostatic discharge discharge protection capability, ', and two applications for electrostatically controlled electrostatic discharge The guard device rotates a "round-out drive capability of the circuit's turn-out signal path. σ &, wrong to increase the core power provided by the invention - an electrostatic discharge control implementation. In a limited layout area == placement doping The zone 'is based on the bias line current, the base of the parasitic transistor of the distribution discharge protection device in the matrix is the secret mode of the above static static discharge. The electrostatic discharge of the high electric ° can be triggered simultaneously and the time guide y SC: ?Electrical discharge current non-uniformity: Set, including a plurality of electrostatic discharge prevention - an electrostatic discharge protection crack discharge protection unit is used to 僖 Mo Yi a bias wire. A plurality of static circuits pass between the first conductive path and Second conductive crystal The body and the Sr electric protection unit comprise a parasitic electric energy, and the parasitic electric crystal 'and the == are connected to the base of each of the parasitic transistors. The driving electrostatic discharge protection device comprises a plurality of output two: ίCurve wire. Multiple output drive units are used to rotate to the first conductive path according to the core per-output drive = signal, which is included in the first parasitic transistor and parasitic resistance. The collector and the emitter of the crystal are respectively connected to the first conductive path and the 蛉'' path, and each of the parasitic resistors is coupled to the corresponding parasitic 11 丄J厶22247twf.doc/n base and the second conductive path The biasing wire is coupled to each of the bases of the parasitic transistor. The electrostatic discharge protection device includes a plurality of electro-crystals from the == electric current; the collector of the body, each conducting, The two-conductor circuit is more than two === connected to: ± between the two poles and the second conductive path. The biasing wire is coupled to the base of the return-up crystal of the mother. The handle "the first kind of static conduction, protective layout, Including the substrate electrostatic discharge prevention multiple bodies have - parasitic resistance. The first doping area = The first conductive path is disposed on the soil, and the ruthenium is placed as a substrate above the substrate. Each of the above electrostatic charges is j. The second conductive path is not in contact with the first doped region. Between the body and the second conductive path...c-the conductive path has a parasitic transistor structure. The plurality of second doping units are provided in each of the above-mentioned electrostatic discharge protection units: the impurity 3 is placed on the substrate and configured Not connected to each of the above-mentioned electrostatic discharge protection units ς = above the second doped region substrate 'the wire is connected to the wire. The wire arrangement is further proposed in the present invention - a kind of two-doped region. Body, first-doped region, first-guided protective layout, including base electric discharge protection unit, multiple ^ conductive paths, multiple static_distributed to the base body: 3⁄4 to electricity 12

U24363 22247twf.doc/n The light path is respectively arranged on the base above the base body and is not connected to the first doped area=electricity, and the protection unit is arranged in the electrical path and the second conductive circuit furnace to conduct static electricity to the first guide. Including the first-to-first phase of the first-and-first phase of the volta-oxygen semi-electric J-electrostatic discharge protection unit. The plurality of third doping regions are provided with a subtractive conductive path and a second MOSFET of the second conductive path and are placed in contact with the first and second MOS transistors. Said - in which the electrical connection to each of the upper poles engages each other = the electrostatic discharge protection of the internal parasitic transistor of each of the electrostatic discharge protection units can be triggered simultaneously to guide the electrostatic discharge electricity, additionally, under different voltage operations When the device is operated in conjunction, the electrostatic discharge device can operate the mixed voltage normally. Further step-by-step, this electrostatic discharge protects the _ front-stage drive unit, causing the charge generated by the front-stage drive unit to discharge. The above described features and advantages of the present invention will become more apparent from the following description. Embodiment 7 FIG. 7 illustrates an electrostatic discharge protection device according to a preferred embodiment of the present invention. Referring to FIG. 7, the ESD protection device 703 is coupled between the soldering pad 7 (^ and the second conductive path (such as the ground voltage rail) 702. The soldering wire 701 is lightly connected to the core circuit via the first conductive path. 7〇6. Solder pin 7〇1 can be an input pad or an output pad. Electrostatic discharge protection device 7〇3 main 13 1324383 22247twf.doc/n contains electrostatic discharge protection units 707~71〇 and bias wires 7〇5 In this embodiment, for example, the electrostatic discharge protection device 703 is implemented by a multi-fnger type layout method, thereby reducing the occupied area of the crucible. Here, only four electrostatic discharge prevention and protection units 707 to 710 are taken as an example. Those with ordinary knowledge can determine the number of ESD protection units depending on their needs.

Each of the electrostatic discharge protection units 707 to 710 in this embodiment has an N-type MOS transistor (ie, FIG. 7*M1 to M4). ^ Since the n-type MOS transistors M1 to M4 are disposed in the substrate _ illusion Each of the electrostatic discharge protection units 707 to 710 has a parasitic transistor A1 to M and each has a parasitic resistance (base resistance) Ral to Ra4. The resistors Rml to Rm4 are respectively connected between the idle voltages of the N-type metal oxide semiconductors m to M4 and the voltage rails 7〇2. Those with ordinary knowledge in this field can adjust the gate of the N-type MOS semi-transistor milk directly to the voltage trajectory according to their needs. Alternatively, the gates of the MOS-type MOS transistors M1 to M4 may be floated.

When static electricity occurs, the high voltage chest enters from the soldering iron. If the high voltage 704 exceeds the breakdown voltage between the secret and the body of one of the N-type MOS transistors, such as the transistor M2, The type ί oxygen pole and the body interface collapse and the base is electrically caught. In this case, the parasitic resistance may be generated by using a biased wire to connect the parasitic transistor αι~α4. This bias voltage is in addition to triggering the parasitic electric η, and other parasitic transistor cores and eight; body two: 'also f At the same time, it is triggered from the first-conducting path to guide the electrostatic discharge to generate electricity _A1~A4, and the electric current flows to the second conductive path (here, 1324383 22247twf.doc/n is the grounded electric house rail) 702 to avoid electrostatic discharge. The component, that is, the solution of the electrostatic discharge current is not the second sentence. In the other embodiment of the invention, the second conductor is the remaining power line. If the second conductive path 7 J is the same, the P-type MOS transistor can be used in Figure 7 to take N = 703 N-type oxy-oxygen semi-transistor milk. Electrical Discharge Tamping Device Figure 8 depicts an electrostatic discharge not preferred embodiment of the present invention. Referring to Figure 8, there is an electrostatic discharge protection. Device. Buffer system. The electrostatic discharge is between (for example, the outline trajectory 801) and the second conductive circuit = the damper line 802). Electrostatic discharge protection device main" ^ electric drive unit (or electrostatic discharge protection unit (4) 7 ~ 8l () m out = wire 813. This embodiment, for example, using a multi-finger layout side two: electrostatic discharge protection device 803. For example, 807~810 is used as an example. The number of output drive units in this field is 〜~w. The number of output drive units is the same. The number of drive units can be determined according to their needs. Each drive unit 8〇7~81 in this embodiment is determined.

Type MOS semi-transistors m~N4 and each have p-work; there are N P1~P4. Straight, Lei B Xu ΧΓ 1 Ή, 'gas semi-transistor between its t electric body Ν 1 ~ Ν 4 and Ρ 1 ~ Ρ 4 series path (such as ground voltage line 802) and ~ 绔 electric system voltage line 801) ( As shown in Fig. 8, the diameter (for example, the transistors Ν1~Ν4 are arranged in the base type 金-type gold-oxygen half and a 丞 basket, so each wheel has a parasitic transistor C1~C4 and a resistance Rci ~Re4. Since the p-type MOS transistor 4 configuration tli 1324383 22247twf.doc / n therefore each of the output drive units 807 ~ B1 ~ B4 and each has a parasitic resistance Rbl

Each of them also has a parasitic transistor 〜Rb4 〇 This embodiment outputs an output buffer of the electrostatic discharge protection device 8G3 805. Each of the wheel drive units ^~_ generates a signal according to the core and output signal (10) that is rotated by the core circuit 8G5. The external output signal is soldered via the first conductive path 81. Since the bias wires 813 shout the parasitic transistors C1 to C4 and the parasitic transistors m to B ^ by the bias wires 812, when the static electricity occurs, if the output cells are: A breakdown due to electrostatic discharge, the bias voltage generated by the electrostatic discharge current through the parasitic resistance will turn on the parasitic transistors B1 to B4 and the parasitic transistor via the bias wire 812. For example, when static electricity is generated such that the junction between the electrode of the transistor N2 (or the tap) and the body collapses, the electrostatic current generates a bias voltage by 2 (or Rb2) through the parasitic resistance. Since the biased wire is used to make (or commit) the base of the parasitic transistor C1~(or B1~B4), the bias voltage simultaneously triggers other parasitic transistors Cl, C3 and C4 (or B1, B3 and B4). Therefore, when the static electricity occurs, the wheel drive unit 8〇7~8ι〇4 will be triggered. The electrostatic discharge current is guided to the third conductive path (for example, the system voltage rail 8〇1) via the respective output driving units 807 to 810. The conductive circuit (for example, the ground voltage rail 8〇2) prevents the electrostatic current from damaging the core. The components inside the circuit 8G5 also solve the problem of guiding the non-uniformity of the electrostatic discharge current. 16 1324383 22247twf.doc/n

Figure 9 is a diagram showing an electrostatic discharge protection device in accordance with a preferred embodiment of the present invention. The ESD protection device 903 is coupled between a third conductive path (e.g., voltage rail 901) and a second conductive path (e.g., ground voltage rail 9〇2). The electrostatic discharge protection device 903 mainly includes output drive units 9A and 908, electrostatic discharge protection units 909 and 910, bias wires 912, and bias wires 913. In the present embodiment, the electrostatic discharge protection device 903 is implemented by, for example, a multi-finger layout. Here, only two wheel drive units 9〇7, 9〇8 and two ESD protection units 909 and 910 are taken as an example, and those skilled in the art can determine the output drive unit and the ESD protection unit according to their needs. Quantity. Each of the output driving units 9A and 908 in this embodiment has a P-type MOS transistor P5, P6 and an N-type MOS half-electrode N5, N6, respectively. Each of the ESD protection units 9〇9, 91〇 has a J N-type gold oxide semi-electrode and a P-type MOS semi-transistor, / /, the transistors N5 N N8 and P5 P P8 are connected in series to the second conductive road name

Between the second conductive path and the second conductive path (as shown in FIG. 9). Each of the transistors N5 to N8 has a parasitic electric crystals it CS to c8 and each has a parasitic resistance Rc5 to Rc8. Each of the transistors P7 and P8 has a parasitic transistor milk, and has a parasitic resistance Rb5 to Rb8. The biasing wire 913 couples the bases of the parasitic electric (5) to C8 together and the biasing wire 912 couples the parasitic electric crystals, and the bases of B5 to B8 are coupled together. For example, this electrostatic discharge protection device 9〇3 can be used as a core 1 buffer. The output driving unit 907 generates an external output signal according to the core output signal outputted by the circuit 905, and the external output signal is output to the bonding pad 9〇4 via the first conductive path 911. . Referring to FIG. 9, since the bias wires 912 lightly connect the bases of the parasitic transistors b5 to B8 together, and the bases of the parasitic transistors eg to eg are lightly connected by the partial ink wires 913, when static electricity occurs, If the output drive unit ', or one of the ESD protection units 909, 910 collapses due to electrostatic discharge', the bias voltage generated by the electrostatic discharge current through the parasitic resistance will open other parasitic via the bias wires 912 and 913. Transistor. For example, when static electricity is generated such that the junction between the drain of the transistor N7 (or P7) and the body collapses, the electrostatic current generates a bias voltage through the parasitic resistance Rc7 (or Rb7). Since the base of the parasitic transistors C5 to C8 (or B5 to B8) is connected by the bias wire 913 (or 912), the bias voltage simultaneously triggers other parasitic transistors C5, C6 and C8 (or B5, B6 and B8). Therefore, when the static electricity occurs, the output driving unit, 908 and the electrostatic discharge protection unit 9〇9, 91〇 are all triggered. The electrostatic discharge current is directed to the third conductive path (eg, system voltage rail 90 and/or second conductive path (eg, ground voltage rail 902) via the ESD protection units 907, 908 and the ESD protection units 909, 910, Avoiding electrostatic currents destroying components inside the core circuit 905' also solves the problem of guiding the non-uniformity of the electrostatic discharge current. In addition, as the process of the semi-transistor progresses, the supply voltage required for the core circuit becomes smaller, thereby reducing power consumption and heat dissipation. However, the core circuit of the low voltage operation may still operate simultaneously with the input and output interfaces of other higher supply voltages. In the operation of the above mixed voltage, the electrostatic discharge protection device 18 22247twf.doc/n is required to ensure the core circuit. The operation can also maintain the electrostatic discharge protection capability at high voltages. Therefore, it is necessary to increase the voltage tolerance of the electrostatic discharge protection device. Fig. 10 is a view showing an electrostatic discharge protection device according to a preferred embodiment of the present invention. 'The solder fillet is drained to the core circuit 1006 via the first conductive path. The ESD protection device 1〇〇3 _ is connected to the road light The second conductive path (such as the grounding electric grinder line) 2 'pad 1001 can be the input pad or the output pad. The electrostatic discharge protection device 1〇〇3 mainly includes the electrostatic discharge protection unit 1〇〇7 ~] _ to f bias wire 10 〇 5. This implementation (four) such as the full reference to the way to implement t electrostatic discharge protection unit 'to reduce the number of only one electrostatic discharge protection unit brain 7 ~ _, this field h The number of electrostatic discharge cells can be determined according to their needs. ^Solan unit Cong ~ face = winter oxygen ^ 曰曰 body (such as Ν type MOS semi-transistor (4)" 乂 and the first MOS semi-transistor (for example Ν D1~D4). 苴中, 笼—also 一一八主兔牛牛电阳阳路路和盥笛1', the first middle 〃, the first - gold oxide semi-transistor connected in series with the first guide ί as V (譬如是Between the grounding and the viscous): 曰2). The gates of the transistors Q1 to Q4 are coupled to the second conductive “electric gate _ to the third conductive path (for example, ===. _ type gold oxide) Semi-transistor" Valley has parasitic transistor Ε1~Ε4 to Rel~Re4. Resistor Rql~R parasitic resistance Q1~Q4; ts life &aq is not coupled to N type Between the gold-oxide semi-transistor pole and the grounded electric ink rail line, this field has a pass 19 22247twf.doc/n I ί See: and the omitted resistor is called 1~Rq4 'Also the N-type _ Q~Q4 gate Extremely lightly connected to the grounded electric calendar 2 ' can make the idle poles of the N-type gold-oxide semi-transistors Q1~Q4 float. The difference between the oxygen half-pattern 1〇 and the Figure 7 is the N-type gold electric body φ~ Q4 is connected in series with N-type gold-oxygen semi-transistor 〇ι~〇4, =Do not mention the trigger voltage of the electrostatic discharge protection unit bribe~_, = the discharge protection device circle has a higher voltage tolerance. Since the bias 005 will parasitic transistor The base of E1~E4 is connected, so the field ~/electricity occurs, if the electrostatic discharge protection unit ι〇〇7~ι〇ι〇, it collapses due to electrostatic discharge, the bias voltage generated by the electrostatic discharge current The parasitic transistors E1 to E4 are turned on by dividing f from the bias wires. The above-mentioned gold oxide half lUD1~D4 is tilted & connected to the green VDD so that the general knowledge of the 7 贞 domain should be known to still be replaced by the p-type MOS transistor (4) _ grounding money (four) • This embodiment is not limited to this range. Fig. i is an electrostatic discharge protection of the preferred embodiment of the present invention. Fig. U' Here, the electrostatic discharge protection device 1103 can be used as a buffer. The ESD protection device should be connected to the third 2 = upper, for example, between the system voltage line and the second conductive path (eg, the spoon). The ESD protection device 1103 mainly includes a wheel drive unit (herein described in the gamma drive unit 1107 to 1110) and a bias wire 1113. 20 22247twf.doc/n In this embodiment, each of the output driving units 1107 to 1110 and the right ί ^ oxygen semiconductors W1 〜 W4, each having an N-type MOS transistor, and each having a P-type MOS Crystals Y1 to Y4. Each of the output drive units has a parasitic transistor called 4 and each has a parasitic resistance Rfl to Rf4. The bases of the partial (1) bodies F1 to F4 are coupled together. Qian Yusheng Baoyang This embodiment can use this ESD protection device 11() 3 as an output buffer of the core circuit 1105. The output driving unit 11〇7~111〇 generates an external wheel according to the core output signal outputted by the path 11G5. The external output signal is output to the pad U04 via the first conductive path 11u. Referring to FIG. 8 and FIG. The example operates similarly to the circuit of the embodiment of Fig. 8 and will not be described again. Figure U differs from Figure 8 in that N-type MOS transistors W1 to W4 and P-type MOS transistors γι2 are connected in series with N-type MOS transistors χι~χ4, respectively, so that k The trigger voltage of the electrostatic discharge prevention unit 11〇7~丨11〇 makes the electrostatic discharge protection device 1103 have a high voltage tolerance. Figure 12 is a diagram showing an electrostatic discharge protection according to a preferred embodiment of the present invention. The ESD protection device 12〇3 is coupled between the third conductive path (eg, the first voltage rail 1201) and the second conductive path (eg, the ground voltage rail 1202). The ESD protection device 12〇3 mainly includes an output drive unit=1207 and 1208, an ESD protection unit 12〇9 and 121〇, and a biasing wire 1213. Here, only two output drive units 12〇7, 12〇8 and two ESD protection units 12〇9 and 丨21〇 are taken as an example. This field has 1324383 22247twf.doc/n. Output the number of county units and electrostatic discharge units. The output driving units 12A7 each have parasitic transistors F5 and F6 and parasitic resistances Rf5 and Rf6. The turns of the ESD protection unit i2 each have parasitic transistors F7, F8 and parasitic resistances Rf7, RfB. The voltage wires 1213 couple the bases of the parasitic transistors F5 to F8 together. Please refer to Figure 9 and Figure! 2. This embodiment is similar to the circuit operation of the embodiment of FIG. 9 and will not be described again. Figure 12 differs from Figure 9 in that Figure Y5 J Oxygen Half-Crystal Boundary 5~ and P-type Gold Oxygen Semiconductors are connected in series (4) Gold Oxygen Semiconductors 5~χ^ρ Oxygen Semiconductors 5~Ζ8 'By increasing the trigger voltages of the output drive units 12〇7 and 1208, the ESD protection unit and 121〇, respectively, the discharge protection device 12〇3 has a higher voltage tolerance. It is worth mentioning that the electrostatic discharge of the present invention has been drawn to a possible type, but it is known in the art that the electrostatic discharge protection components used are different. 2 implementation __ gold oxygen semi-electric (10) for the electrostatic discharge protection device as an example 'but can still use P-type gold oxide semi-transistor for the electrostatic discharge protection element _ _ _ _ _ _ _ _ _ _ _ _ _ _ A possible type. Lu Zhi, as long as the base of some or all of the parasitic transistors in the ESD protection device is coupled together, so that the parasitic body in the ESD protection device has a base potential, thereby simultaneously triggering the parasitic transistor to guide Quiet. 'Discharge current is already in line with the spirit of the present invention. 22 247 22247 twf.doc/n Other embodiments will be presented to provide a general knowledge of the above embodiments. The ® 13 field is shown as a top view of the static/discharge protection layout of the above-described embodiment of Fig. 7, and Fig. 13B is a cross-sectional view of the layout of the bribe secret protection shown in Fig. 7 above. Please refer to (4)m and Figure 3Β. The electrostatic discharge protection layout of this embodiment includes a Ρ-type base measurement, a first-stage hybridization area, an electrostatic discharge protection unit 13G7-131G, and a second doped area.

The mCM 321, the first conductive circuit passes through the 13G1, the second conductive path 1302, and the bias wire 1305. The electrostatic discharge protection sheets s n〇7~mo each have an N-type gold-oxygen semi-electrode, wherein the electrostatic discharge protection sheet has a parasitic transistor structure. The substrate 13〇3 has a parasitic resistance. The first doped region 1304 is a P+ doped region which is disposed on the substrate 13() 3 and is coupled to the ground voltage ' to serve as an electrode of the P-type substrate 1303.

The ESD protection unit 1307 has an N-type MOS transistor formed by the N+ doping regions 1311, 1312 and the gate 1316, and a parasitic transistor formed by the N+ doping regions 1311, 1312 and the P-type substrate 1303. . The ESD protection unit 1308 has an N-type MOS transistor formed by the N+ doping regions 1312, 1313 and the gate 1317, and a parasitic transistor formed by the N+ doping regions 1312, 1313 and the P-type substrate 1303. . The electrostatic discharge protection unit 1309 has an N-type MOS transistor formed by doped regions 1313, 1314 and a gate 1318, and has a parasitic transistor formed of N+ doped regions 1313, 1314 and a P-type substrate Π03. The electrostatic discharge protection unit 1310 has an N-type MOS transistor formed by the N+ doping regions 1314, 1315 and the gate 1319, and a parasitic transistor formed of the N+. impurity regions 1314, 1315 and the P-type substrate 1303. . 23 1324383 22247twf.doc/n Electrical anti-smashing 13G7~131G is used to conduct the electrostatic discharge current; between the conductive path 13G1 and the second conductive path 13()2. Therefore, the n+ doped region 1312, 1314 (the N-type MOS transistor) has an electrical path in which the first conductive path is electrically connected to the solder bump i (here, the output pad or the input pad field region) Ϊ́3ΐι, 1313, 1315 (the source of the 金-type MOS transistor) and the open electrodes 1316 〜 1319 are coupled to the second conductive path (4) (here may be the ground voltage rail embodiment of the base of the internal parasitic transistor) The bias wires are coupled together to simultaneously trigger the parasitic transistor to conduct the electrostatic discharge. In order to electrically connect the bias wires 13〇5 and the base of the parasitic transistor, the germanium + doping region 1312 The second doped regions 1320 and 132 are respectively disposed in the range of 1314, and the second doped regions are measured and the field oxide layer (or other isolation technology) is respectively separated from the doped regions 1312 and (3) 4, wherein the second is separated. The doped region is electrically connected to the second doped regions 132〇 and 1321. In another embodiment of the present invention, the electrostatic discharge protection units 1307~1310 may each be The _ _ type MOS MOS transistor is implemented so that the substrate 1303 is a Ν type substrate (or The 井-type well placed in the Ρ-type substrate) 'the first-doped region is the Ν+ impurity-changing region and is connected to the system voltage'. The second impurity-changing region 1311~1312 is the Ν+doped region'the second conductive path 13〇 Voltage trajectory. Figure 14 shows a schematic diagram of an electrostatic discharge protection layout according to a preferred embodiment of the present invention. Please refer to Figure 14 for the difference between the actual and the map. In the range of Ν+ doped regions 13U, (3)3, and m5, 24 1324383 22247 twf.doc/n do not configure ^ doped regions 1322~1324. 帛: 1322~1324 > Do not use field oxide layer (or other isolation technology)# The N+ doping regions 1311313 and 1315 are isolated from each other, wherein the second doping regions 1322~1324 are doped regions, and the bias wires 13〇5 are electrically connected to the second doping regions 1322~1324 to make internal parasitic transistors The base is coupled together. Figure 15 is a top view of the ESD protection layout according to a preferred embodiment of the present invention. The reference is shown in the range of the N+ doped regions 13γ~1315. The second doping regions 1320 to 1324 are disposed. The second doping regions 132〇 to 1324 respectively utilize field oxide layer (or other isolation technology) and germanium + doping The doped regions 1311~1315 are isolated. The second doped regions 1320~1324 are Ρ+ doped regions, and the bias wires 13〇5 are electrically connected to the second doped regions 132〇~1324 to make internal parasitic transistors Figure 16A is a top view of the electrostatic discharge protection layout of the embodiment of Figure 1 above, and Figure 16A is a cross-sectional view of the electrostatic discharge protection layout of the embodiment of Figure 10 above. Please refer to Figures 16 and 16 simultaneously. The electrostatic discharge protection layout of the present embodiment includes a Ρ-type substrate 1603, a first doped region 1604, electrostatic discharge protection units 1607~1610, a second doped region 1630~1631, a Ν+ doped region 1611~1619, a first conductive The path 1601, the second conductive path 1602, and the biasing wire 16〇5. Among them, the p-type substrate 16〇3 has a parasitic resistance. The electrostatic discharge protection units 16A7 to 161 are implemented by using a ruthenium-type oxynitride. The first doped region 16A4 is a p+ doped region disposed in the germanium-type substrate 1603 and coupled to the ground voltage rail to serve as an electrode of the substrate 1603. 25 1324383 22247twf.doc/n Electrostatic discharge protection unit 1607 has two n-type MOS transistors formed in series with N+ doped regions i6u~1613 and gates 1620~1621, and has N+ doped regions 1611 A parasitic transistor formed by the 1613 and the substrate 1603. The ESD protection unit 1608 has two N-type gold oxide semi-transistors formed in series with the gates 1622 1626 by the doped regions 1613 16 1615 and has a N+ doped region 1613, 1615 and a substrate 1603. Parasitic transistor. The ESD protection unit 1609 has two N-type MOS transistors formed in series with the *N+ doped regions 1615 1617 and the gates 1624 〜 1625, and has a disk substrate 1603 formed by the N+ erring regions 1615 and 1617. Parasitic transistor. The ESD protection unit 161 has two N-type MOS transistors formed in series with the gates 1626 〜 1627 by the N+ doping regions 1617 〜 1619 and has parasitic formations from the doped regions 1617, 1619 and the substrate 1603 Transistor. ', the ESD protection units 1607~1610 are for conducting an electrostatic discharge current between the first conductive path 1601 and the second conductive path 丨6〇2. Therefore, the 1^+ _ doped regions 1613 and 1617 are coupled to the first conductive path 16〇1, wherein the first conductive path 1601 is electrically connected to the pad 1606 (here, an output pad or an input pad). The regions 161, 1615, 1619 and the gates 1620, 1623, 1624, 1627 are connected to the second conductive circuit control 1602 (which may be the ground voltage rail). In addition, the gates 1621, 1622, 1625, 1626 are connected to the system voltage VDD. In this embodiment, the base of the internal parasitic transistor is coupled together with the biasing wires 16〇5, thereby simultaneously triggering the parasitic transistor to direct the electrostatic current. In order to electrically connect the bias wire 1605 to the base of the parasitic transistor 26

丄JZr leaf JOJ 22247twf.doc/n 1613, 1617 are respectively configured with the second = ΓΓ~1631 H pure 163G~1631 fractional field oxide layer (or other isolation technology) and N+ doped regions 16l3, i6i7 isolated. ^The second doped region is a doped area and the biased wire is electrically connected to the second doped region 1630~163

In another embodiment of the present invention, the ESD protection units 1607 1616 can be implemented by using two p-type MOS transistors in series. Therefore, the substrate 603 is an N-type substrate (or N disposed in the p-type substrate). The well is) the first doped region is an N+ doped region and consumes a system voltage, the second doping @1630~1631 is an N-doped region, and the second conductive path 16〇2 is a system voltage line.

Figure 17 is a top plan view showing an electrostatic discharge protection layout in accordance with a preferred embodiment of the present invention. Referring to Fig. 17 and Fig. 16A, the difference between this embodiment and Fig. 16A is that the second dummy regions 1632 to 1635 are disposed within the range of the N+ doping regions 1612, 1614, 1616, and 1618. The third holding region 1632~1635 is isolated from the N+ doped regions 1612, 1614, 1616, 1618 by field oxide layers (or other isolation techniques), respectively. The third doped regions 1632~1635 are P+ doped regions, and the bias wires 16〇5 are electrically connected to the third doped regions 1632~1635 to couple the bases of the internal parasitic transistors together. Figure 18 is a top plan view showing an electrostatic discharge protection layout in accordance with a preferred embodiment of the present invention. Referring to FIG. 18 and FIG. 16A, in the present embodiment, p+ doping regions 1636 to 1638 are disposed in the range of N+ doping regions 1611, 1615, and 1619, respectively. The second doped regions 1636~1638 are separated from the N+ doped regions 1611, 1615, 1619 by field oxide layers (or other isolation techniques), respectively. The bias wire 1605 of the 27 丄 324383 22247 twf.doc/n is electrically connected to the second doped regions 1636 〜 1638 to lightly connect the bases of the internal parasitic transistors. Figure 19 is a top plan view showing an electrostatic discharge protection layout in accordance with a preferred embodiment of the present invention. Referring to FIG. 19 and FIG. 16A, in the present embodiment, second doping regions 1636, 1630, 1637, 1631, and 1638 are disposed in the range of N+ doping regions 1611, 1613, 1615, 1617, and 1619, respectively. The second doped regions 1636, 1630, 1637, 163, 1638 are isolated from the N+ doped regions 1611, 1613, 1615, 1617, 1619, respectively, by a field oxide layer (or i isolation technique). The second doped regions 163〇16331,1636~ are deleted into the impurity-changing regions, and the wires 16〇5 are electrically connected to the second doping region·~163b 1636:1638 to make the base of the internal parasitic transistor Coupled together. In the electrostatic discharge protection device of the present invention, the base of the parasitic transistor of the element (four) is used, thereby stimulating the parasitic transistor to guide the electrostatic discharge electric discharge protection device. More can be two; ask another 'this electrostatic discharge device New Zealand secret layout, for, near riding electric discharge protection components mixed with u protection yuan! r not contact, and = together, no need to add extra;; The basis of the parasitic transistor has been disclosed in the preferred embodiment as above, and the iron is not intended to depart from the spirit and scope of the present invention, and can be used as 2=Run; not 28 22247twf.doc/n = Benga _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Figure 2纟h is the grounding electrode_gold oxide electric discharge protection device. The static image implemented by a particle is shown as a conventional static image. A top view of the circuit layout is shown in Figure 3B. The cross section of the layout of the electric discharge protection circuit is shown as a conventional electrostatic protection circuit. Know the static protection circuit. Shown as a conventional static protection circuit. Figure 7 is a diagram of the present invention. The electrostatic discharge protection package of the preferred embodiment Fig. 8 is a view of the present invention. ~ Preferred Embodiment Electrostatic Discharge Protective Device FIG. 9 is a view of the present invention. The electrostatic discharge protection package of the preferred embodiment Fig. 10 is a view of the apparatus of the present invention. Electrostatic discharge protection device of a preferred embodiment Figure 11 depicts an electrostatic discharge protection not according to a preferred embodiment of the present invention. 29 22247 tw/doc Figure 12 illustrates the apparatus of the present invention. The electrostatic discharge prevention of the preferred embodiment is shown in Figure 13A as a top view of the layout of the present invention. 1 Electrostatic discharge prevention of the actual reading Fig. 13B is a cross-sectional view showing the layout of the protection of the present invention. The electrostatic discharge prevention of the preferred embodiment of the month is shown in Fig. 14 as a top view of the layout of the present invention. The electrostatic discharge protection layout of the present invention is a top view of the present invention. The electrostatic discharge protection cloth of the present invention is a hard-to-implement method. The electrostatic discharge protection cloth is the electrostatic discharge of the preferred embodiment of the present invention. Anti-layout = see r is the electrostatic discharge protection layout of the preferred embodiment of the present invention:: Ermin's - Electrostatic Discharge Protection of the Preferred Embodiment FIG. 19 is a top view of the layout of the present invention. Electrostatic discharge protection of a preferred embodiment [Description of main components] VDD: system voltage VSS: ground voltage

MN1~MNi : N type MOS semi-electric 30 1324383 22247twf.doc/n MPl~MP2 : P-type 氡 氡 氡 RP1, RN1 : Resistor CPI, CN1 : Capacitance

Rdl~Rdi, Rsl~Rsi: Stabilizing resistors 101, 201: pads 102-103: electrostatic discharge protection devices 104, 204: core circuits 105~106, 205: pulse 301: P+ doping region 302: gates 303~305 '307, 311: N+ doped region 306: P+ diffusion region 308: substrate 309~310, 312: parasitic transistor 314: resistance

Ml~M4, N1~N8, D1~D4, Q1~Q4, W1~W8, XI~· Ν type MOS transistor Ρ1~Ρ8, Υ1~Υ8, Ζ5~Ζ8 : Ρ-type MOS transistor Α1 ~Α4 ' Β1~Β8, C1~C8, Ε1~Ε4, F1~F8: parasitic electric yang

Ral~Ra4, Rb1 to Rb8, Rcl~Rc8, Rel~Re4, Rfl~Rf8 : parasitic resistance

Rml~Rm4, Rq1~Rq4: resistors 701, 804, 904, 1001 '1104, 1204: pad 31 1324383 22247twf.doc/n 702, 802, 902, 1002, 1102, 1202: grounding hair 8 (U, 901 1, 1101, 1201: system voltage line 703, 803, 903, 1003, 1103, 1203: electrostatic discharge prevention

705, 912, 913, 1005, 1113, 1213: bias wires 706, 805, 905, 1006, 1105, 1205: core circuits 707 to 710, 909 to 910, 1007 to 1010, 1209 to 1210: electrostatic discharge

Electrical protection units 807-810, 907-908, 1107~1110, 1207~1208: output drive units 811, 1111, 1211: first conductive paths 1301, 1601: first conductive paths 1302, 1602: second conductive paths 1303, 1603: substrate 1304, 1604: P+ doped regions 1305, 1605: biased wire

1306, 1606: pads 1307~1310, 1607~1610: electrostatic discharge protection units 1311~1315, 1611~1619: N+ doped regions 1316~1319, 1620~1627: gates 1320-1324, 1630~1638: P+ doped Miscellaneous area 32

Claims (1)

丄22247twf.doc/n X. Patent application scope: L An electrostatic discharge protection device, including: Multi: Electrostatic discharge protection unit 'to conduct static electricity flow between a first-conductor ^ second conduction circuit, each of which Electrostatic discharge protection, single conduction f: a germanium transistor, whose collector and emitter are respectively connected to the first circuit and the second conductive path; and a first-channel-parasitic resistance, which is connected to the parasitic electricity The base plate of the crystal is between the conductive paths; and the turns, the side wires are coupled to the base of each of the above parasitic transistors. 2. The electrostatic discharge as described in the application patent (4) item i. The second conductive path is the system voltage trajectory. J: The electrostatic discharge protection device described in the above paragraph 3 of the patent scope, ', the second conductive path is a ground voltage line. ^ 々· 申 晴 晴 晴 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利Coupled to an output pad. 6. The scope of the patent application is as follows: the circuit of the electrostatic discharge protection electric discharge protection device is electrically connected to the first to the second conductive path. The electrostatic discharge protection device of claim 1, wherein each of the above electrostatic discharge protection units further comprises: The gold-oxide semi-transistor has a drain and a source respectively coupled to the first conductive path and the second conductive path, and the gate of the operating half-transistor floats. The electrostatic discharge protection device of claim 1, wherein each of the above electrostatic discharge protection units further comprises: a first gold oxide semi-transistor; and a first gold oxide semi-transistor, wherein the The first and second MOS transistors are connected in series between the conductive path and the second conductive path, and the gates of the first and the MOS transistors are respectively coupled to the second conductive circuit and the first The third conductive path. 9. The electrostatic discharge protection device of claim 8, wherein the third conductive path is a system voltage trajectory, and the second conductive path is a ground voltage trajectory. t 10. An electrostatic discharge protection device comprising: a plurality of output drive units for generating an external output signal according to a core output signal and outputting to a first conductive path, wherein each output drive unit is coupled: Λ Each of the crystal tantalum emitters is coupled to the first conductive path and a second conductive path; and a parasitic resistance 'coupled between the second conductive path of the base blood of the parasitic transistor; Bias the wire, _ to the base of each of the above parasitic transistors. The electrostatic discharge device of claim 10, wherein the first conductive path is coupled to an output pad. 12. The electrostatic discharge device of claim 1, wherein the second conductive path is a system voltage line. 13. The electrostatic discharge device of claim 1, wherein the second conductive path is a ground voltage line. The above-mentioned output drive unit further includes: a gold-oxide semi-transistor having a drain and a source respectively coupled to the electrostatic discharge protection device according to the first aspect of the invention. The conductive path 'and the gate of the MOS transistor receives the electrostatic discharge protection nest described in the item (4) ι〇> ★ The output driver unit of the mother includes: two first gold oxide semi-transistors; a gold-oxygen semiconductor transistor, wherein the first and second gold-oxygen semiconductors are between the first conductive path and the second conductive path, the gate of the second body to the third conductive path, The second metal body gate receives the core wheeling signal. The third conductive path of the electrostatic discharge protection device described in claim 15 is the system voltage trajectory, and The second conducting circuit is in the ground voltage trajectory. η· An electrostatic discharge protection device comprising: 35 22247 twf.doc/nj transistor 'its and emitters respectively transmitting the first-first conductive circuit and a second conductive path Between; edge-to-lead circuit via-guided ί=ϊ '分_ is connected between the base of the corresponding transistor and the first conductive circuit; and $ ΐί / lt wire, reduced to the base of each of the above-mentioned transistors. In the electrostatic discharge protection device, the first conductive path is coupled to an input pad. The electrostatic discharge protection armor is coupled to the first conductive path of the electrostatic discharge protection armor of JL. One round of soldering pad. Place: two applications "I range of the electrostatic discharge protection described in item 17 of the conductive path is the system voltage rail. The electrostatic discharge protection described in item 17 of the scope is connected to the ground voltage by a conductive path. An electrostatic discharge protection layout comprising: a substrate having a parasitic resistance; a second substrate disposed on the substrate as an electrode of the substrate; an ν electrical path disposed above the substrate; a plurality of the substrate above; The impurity region (4) is disposed on the substrate and does not conduct static electricity to the first conductive path and the first crystal structure with n 3 of the second conductive path; wherein the electrostatic discharge protection unit has a parasitic The electric 36 1324383 22247 twf.doc / n ^ second admixed 'disposed in the county body and disposed in the static electricity placed in a single =, wherein the second doped regions are not in contact with the electrostatic discharge prevention 7L early And a partial line disposed above the button, the wire of the test wire is electrically connected to the mother-second second doped region. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The two conductive paths are system voltage rails. The office 25 is as described in claim 22, wherein the second conductive path is a grounded electrical trajectory. 5 layout 22 items of static electric protective cloth eight 1f mother above electrostatic discharge protection unit including · more circuit == road == from the first - lead to the second conductive circuit ^ and the gold oxide semi-transistor Idle and lightly connect 27. For example, in the 22nd application of the Patent Park, each of the above-mentioned static electrostatic discharge protective cloth circuits is connected to the first guide by the pole and the source, and the material is the above-mentioned electrostatic discharge protection sheet. 1 = static Wei electric protective cloth one brother - gold oxygen semi-transistor; and 37 丄: > δ: > 22247twf.doc / i a second gold oxide semi-crystal, wherein the first and second gold oxygen The half body is connected in series between the first conductive path and the second conductive path. 曰曰29. The electrostatic discharge protection layout of claim 28, wherein the first and second MOS transistors The gates are each lightly connected to the second conductive path and a third conductive path. u 30. The electrostatic discharge protection cloth according to claim 29 In the office, the third conductive path is a system voltage track, and the second conductive circuit is protected by a ground voltage track. The electrostatic discharge protection device of claim 29, wherein the second conductive path is a system voltage line and the third conductive line is a ground voltage track. A plurality of third doped regions of the ESD protection cloth according to claim 28, disposed in the substrate and disposed between the and the second gold oxide semi-transistor, and the third Change zone does not turn Connected to the bias: ί:: bulk contact 'where the third doped regions are electrically centered. The electrostatic discharge protective cloth described in Item 32 of the monthly patent;: gold oxygen;;: the layer is isolated from the first part - the first and second are ': field specific oxygen:: separation; 24 said static electricity Electric discharge protection unit. Some of the two doped regions and the electrostatic discharges 35. An electrostatic discharge protection layout, comprising: 38 22247twf.doc / n a substrate; a: one ^ two / / is disposed in the substrate 'as the electrode of the substrate a plurality of static electricity are disposed above the substrate; an electrostatic discharge prevention antimony doping region is in contact with the substrate, and is disposed between the substrate and the first and second conducting circuits, and the I ^ static current flows through the first a conductive path and the first-to-first electrostatic discharge protection unit include: a half transistor; and a first gas-a π transistor connected in series to the first body, wherein the first and second gold Oxygen is disposed between the plurality of third doped regions and the second conductive path; and the second gold oxide semi-transistor is disposed in the substrate and disposed in the first-half transistor phase 2 The doping is coupled to each of the above third doped bodies, wherein the bias wires are electrically connected. 36. If applying for a patent scope bureau, the first-electrostatic discharge protective cloth 37. If the patent application scope 35th household office '=;=, unified electricity = electric discharge protection layout, t the second special guide == Item: The line of electrostatic discharge protective cloth 39. If you apply for the scope of the 35th item, 'the bureau, which is divided into the county by the county (four) discharge protection ^ second gold oxide semi-transistor. Brother - Muqu District and the first - and 39