TWI314005B - Method and apparatus for stereoscopic display employing a transmissive active-matrix liquid crystal pixel array - Google Patents

Description

1314005 IX. INSTRUCTIONS: ONE----Technical Field of the Invention The present invention relates to a stereoscopic display method and system, and particularly to a page-switching stereoscopic display method and system: a device for use. Eighth Institute [Prior Art] The stereoscopic display system uses two such perspectives to see that only one of the two images is seen by each eye of the observer. There are many ways to provide this capability through various methods. Some of the methods of the law are commonly referred to as "page exchange (page fi coffee (8)" or frame sequential switching (framesequentiai) stereo = in these methods, the left and right perspective images are in different display periods (ie, 'left and right' The fluoroscopic image display period) is time-multiplexed = and thus displayed. Stereo lenses (such as shutter or polarized two-doors) to ensure that the left fluoroscopic image is displayed in the left fluoroscopic image: I give the left eye, and the right The fluoroscopic image is displayed in the right fluoroscopic image, and is presented to the right eye during the month. The lower autostereoscopic system has been developed, which uses optical (such as a lenticular system, a parallax barrier, and a mirror). The left perspective image is given to the left eye and presents the right perspective image, eye. These systems are expensive and encounter various technical questions 1314005 b. The restricted viewable area of the display: the face-exchange stereoscopic display system—usually suitable for interaction in the interactive scan mode of the perspective image and the right perspective image: : Line tube (10) T) display to achieve. These systems provide ° 旎 but 邠 limited by their screen size and weight. "Users have tried to exchange the page of the conventional technology: ... no method applied to the active matrix LCD (10) Panels. These panels have the advantage of increased screen size and significant weight reduction. When used for page-switched stereoscopic viewing, the line-based update mechanism used in LCD panels results in considerable interlaced image interference. The pixels from the left fluoroscopic image and the pheromone from the right fluoroscopic image are simultaneously displayed as shown in Fig. 1. This interference reduces enamel and limits the commercial acceptance of the LCD stereoscopic display system. [Invention] Therefore, the present invention The purpose of the field is to provide a page-switching LCD stereoscopic display device and method for reducing staggered image interference. The other object of the present invention is to provide this A stereoscopic display system and method 'which provides improved #4 quality and stereoscopic observation. Edited. 1314005 Based on these purposes, which will be discussed in detail below, The improved stereoscopic display device and method includes a liquid crystal type transmissive pixel array that is loaded with a desired analog voltage potential signal for display during both the left perspective 1 display period and the right perspective image display period: It is cleared (ie, set to -"dark" state.) This way = avoids interlaced image interference between left and right perspective images and improves the quality of stereoscopic experience. The display device is adapted to erase all of the pixels of the array prior to being displayed during the display of both the left fluoroscopic image display period and the right fluoroscopic image display period, with the desired analog voltage potential signal being loaded. All of the gate lines of the array are simultaneously enabled to simultaneously provide a voltage potential signal that produces a "dark" element to all of the source lines of the array. In a second embodiment, the array includes a reset line for each column of the memory. The host element includes a discharge transistor that, when activated, provides a conductive path for discharging the storage capacitor of the pixel. The reset of the predetermined column (4) The batch of the discharge transistor electrically connected to each pixel of the predetermined column is also the bud 43; , ·^ Control electrode. These elements are contained in a desired analog voltage potential signal for display prior to display during both the left fluoroscopic image display period and the right fluoroscopic image display period. This removal is achieved by initiating a reset line for all columns of the array. The activation of these reset lines initiates the conduction path provided by the discharge transistors of all of the pixels of the array. In another embodiment, an improved stereoscopic display device and method includes a liquid crystal type transmissive halogen array. During the right fluoroscopic image display period, the pixel of the array carries an analog voltage potential signal corresponding to a left perspective image, while displaying a front right perspective image. Similarly, during the left fluoroscopic image display period, the pixel of the array carries an analog voltage potential signal corresponding to a right fluoroscopic image while displaying the front left fluoroscopic image. In this way, the interfering image interference is avoided and the left and right fluoroscopic image display periods can be expanded. The above described objects, features, and advantages of the present invention will become more apparent and understood. A functional block diagram of a three-dimensional transmissive active matrix LCD flat display system embodying the present invention includes a top-side video processor 12 that interfaces with an active matrix LCD flat panel display. The front end video processor 12 generates and outputs a picture continuously switched stereo video signal representing a sequence of images comprising a sequence of left and right perspective images (or pictures) to be displayed on a transmissive active matrix liquid crystal pixel array 16. A backlight and a rear polarizer (not shown) emit polarized light from behind to the array of penetrating books 10 to 1314005 1 gas correction replacement page j =. - The front polarized light is not shown between the penetrating pixels of the array 6 and the observer. In a preferred embodiment, the left and right sides of the digital video signal are continuously switched according to the 24-bit RG (red, green, blue, horizontal sync, vertical sync, pixel clock) digital format. Other digital video formats can also be used. The front-end video processor 12 can be implemented as a computer-based graphics engine, a receiving-in-one or satellite television signal set-top box, a video player (such as a DVD player), and a direct field, A dedicated 3D game console, or part of another suitable audio/video component. Display 14 includes an interface block 18 that receives successively switching digital video signals from the front side of the front end video processing benefit 12. In the preferred embodiment, the continuous switching of the digital video signal is transmitted from the front end video processor 12 to the interface block 18 through a phase communication channel using a low (four) difference (four) transmission (_). In this configuration, interface block 18 includes a brain interface circuit and a de-Serializer. As is well known, the interface block 18 restores the red, green and blue sinus data encoded in the digital video continuously switched on the side of the picture - perhaps re-scaling these sinus data and red, green and blue sinus data Transfer to a row of drivers 20. As is well known, it also includes a timing signal generator and control circuit, 1314005 with which generates a clock channel and other timing control signals that are provided to the row driver 2 idler driver 22. The gate driver 22 and the row driver 20 cooperate to load an active pixel of the array 16 having an appropriate analog voltage level corresponding to the red, green and blue pixel data supplied to the row drive _ 2G. Maintain this voltage level ^ ^ ± bb, corresponding to the active written two public, time period (the period of its - face). In order to perform this function, 'line drive-=good includes: a plurality of shift registers and digital converters' which produce an analogy to the red, green and blue pixel data provided there. The 昼 position 'and the plurality of source drivers' provide the t-type + wei, & voltage level to each of the t source lines S°, &, ... Sx of the pixel array 16. The polarity of these analog voltage levels is the same as the - inversion mechanism (for example, pixel inversion, sub-book symplectic inversion), so as to prepare for the day 1 Ding Dan I point 0 曰 to avoid liquid helium极化 The polarization of the material and reduce flicker. :::Moving $22 contains a plurality of addressing logics and drivers, which select ~j to start and terminate the bit line G of the pixel array 16. When the 22 and the actuator 22 activate a gate line (such as the gate line G) of one of the arrays of the array 16, the source lines S, Si, and Sx of the W, Chen, and Tian Hui columns are仃 〇 〇 〇 〇 〇 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 。 。 。 。 。 。 。 。 。 。 。 。 。 Figure 3 (A) shows a schematic diagram of an exemplary active pixel structure. ,131119F (Lion ^ month) doc

SUNDIAL CONFIDENTIAL In this configuration, the halogen has a storage S» (which is connected to the electrical device cs, a source line of the halogen), and the domain-gate source line S is a film; J: Body;,). : This pixel is used to connect to the electric: path of the storage capacitor C to select both the first plate and the liquid crystal cell: the lower electrode (shown by its parasitic electric power). Storage Capacitor • The youngest brother – the board is connected to the (four) position. The transparent of the liquid crystal cell • The electrode is connected to a reference voltage (for example, the ground potential as shown). The gate line Gn for this pixel is connected to the control electrode (gate) of the transistor T1. A color filter material (not shown) is incorporated into the pixel structure 'to selectively pass a desired color band of light (eg, 'red color red light, blue color blue light, and, The green light of Thai color is). The electrical piezoelectric position stored on the storage capacitor 提供 provides a voltage difference between the lower and upper pixel electrodes that controls the alignment of the LC material therebetween. This control of the alignment of the material of the unit provides control over the polarization of the light emitted therefrom and is used as part of a light valve to control the gray scale light intensity of the element. The elemental element and the lower electrode of these elements are integrated on a transparent glass substrate. The electrodes above these elements are positive & on a pair of transparent glass substrates. A liquid crystal material is disposed between the two substrates to effect such a penetrating liquid of the array 16 13 13 1 400'S H9F(»BJ).doc

13 1 400'S H9F(»BJ).doc SUNDIAL CONFIDENTIAL Crystal early. During the loading action, the gate (4) If U ϋϋ Gn ' causes the current path of the transistor Τ 1 to be activated. Line _ 2 〇 shows the desired voltage potential signal above the source line Sra, which is loaded by the current path of the transistor 1 being activated.

To the storage capacitor Cs. The PM k Sr* 4 W interpole driver then terminates the gate line Gn, which causes the current path of the transistor T1 to be terminated, thereby insulating both the storage capacitor Cs and the liquid crystal cell from the source line Sn. During this period of time (which is in the retention period 矣+, also in the case of the power), the charge from the storage capacitor maintains the desired voltage potential (4) applied to the liquid crystal cell. This hold state continues to exist during the active face-to-face execution of these load and hold actions for each column of the pixel array 16. After the period of the ::face has expired, these load and hold actions are performed throughout the columns of the next pixel array 16 . According to the invention, the driver 14 of the display 14 is provided. The system is adapted to enable the pixels of the array 16 to have the desired analog voltage image display period and the right fluoroscopic image in the frame. The left perspective image & During the period, the display is cleared (that is, set to one). In this way, the interlaced image between the right perspective images is dried 1) and the quality of the stereoscopic experience is improved. J314&&Su9F(mm -d〇c

SUNDIAL CONFIDENTIAL Figures 3(B), 3(C), 3(D)(1) and 3J)(ii) show a - embodiment of the present invention whereby the row driver 2 and the gate driver 适合 are adapted to perform a The sputum removal action of the face. As shown in the flowchart of Figure 3(8), these actions are performed by Initialization-Index 1 (which represents the number of starting columns in each picture) and a variable book (which represents the total number of columns in this array and each picture). Start at block 3〇1. In block 303, a face-based pixel removal operation is performed in which the idle driver 22 simultaneously activates all of the gate lines of the array 16.

Gl, /.Gy (G° <-m, ··· Gy&lt;=, r), and the row drive is 20 to drive all of the source lines Sq, Si of the array 电压 by generating a voltage potential of one of the "dark" elements. ...Sx. In block 3〇5_315, the column-based load and hold actions are performed throughout the columns of the array of current pictures. In block 〇5, a counter "(which indicates the column in which the month J is located) is assigned to index i, and a counter indicating the total number of columns processed in the loop of blocks 305-315) is initialized to 0. In block 3〇7, the gate driver 22 activates the pole line Gr (Gr &lt;=, 1,) between the columns r. In block 3〇9, the row driver 2〇 corresponds to the red, green and blue pixel data of the pixels of the column, and the source line s of the array 16 is driven by the analog voltage level and polarity. . , Sl, ... Sx. This data is transferred to row driver 20' in block 321 and converted from digital form to 15 1314 Θ©5 119F (5I^ Ming) in block 323.

1314Θ©5 119F(5I^明).doc SUNDIAL CONFIDENTIAL Analogy. As a result of blocks 307 and 309, for each of the columns r, the current path of the T1 transistor is activated for a given voltage, and the desired voltage potential signal system is activated via the transistor. The current path is loaded into the memory capacitor Cs of the predetermined pixel. In block 311, the gate driver 22 terminates the supply of the gate line Gr (Gr &lt;= '0,)' which causes the current path of the T1 transistor to be terminated for each element of the column r, thereby The storage cells and liquid crystal cells of the columns are insulated from their corresponding source lines. In this case, the voltage potential signal maintained by the charge stored in each of the stored electricity (4) is applied to the corresponding liquid crystal cell. This state of persistence continues during the active period. In block 313, the current column counter r is updated by a function ^ and the count II TR is incremented. In the preferred embodiment, the initialization of the column counter r and the function fr are adapted to provide an allocation throughout the panel 16 The smooth and balanced illumination of the series. In block μ, it is determined whether all columns of this array 16 have been processed (i.e., TR = NR). If no, then the action returns to the block win 313 to carry the person and keep the pixels of the lower-column. If yes, then these actions continue to block 317 to wait - the update timer expires. This termination marks the end of the display period of the current face. At the end of the update timer, these actions are returned to block 3G3-315 for performing the following steps for the next 之 ) ) ) ) ) ) ; ; ; ; ; ; ; ; ; ; ; ; ; ;

^lUWIDENTlAL, the pixel removal on the screen (four) and the based on the person-made. The loading of each element of the face, the 2-motion-left perspective image display cycle shows a left perspective image 2: in a f-perspective image display cycle display - the right perspective image movement = between the parental changes ( Figure, period fluoroscopy image display period / analog of the analogy of the electric power &gt; 1 potential for the second = Γ 1120 received the corresponding left fluoroscopic image of the red, green and blue pixel data of the Beca. During the period, the analog voltage potential signal of the pixels that are carried to the array is output from the corresponding right perspective material received by the row driver 2G. The green light color data is 0. Figure 3 (0 shows the gate Actuator 22 acts to initiate and terminate the gate line of array 16 as part of the face-based pixel removal action and column-based manned and reserved actions of Figure 3(8). - Figure 3(D)(1) and Ii) Using the action of the shutter lens, the temporal relationship between the pixel clearing action and the loading and retaining actions of Figure 3(B) is respectively displayed. These actions provide an improved stereoscopic view. Figure 3(]))(ϋ) As shown, the shutter lens is controlled to be in the "left" mode And &quot;Right view, the mode changes alternately. In the &quot;left view&apos;, mode, the displayed image reaches the left eye via the left lens of the lens, but is blocked by the right lens of the lens.

SUNDIAL CONFIDENTIAL * 13 1 40 County 119F (face).doc "Right view M mode" is displayed image through the right lens of the lens to the right eye 'but blocked by the left lens of the lens. The lens is in the "left view" mode and right Switching between the "view modes" preferably occurs during the face-based pixel removal action of the display as shown and is based on the synchronization signal transmitted from the interface block 18 to the shutter lens (FIG. 2) • The corresponding left and right perspective images show cycle synchronization. The sync signal may be passed from the interface block 18 to the shutter lens through a wired or wireless communication link. 4(A), 4(B), 4(C), 4(D)(i) and 4D(ii) show a second embodiment of the present invention whereby the main animin structure, the row driver 20 and the gate are made The pole driver 22 is adapted to perform a pixel removal action using a reset line (each reset line is connected to one of the array pixels in the array 16). In the second embodiment, the gate driver 22 and the row driver 20 of the display 14 are adapted such that the pixels of the array 16 are cleared before the pixel carries the desired analog voltage potential signal ( Also • that is, set to a &quot;dark&quot; state. In this way, staggered image interference is avoided (Figure 1). Figure 4 (A) shows an alternative to an active halogen structure in accordance with one of the present invention. In this configuration, the halogen has a storage capacitor Cs, a source line (which is connected to the pixel of the array m), and a gate line and a reset line Rn (which are connected to the array) Column η 昼 )). For, 1314005 U9F (seam) -

This is the source line &amp; The capacitor ^ indicates that the transparent upper electrode of the two j liquid crystal cells is connected to a reference voltage (for example, a ground potential). The second board of the library capacitor is also connected to a reference voltage (for example, the ground potential as shown). For this purpose, the gate line Gn is connected to the control electrode (gate) of the transistor T1, and the reset line Rn is connected to the control electrode (gate) of the transistor Τ2. The current path of transistor T2 selectively connects the first plate of the storage capacitor (: 3 to the second plate. The color filter material (not shown) is incorporated into the pixel configuration for selective passage of expectations. The color band of light (for example, red light of red halogen, blue light of blue halogen, and green light of green halogen). The voltage potential stored on the storage capacitor Cs is provided between the lower and upper pixel electrodes. a voltage difference that controls the alignment of the material therebetween. This control of the alignment of the LC material of the unit provides control over the polarization state of the light emitted therefrom and is used as part of a light valve to control The gray-scale light intensity of the halogen. The active element and the lower electrode of these elements are integrated on a transparent glass substrate. The electrodes above these pixels are integrated on a pair of transparent glass substrates. The material is placed between the two substrates, 13 1 4QQ5ll9F (Zhang Xinming).doc

SUNDIAL CONFIDENTIAL is used to implement such penetrating liquid crystal cells of array 16. During a reset action, the drain driver 22 activates the reset line Rn' which causes the current path of the transistor T2 to be activated. The interpole driver 22 also drives the current column (the gate of the GO is at a "ofr" level (eg, 'Gn &lt;='〇'). This will clear any stored capacitors via the transistor Τ2's enabled current path. The charge of Cd, thereby applying a -zero voltage signal to the liquid crystal cell, thereby producing a &quot;dark&quot; halogen. After completing the reset action, gate driver 22 terminates reset line Rn' which results in current path of transistor T2 The gate driver 22 activates the gate line 匕 during the load and hold operation, which causes the current path of the transistor T1 to be activated. The row driver 20 exhibits the desired electrical potential (4) up. The transistor τ 1 &lt; is loaded into the storage capacitor Cs by the start current path. The gate 怒 怒 怒 驱动 驱动 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 In the case of the soil &amp; section, it is insulated from the source line &amp; in this period, the charge stored in the storage capacitor is maintained by the application of the voltage potential signal in the liquid phase! in During the active picture period, the hold state relay T is maintained in an inactive state for all of these actions. These pheromone removal actions are performed for each column of the pixel array 16 20 1314© 119F (张欣明).doc

The SUNDIAL CONFIDENTIAL and the load and hold actions are shown in the flow chart of Figure 4 (β). These actions begin at block 401 by initializing an index 1 (which represents the starting number of columns in each face) and a variable NR (which represents the total number of columns in the array and each facet). In block 4〇3, a counter factory (which indicates the current column) is set to index 丨, and a counter TR (which is represented by the total number of columns processed in the loop of blocks 305-31 5) is initialized. For '〇'. In block 405, gate driver 22 simultaneously activates all reset lines R of array 16. , Rl, ... R/Rd,, r1 &lt;= Γ, ... Ry&lt;= ’ Γ ). The gate lines &, & of array 16 are driven to a &quot;off" level (Gfl&lt;=, 〇,, Gi&lt;=, 〇, ...). This is via the pixel T2 of the pixel. A current path is initiated to remove any charge stored on all of the pixel storage capacitors of array 16 from a voltage signal applied to the liquid crystal cells of the cells, thereby producing a &quot;dark&quot; The block-based load-and-hold action-system is executed in blocks 407-417 - these columns are executed throughout array 16 of the current picture. In block 4〇7, gate driver 22 terminates for the current column r Setting the line Rr(Rr &lt;='0')' causes the current path of the transistor 供2 for the elements of the array to be terminated. In block 4〇9, the gate driver 22 is activated for this column r The gate line Gr (Gr<=, 丨,) is used. In block 411, the row driver 20 is based on the pixels 21 corresponding to the column.

1314®05ii9F(雠明).d〇c SUNDIAL CONFIDENTIAL The red, green and color data of the panel, using the analog voltage level and polarity to drive the source lines S〇, Si, ... Sx of the array 16. This information is transferred to row driver 2〇 in block 421 and converted from digital form to analog form in block 423. As a result of the blocks 4 〇 9 and 411, for each of the given elements of the column r, the current path of the τ 1 transistor _ is initiated for a given element, and the desired voltage • potential 彳 § is via The current path of the τι transistor is activated and loaded into the storage capacitor Cs of the given element. In block 413, the gate driver 22 terminates the gate line Gr for the column r (Gr &lt; = 〇) which causes the current path of the T1 transistor to be terminated for each of the columns r, thereby causing the column The storage capacitors and liquid crystal cells of these elements are insulated from their corresponding source lines. In this case, the charge stored by each storage capacitor maintains the desired voltage potential signal applied to the corresponding liquid crystal cell. During the active picture, U • this hold state continues to exist. At block 415, the current column counter r is updated by a function fr and the counter TR is incremented by i. In the preferred embodiment, the initialization and function of the column counter r is adapted to provide smoothing and equalization illumination for the arrays distributed throughout the panel 16. In block 417, it is determined whether all of the columns of the array, 16 have been processed (i.e., TR = NR). If not, then the action is returned to blocks 407-415 to load and hold the next column of pixels. If yes, then this 22 Ι314βΘ^

119(090227)CRF psnrii~~ η

D 月 SUN SUNDIALCONFIDENTIAL L---- Some actions continue to block 419 to wait for an update timer to terminate. The cessation termination marks the end of the display period of the current face. When the update timer expires, these actions revert to block 403-417 to perform a pixel clearing action and a column based loading and retaining action for the pixels of the next frame. The loading and reserving actions of these pixels of each picture are based on a left perspective image display period display - the action of the left perspective image and alternating between the action of the right perspective image display period and the right perspective image Change (Fig. 4(D)(i)). During the left fluoroscopic image display period, the analog voltage potential signals of the pixels loaded to the array J are red, green and blue pixels from the corresponding left fluoroscopic image data received by the row driver 20. Data export. The analog voltage potential signals of the pixels loaded into the array during the right fluoroscopic image display period are red, green and blue pixels from the corresponding right fluoroscopic image received by the 仃 drive g 2 系Data export. Fig. 4(C) shows the action of the gate driver (2) when starting and terminating the closed and reset lines of the array as part of the pixel capture and hold and hold operations of Fig. 4(8). Fig. 4(D)(i) and (ii) using the action of the shutter lens to show the sound of Fig. 4(B), and the master's forgetting knives; the straightforward research and the loading and retaining action Zhao Relationship. This action also raises the # &amp; $ temporary action for improved stereoscopic view. Figure 4 (D) (iu 23

I314M§3119(090227)CRF 9| 4 11 Correction Replacement Page 丨 SUNDIAL CONFIDENTIAL The shutter lens is controlled to alternate between the &quot;left-view&quot; mode and &quot;right-view&quot; mode. In the &quot;left view&quot; mode, the displayed image reaches the left eye via the left lens of the lens but is blocked by the right lens of the lens. In the right view mode, the displayed image passes through the right lens of the lens to the right eye, but is blocked by the left lens of the lens. The switching of the lens between the &quot;left-view&quot; mode and &quot;right-view mode&quot; preferably occurs during the initial period of the pixel clearing and loading and reserving actions of the display as shown, and is based on the interface block 18 The synchronization signal (Fig. 2) transmitted to the shutter lens is synchronized with the left and right fluoroscopic image display periods corresponding to the display. The sync signal may be passed from the interface block 18 to the shutter lens through a wired or wireless communication link therebetween. 5(A), 5(B), 5(C), 5(D)(i) and 5D(ii) show a third embodiment of the present invention, whereby the main animin structure of the display 14 and the row driver are 20 and gate driver 22 are adapted to perform interlaced pixel insertion and display operations. In the structure of FIG. 2(A), the interlaced pixel loading and display operations are performed throughout the sequential color components, and the sequential color components are configured to continuously switch the digital video signals from the front-end video processor 12 to the interface of the interface block 18. Encoded left perspective image and right perspective image. For example, consider the system in which the display sub-period of the green color component of the left or right fluoroscopic image that is directly shot from the reflex pixel array is before the display sub-period of the blue color component. 24 Ϊ3 1 4^eQ^3119(090227)CRF Year 4 ·Net/j SUNDIAL CONFIDENTIAL In this illustrated system, the display of the color component of the blue color component of the left or right fluoroscopic image and the green color component The movements are staggered. In the structure of Fig. 2(B), the 'interlaced pixel loading and display operation' is performed over the left perspective image and the right perspective image encoded by successively switching the digital video signals by the picture. In the configuration of Fig. 2(B), during the right fluoroscopic image display period, the pixel of the array carries an analog voltage potential signal corresponding to a left fluoroscopic image while displaying a front right fluoroscopic image. Similarly, during the left fluoroscopic image display period, the pixel of the array carries an analog voltage potential signal corresponding to a right fluoroscopic image while displaying the front left fluoroscopic image. In both configurations, interlaced image interference is avoided (Figure 1). Moreover, this interlacing action avoids the time lag between the active display of the component images in the structure of Fig. 2(A) and the time between the active display of the left and right fluoroscopic images in the structure of Fig. 2(B). The stagnation increases the viewing period of the left and right fluoroscopic images and improves the quality of the stereoscopic view. Figure 5 (A) shows another active halogen structure in accordance with the present invention. In this configuration, the pixel has two storage capacitors, one source line S, which is connected to the array m, and the two closed lines (which are connected to the array) η**). Two control lines are connected to the second source of the array. The source line S« is selected by the current path of a thin film θ θ 涛 电 电 25 25 25 | | sun sun sun sun | sundialconfidential

3 ^1^^3li9 (〇9〇227) is CRF-connected to the first plate of the storage capacitor. The source core is also selectively coupled to the first plate of the storage capacitor c% by the current path of the thin film transistor T4. The first plate of the storage capacitor q is selectively connected to the transparent lower electrode of the liquid crystal cell (represented by its parasitic capacitance ^) by the current path of the γ thin film transistor T2. The container d-plate is selectively connected to the transparent lower electrode of the liquid crystal cell (represented by its parasitic capacitance Clc) by the current path of the thin film transistor T3. The transparent upper electrode of the liquid crystal cell is connected to a reference electrical waste (e.g., ground potential as shown). The second plate of the storage capacitor Cs and the second plate of the storage capacitor 匕 are also connected to a reference voltage (e.g., a ground potential as shown). Ask the pole wire to connect to the control electrode (gate) of the transistor τι. The closed line G% is connected to the control electrode (closed pole) of the transistor T4. The control line L is connected to the control electrode (closed pole) of the transistor Τ2. The control line is connected to the control electrode of the transistor η (closed pole). The color filter material (not shown) is incorporated into the pixel configuration to selectively pass a desired color band of light (eg, red) The painting $ $ A Α ^ 匕 the red first of the heavy animal, the blue of the blue pixel and the green light of the green pixel). The voltage potential stored in the storage capacitor & provides a voltage difference between the lower and upper pixel electrodes It controls the alignment of the LC material in between. This rhyme is controlled by the alignment of the LC material of the unit, providing information about the light emitted from it. 26 I314〇as 119F (Zhang Xinming)_doc I314〇as 119F (Zhang Xinming)_doc

The control of the polarization state of SUNDIAL CONFIDENTIAL is used as part of a pupil to control the grayscale light intensity of the element. The active element and the lower electrode of these elements are integrated on a transparent glass substrate. The electrodes above these elements are integrated on a pair of transparent glass substrates. The liquid crystal material is disposed between the two substrates of the substrate to realize the transmissive liquid crystal early elements of the array 16. As shown in the table of FIG. 5(B), during the right fluoroscopic image display period, the gate driver 22 terminates the control line L (L &lt;=, 〇,), which causes the current path of the electrical body T2 to be an array. All of the elements of 6 become the inactive current path of the inactive electrode body 2, so that the first plate of the storage capacitor Cs is insulated from the liquid crystal cells of all the pixels of the array. For a given column n of one of the arrays 16, the gate driver 22 activates the column n for the idle line Gn (Gn &lt;=, i,), which causes the current path of the transistor T1 to be the column η. initiative. The active current path of the transistor T1 connects the source line &amp; to the pixel storage capacitor Cs in column n. The first row driver 20 exhibits the desired voltage potential signal above the source lines of the array. It is loaded onto the storage capacitor cs by the initiated current path of the transistor T1, which is a mutual prime of the column η. Gate driver 22 then terminates the gate, ', (&quot;&lt; 1 )' which causes the current path of transistor T1 to be terminated, thereby causing storage capacitor Cs and the source of such pixels in column n to be 27

13* 1 4ββ§3119F(»HJ).d0C

SUNDIAL CONFIDENTIAL Line S n insulation. In this case, it is represented by the hold state or the reserved state, and the storage capacitor Cs stores the charge applied to the liquid crystal cell at a subsequent left fluoroscopic image display period to maintain the desired voltage potential signal. This hold state continues during the active right image display period. These pixel loading and holding actions are repeated for each column of array 16. - At the same time, during the right fluoroscopic image display period, the gate driver 22 terminates the pole lines d ◊ , 〇 ') between all columns of the array 16 and activates the control line r (r "-]'). The termination of the G% of the gate lines across all columns causes the transistors to be inactive for all of the elements of the array, thereby making the first plate of the storage capacitor and the source of all the elements of the array Wire core insulation. The start of the control line R causes each current path of the electric day and day T3 to become active for all the elements of the array. The active current path of the transistor Τ3 connects the mushroom storage capacitor c% to all of the liquid crystal cells of the array, so that the battery is carried to the respective storage valleys cs in the previous left fluoroscopic image display period. It is applied to the corresponding liquid crystal cell for display. In the left perspective image display period „, the gate drive (four) 22 control tank &lt;=, 〇 ') ' it leads to the current path of the transistor T3: all the elements of the array 16 become inactive. The transistor is not active 28 13 1 4QeQ^3U9F (Lion Month).doc

_ SUNDIAL CONFIDENTIAL The current path is such that the first board storing the electric shock H々VC s and all the liquid crystal units of the array are all in the same row as the first column 16 and the gate driver 22 n &amp ; &amp; ° Start the supply "Use the gate line (10) &lt;= -., the current path of the crystal T4 is the active of all the elements of the column n. Electro-crystal 舻 ~ ~ J η (all paintings connected to the storage of the active current path The source line S is connected to the first board of the storage capacitor Γ* 。. The row driver 20 exhibits a 'bit signal' to the source lines of the array, which is thereby stupid by the column η The circuit of the crystal chip 4 is activated and loaded onto the storage capacitor C%. The idle driver 22 then terminates the gate line, which causes the motor path to be terminated, thereby making the storage capacitor Insulated with the source line S» of the elements in column n. In this case, its /糸, hold state or retention state indicates that the storage capacitor is stored in the subsequent right fluoroscopic image display period to maintain the desired The voltage potential signal applied to the liquid crystal unit This hold state continues during the active left fluoroscopic image display period. These pixel loading and holding actions are repeated for each column of the array 16. Meanwhile, during the left fluoroscopic image display period, the gate driver 22 Terminating the gate line Gn (Gn &lt;= 〇) across all columns of the array 16, and starting the control line L (L &lt;=, 1,). Termination of the gate line Gn throughout all columns results in the transistor τι Each of the current paths for this array 29 13 1 4 &amp; 119F__, d 〇 c all 4 * become the inactive °nfidential board and all the (four) capacitors k of the array of the first lining source line & insulation @Start-up leads to the transistor f control line L ^ * . . . ^ Each current path is the active of this array. The electron crystal is in the "all active current path container" connected to the turn & The stored liquid J &lt; all the liquid crystal single previous right perspective image is dried 3 so that the voltage loaded in the middle of each storage capacitor Cs during the crying period is applied. The main corresponding liquid crystal unit is for Display (6) shows that the idler driver 22 is starting and terminating When the gate line of the array and the control line are... ^ ^ &lt; action as part of the soft parent error as described above with respect to Figure 5 (8) ~ retaining action and display action. Figure 5 (8) (1) and ((1) using the action of the shutter lens, Figure 5 (8) shows the temporal relationship between the interleaved element loading/retention action and the display action. These actions provide an improved stereoscopic view. As shown in Figure 5(d) (the '(4) lens system is controlled to be in &quot;left view" The parental change between the pattern and the &quot;right view" mode. Yu, Zuo Yu, the left-handed wedge, and the left-view wedge, the displayed image reaches the left eye through the left lens of the lens, but is blocked by the right lens of the lens. In the "right view" mode, the image is displayed via the right lens of the lens to the right eye, but is blocked by the left lens of the mirror. The switching between the "left" mode and the "right mode" of the lens is best done in each of the 30 131 «

119 (090227) CRF 曰 correction replacement page

SUNDIAL CONFIDENTIAL The left and right fluoroscopic image display periods are synchronized during the initial period of the left and right fluoroscopic image display periods and in accordance with the synchronization signal (Fig. 2) transmitted from the interface block 18 to the shutter lens. The sync signal may be passed from the interface block 18 to the shutter lens through a wired or wireless communication link therebetween. Several embodiments of the stereoscopic active matrix liquid crystal planar display system and the methods and mechanisms used therein have been illustrated and described herein. Although specific embodiments of the invention have been described, these specific embodiments are not intended to limit the invention, as the scope of the invention is intended to be construed as broadly as the kind. Thus, while specific system structures and specific pixel configurations have been disclosed, it will be appreciated that other system structures and pixel configurations can be used. In addition, although specific messaging mechanisms and control mechanisms have been exposed, we will understand that other signaling mechanisms and control mechanisms can also be used. For example, the front-end video processing block and the interface block generate and process a picture to continuously switch stereoscopic video signals. This processing is advantageous 'because it can operate on conventional (non-stereo) picture continuous (four) video signals for supply to such conventional displays that continuously switch video signals (without shutter lenses). Those skilled in the art will appreciate that the processing blocks and interface blocks can be easily adapted to other signal formats, including but not limited to - dual channel letter 1314 arbitrarily 3119_227_%4 external corrections. Age!

The SUNDIAL CONFIDENTIAL number format (that is, the left and right perspective shirt images transmitted on the physically separated channels), a single channel column interlaced signal format (that is, the left and right perspective images are tied to each other in an alternate column of each image frame). Together, a single channel over-under signal format (ie, left and right perspective images are added to the lower half of each image frame), a single channel parallel signal format (ie, left and right perspective image system) Add to the left and right sides of each image frame), a single channel line interlaced signal format (ie, 'left and right perspective images are combined on multiple lines of each image frame) and single channel dual-screen color multiplex The format (ie, the left and right perspective images are encoded by two consecutive rounds of image processing by color multiplex processing). It will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the protection of the present invention (4) is subject to the definition of the scope of the patent application. 32 m^9Mu9(090227)CRF PWWf3 SUNDIALCONFIDENTIAL [Simplified illustration] ^^^j Circle 1 is an active matrix liquid crystal display showing a conventional technique. It is also used when continuously switching stereoscopic video signals. Schematic diagram of loading and retaining actions. Figure 2 is a functional block diagram of an exemplary transmissive active matrix liquid crystal display device embodying the present invention. Fig. 3(A) is a schematic diagram showing an exemplary main animation structure of the pixel array of Fig. 2. 3(B) is a diagram showing a face-based pixel clearing action and a column-based loading implemented by a row driver and a gate driver of a circle 2 according to a first embodiment of the present invention. A flow chart with the retained action. 3(C) is a view showing the action of the gate driver of FIG. 2 when starting and terminating the gate line of the pixel array, as part of the pixel clearing action and the loading and reserving action of FIG. 3(B). schematic diagram. Fig. 3(D)(i) and (ii) are schematic diagrams showing the temporal relationship between the pixel removal operation of Fig. 3(B) and the manned and reserved operation by the action of the shutter lens. Fig. 4(A) is a schematic diagram showing one of the pixel arrays of Fig. 2 in place of the main animin structure. 4(B) is a diagram showing a book 33- 1314 off 119_7) crf s_alc__al j element clearing action and loading implemented by the row driver and the question mark driver of the display device of FIG. 2 according to a second embodiment of the present invention. The process circle with the reserved action. FIG. 4(C) is a diagram showing the action of the gate driver of FIG. 2 when starting and terminating the gate line and the reset line of the pixel array, as the pixel clearing action and loading and retaining of FIG. 4 (β). Schematic diagram of one of the actions. Fig. 4(D)(i) and (u) are schematic diagrams showing the temporal relationship between the pixel clearing action of @4(B) and the manned and reserved actions, respectively, by the action of the shutter lens. Fig. 5(A) is a schematic diagram showing still another main antherin structure of the pixel array of Fig. 2. Fig. 5 (8) shows a table of interleaving loading and display operations by the row driver and the gate driver of the display device of Fig. 2 in accordance with the third embodiment of the present invention. Fig. 5(6) is a view showing the action of the gate driver of Fig. 2 when starting and terminating the gate line and the control line of the array, as a part of the intersection of the circle 5 (8) and the display operation. The other two i1) is the action of the shutter lens, which is indicated by I. The temporary relationship between the father and the display action [Main component symbol description] Cu: parasitic capacitance

Cs: storage capacitor 34 1314 brain

SUNDIAL CONFIDENTIAL

3119(090227)CRF fr :function Go : gate line Gn · gate line Gr : gate line i : index L : control line NR : variable r : counter R : control line R〇 : reset line Rn : reset Line Rr : Reset line S» : Source line T1 : Transistor Τ 2 : Transistor Τ 3 : Transistor Τ 4 : Transistor TR : Counter 301-323 : Method steps 401-423 : Method Step 10 : Active matrix LCD plane display System 35

SUNDIAL CONFIDENTIAL 1314UeQ^3119(090227)CRF%4.Monday 14 Amendment Replacement Page丨________________! 12: Front End Video Processor 14: Active Matrix LCD Flat Panel Display 16: Alizarin Array/Panel 18: Interface Block 20: Row driver 22: gate driver 36 — --1

119 (090227) CRF

1 W replacement page of SUNDIAL CONFIDENTIAL 9 j _ , --------------1 image while displaying the preceding second perspective image. In this manner, cross-frame image interference is avoided and the left and Right perspective image display periods can be expanded.

I3HPeP^3119(090227)CRF

During the right perspective keying display period, a plurality of voltage potential signals are supplied to the source lines of the array, and the one gate line of the corresponding gate pair is activated to The source lines load the voltage potential signals into the first storage capacitors of the pixels of the array, and the second control line is activated to utilize the images in the array. The (4) two storage capacitors of the voltage potential signals to drive the transparent liquid crystal cells of the pixels of the array; and two of the plurality of voltage potentials are broken during the left fluoroscopic image display period Providing the source lines to the array, the other pair of lines of the corresponding closed line pair being activated to carry the voltage potential signals from the source lines to the array The second storage capacitors of the pixels, and the first control line is activated to drive the array by using the electrical potential signals stored on the first storage capacitors of the pixels of the array Some of these pixels should be worn Liquid crystal cell. The display device according to any one of claims 1 to 7 wherein the synchronization signal is transmitted to the shutter lens. 2. A display device as claimed in claim 19, wherein: 49

^14F^3119(〇9〇227)CRF 9养养月11 Revised replacement page丨SUNDIAL CONFIDENTIAL The shutter lens receives the synchronization signal and uses the synchronization signal to synchronize the left and right view modes with the left and right perspective image display cycles, respectively. . The display device according to any one of claims 1 to 7 wherein the at least one video signal is generated by the display device. The display device according to any one of claims 1 to 7 wherein: the at least one video signal comprises a picture continuously switched stereo video signal. The display method according to any one of claims 8 to 14, wherein: a synchronization signal is transmitted to the shutter glass. [24] The display method of claim 23, wherein the shutter lens receives the synchronization signal and (4) the same = the left and right view modes and the left and right perspective images display week: to 14 items and 17th to 18th The display method according to any one of the claims of claim 8, wherein the at least one video signal is a 50

B1 ring 3119 (090227) CRF gas 4314 revision 刽 3 SUNDIAL CONFIDENTIAL, the display device includes the transmissive liquid crystal type pixel array. The display method according to any one of claims 8 to 14, wherein the at least one video signal comprises a picture continuously switching stereoscopic video signal. 51

Claims (1)

SUNDIAL CONFIDENTIAL ]31 4#0#ii9f( earning).d〇c X. Patent application scope: 1. A display device comprising: a receiving hand for receiving a representation comprising a left perspective image and a right perspective image - At least a video signal of the phase pair; a transmissive liquid crystal halogen array comprising a plurality of transmissive liquid crystal elements; and a deriving means for relying on at least one video representing the left fluoroscopic image Corresponding part of the signal, one of the first set analog voltage signals for the pixels of the array is derived; a clearing means for setting one of the corresponding ones of the first set of analog voltage signals to one The pixel is used to clear the predetermined pixel of the array before being displayed during the image display period; and the method is further configured to reduce the corresponding portion of the video signal according to the right perspective image. Deriving a second set of analog voltage signals for the pixels of the array; and another π removing hand &amp; for loading one of the corresponding ones of the second set of analog voltage signals to the The predetermined pixel of the array is cleared before it is displayed during the right image display period. 2. For the display device described in the first application of the patent specification, the package includes 37 I314〇£5 FlIe: TW3119F (张欣明).doc contains: SUNDIAL CONFIDENTIAL a means for loading the first group of analogies Clearing any one of the voltage signals to the corresponding pixel for clearing all pixels of the array before the left fluoroscopic display period is displayed; and a second means for using the second group analogy Any one of the voltage signals is carried to the corresponding pixel for clearing all the pixels of the array before being displayed during the right fluoroscopic image U display period. The display device of claim 2, wherein: the δ ray array comprises a plurality of gate lines and a plurality of source lines, each of the idle lines corresponding to a specific column of pixels, each of the sources The line corresponds to a / specific row of pixels, each of the elements comprising a penetrating liquid crystal cell, a storage capacitor and a transistor, the storage capacitor is electrically connected to the penetrating liquid crystal cell, the electric S chain day The body has a control electrode and one of the gates and the gates connected thereto to selectively activate a conduction path from one of the source lines; and The saki capacitor is used to remove the first means of all the pixels of the array, and the first number of pixels, which are suitable for providing the source of the complex source line. The gate lines are loaded with the 38 131 W3 II9F (Zhang Xinming).doc SUNDIAL CONFIDENTIAL voltage potential signals from the sources to generate a plurality of dark signals to the pixels of the array. Among these storage capacitors. 4. The display device of claim 3, wherein: the gate driver circuit simultaneously activates all of the gate lines of the array to generate the voltage potentials of the dark signals from the source lines. The numbers are simultaneously loaded into the storage capacitors of the elements of the array. 5. The display device of claim 2, wherein: the array comprises a plurality of gate lines, a plurality of reset lines, and a plurality of source lines, each of the gate lines corresponding to a specific column Each of the reset lines corresponds to a pixel of the special column, and each of the source lines corresponds to a special element, each of which includes a transmissive liquid crystal cell, a capacitor: a capacitor a transistor and a second transistor, the storage electric grid is electrically connected to the transmissive liquid crystal unit, and the first electro-electrode has two control electrodes and electrically connected to the gate lines, eight middle strips , for selectively starting a conduction path of the library capacitor from one of the source lines, and the second body having a control electrode and an electrical connection to the tube - a stripe 'for selectively initiating a conduction path from the beginning of the storage of electricity; and a means for reading all of the elements of the (4) and the 39th W3119F (Ermin).d0c SUNDIAL CONFIDENTIAL II The means 'includes a pole drive suitable for starting the array between the reset lines Circuit, whereby the shape of the array of the storage capacitor of each of the discharge of these factors day to enabling each of the storage capacitor to store a plurality of dark pixels to generate a plurality of voltage potential signal. 6. The display device of claim 5, wherein: the gate driver circuit simultaneously activates all of the reset lines of the array to discharge the capacitors of the array of the pixels. The storage capacitors are stored to generate the voltage potential signals of the dark molecules. The display device of claim 6, wherein the gate driver circuit is adapted to cycle through the arrays of the arrays to load the corresponding electrical (four) bit signals on the continent and the predetermined columns. The reset line for the (4) is terminated before the element is displayed for display. ! 8) A display method comprising the steps of: receiving an image pair comprising a left perspective image and a right transparency sequence (4) providing a transmissive liquid crystal type pixel array, a transmissive liquid crystal type pixel; One of the pair of video-visual signals, the first group analogy is based on the at least part of the left-perspective image, and is derived from the SUNDIAL CONFIDENTIAL 13 i4〇ft§W3119F doc-type voltage signal for the array. Clearing the predetermined pixel basis of the array to represent the right perspective before loading the corresponding one of the predetermined set of voltage signals of the first set of analog voltage signals for displaying the period of the left perspective image display period And outputting, to the portion of the at least one video signal, a second set of analog voltage signals for the pixels of the array; and a corresponding JL loading the second set of analog voltage signals The predetermined element of the array is cleared until the predetermined element is displayed for display during a right fluoroscopic image display period. 9. The display method of claim 8 of the patent application, comprising the steps of: clearing the array if: entering the first set of analogy signals is to be displayed during the display period of the left fluoroscopic image All of the elements of the array; and 'the heart is loaded into the second set of analog voltages, the book is arbitrarily-to the corresponding one, in the middle to clear all the elements of the array before the right perspective image . Between the μ and the display method of the ninth application patent scope, the barrier includes a plurality of idle polar greens and a plurality of source lines, each of which is Ϊ3Ϊ4·Ψ3 119F (Zhang Xinming).doc SUNDIAL The CONFIDENTIAL idle line corresponds to a specific f-check, each of the source lines corresponding to the source line of the specific line, each of the _ _ A person ~, each of the elements includes a penetrating liquid crystal unit, a storage capacitor and a lightning crystal private day, the storage capacitor being electrically connected to the transmissive liquid crystal cell, the transistor having a control electrode connected to one of the interpolar lines at the portion for selective a second one of the storage capacitors from the source lines, the middle strip to the one of the storage capacitors; and by providing a plurality of voltage potentials that generate a plurality of dark substances to the Forming the sources (4) and collecting the gate lines to generate the plurality of dark signals from the source lines, and the bit signals are carried to the storage capacitors of the pixels of the array. In the middle, all the arrays are cleared Su. 11. The display method as claimed in claim 1, wherein all the elements of the array are removed by the following actions: simultaneously opening the stomach array "all the polar lines are 16 and the source lines are simultaneously generated. The voltage potential signals of the dark signals are loaded into the storage capacitors of the array. The display method of claim 9, wherein: the array comprises a plurality of gate lines, a plurality of reset lines, and a plurality of source lines, each of the gate lines corresponding to a specific Column n &lt; pixels, each of the 42 1314 · W3119F (Zhang Xinming).doc SUNDIAL CONFIDENTIAL reset line corresponds to a specific column of pixels, and each of the source lines corresponds to a specific row of pixels, each 昼The device includes a penetrating liquid crystal cell, a storage capacitor, a first transistor and a second transistor, the storage capacitor being electrically connected to the penetrating liquid crystal cell, the first transistor having a control electrode and an electrical connection One of the gate lines to be used to selectively initiate a conduction path from one of the source lines to the storage capacitor of the pixel, and the second φ transistor has a control An electrode and one of the reset lines electrically connected thereto for selectively starting a conductive path from the storage capacitor; and all of the elements of the array are cleared by: Reset line of the plurality of arrays, each of the plurality of day whereby the pixel array of the discharge of the storage capacitor to enabling each of the storage capacitor storing a voltage potential to generate a plurality of signals multiplexed plurality of dark pixel day. 13. The display method of claim 12, wherein all of the elements of the array are removed by simultaneously actuating all of the reset lines of the array to thereby make the elements of the array Each of the storage capacitors is discharged, and each of the storage capacitors stores the voltage potential signals of the dark molecules. 14. The display method of claim 13, further comprising: 43 13 Ϊ 4 (8) e § W3U9F (identified). doc SUNDIAL CONFIDENTIAL circulates through the columns of the array to utilize the voltages corresponding thereto The reset signal for the predetermined column is terminated before the potential signal is loaded into a predetermined column of pixels for display. 15. A display device comprising: a squad jacket does not include a left perspective 狡 亍 · ) ) ) 一 一 一 一 一 一 右 右 右 右 右 右 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列 序列The transmissive guilloche contains the penetrating element: a first storage capacitor of the unit and a second storage capacitor, and a derivation means for indicating the left perspective The image ^ is at least - the corresponding portion of the minus sign, the one of the feed columns is derived from the first set of analog voltage signals; - a first means - in the - right perspective image display period is used Carrying the first-group analog voltage signal into the first-storage capacitors of the corresponding pixels of the array, and simultaneously utilizing the first-sense 'second-storage capacitors of the pixels of the ρ column And storing the analog voltage signal to drive the μ ternary unit of the array, and the other derivative means for extracting the image, and the method for deriving the pixel of the image according to the corresponding portion of the at least the video signal Use one of the second group analogy Signals, · and ~, these 44 'W3119F (Zhang Xinming).doc SUNDIAL CONFIDENTIAL A second means of operating during a left fluoroscopic image display period for loading the second set of analog voltage signals to the array The second storage capacitors of the corresponding pixels, and the analog voltage signals stored by the first storage capacitors of the pixels of the array are simultaneously used to drive the pixels of the array The liquid crystal cells. 1. The display device of claim 15, wherein: the array comprises: a plurality of gate pairs, a plurality of source lines, and first and second control lines, each of the gate lines The pair corresponds to a specific column of pixels, each of the source lines corresponds to a specific row of pixels, the first and second control lines are shared by all the elements, and each element further includes the first and second And third and fourth transistors, the first transistor having a control electrode and a gate pair electrically connected to one of the gate pairs for selectively starting from a corresponding source Wired to a conductive path of the first storage capacitor, the second transistor having a control electrode and the first control line electrically connected thereto for selectively starting from the first storage capacitor to the transmissive a conduction path of the liquid crystal cell, the third transistor having a control electrode and the second control line electrically connected thereto for selectively starting conduction from the second storage capacitor to the one of the transmissive liquid crystal cell Path, while 45 'W3119F (Zhang Xinming).doc The fourth transistor has a control electrode and another gate line electrically connected to the corresponding gate pair to be selectively activated from the corresponding source line to the first Storing a conductive path of the capacitor; the first means comprising: a row of driver circuits adapted to provide a plurality of voltage potential signals to the source lines of the array; and a gate driver circuit adapted to i) initiate the And the one of the gate lines of the corresponding gate pair is loaded with the voltage potential signals from the source lines to the first storage capacitors of the pixels of the array, and ii) a second control line for driving the transmissive liquid crystal cells of the pixels of the array by using the voltage potential signals stored on the second storage capacitors of the pixels of the array; and the second The method comprises: a row of driver circuits adapted to provide a plurality of voltage potential signals to the source lines of the array; and a gate driver circuit adapted to i) activate the corresponding gate line The other gate line loads the voltage potential signals from the source lines to the second storage capacitors of the pixels of the array, and ii) activates the first control line to utilize the storage The voltage potential signals on the first storage capacitors of the pixels of the array to drive the transparent liquid crystals of the pixels of the array 46 Ι 314 〇 β ^ unit 119F (Zhang Xinming). 〇c SUNDIAL CONFIDENTIAL 17. The display method _ , &amp; A force, includes the following steps: The receiving table does not contain - at least - video signal of the left fluoroscopic image and a right fluoroscopic image / sequential image; M $ through A halogen matrix comprising a plurality of transmissive paintings. Each of the transmissive elements includes a first storage device that is operatively coupled to the first type of transmissive liquid crystal, and a second storage capacitor; the at least one of the video signals representing the left perspective image Corresponding to the J-point, the array-type voltage signal is derived; the "-----the analogy of the first-group analogy is loaded into the rut during the factory-right fluoroscopic image display period. The corresponding elements of J: the capacitor 11 is 'same' with the analog voltage signals stored in the array capacitors of the array of materials to agitate the pixels of the array. The liquid crystal cells; H indicates that the number of W is less - the pair of the nominal number = the second group of analog voltages for the elements of the array, and the second group of analog voltages; The voltage signal is loaded into ": the analogy of the brother-group, the corresponding storage element of the U in the U storage capacitor H" while using the array of the elements of the W3119F (Zhang Xinming).doc SUNDIAL CONFIDENTIAL These first storage capacitors store these classes Voltage signal to drive the plurality of the plurality of liquid crystal cell of the pixel array of the day. 18. The display method of claim 17, wherein: the array comprises a plurality of gate pairs, a plurality of source lines, and first and second control lines, each of the gate pairs corresponding to a specific column of pixels, each of the source lines corresponding to a specific row of pixels, the first and second control lines being shared by all the elements, each element further comprising first, second, third a fourth transistor having a control electrode and a gate line electrically connected to one of the gate pairs corresponding to the one of the gate electrodes for selectively starting from a corresponding source line to the first Storing a conductive path of the detector, the second transistor having a control electrode and the first control line electrically connected thereto for selectively starting from the first storage capacitor to the penetrating liquid crystal cell a conduction path, the third transistor having a control electrode and the second control line electrically connected thereto for selectively starting a conduction path from the second storage capacitor to the transmissive liquid crystal vehicle And the fourth transistor has a control Where the electrode is electrically connected to the gate of the corresponding pair of the other gate line, to selectively start from the source line corresponding to a conduction path of one of the first storage capacitor; 48