TWI312560B - Package substrate and method thereof - Google Patents
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- TWI312560B TWI312560B TW95138758A TW95138758A TWI312560B TW I312560 B TWI312560 B TW I312560B TW 95138758 A TW95138758 A TW 95138758A TW 95138758 A TW95138758 A TW 95138758A TW I312560 B TWI312560 B TW I312560B
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1312560 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板之結構及其製造方法，尤 指一種適用於細線化（Fine Pitch)封裝基板之結構及其製造 5 方法。 【先前技術】 # 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (Integration)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuit)需求。 15 以增層（Build_UP)方式製作之多層封裝基板，是在基板 馨（例如電路板）的一面或雙面，使介電層與金屬層順序增層， 而構成高密度之金屬佈線圖形。常見之封裝基板增層結構 的製作方法如圖1A至1F所示。 請參閱圖1A，首先提供—封裝基板丨〇1，其至少一表 20面具有複數個電性連接塾1〇2、以及一介電層ι〇3。該電性 連接墊102之材料一般為銅。該介電層1〇3係全面性的覆芸 於該封裝基才反UH上，其#料一般為ABF(Ajm〇m(；〇BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a package substrate and a method of fabricating the same, and more particularly to a structure suitable for a fine lined (Fine Pitch) package substrate and a method of manufacturing the same. [Prior Art] # With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 10 and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. Under the space, the interlayer area is used to expand the available wiring area on the board to meet the high electron density integrated circuit requirements. 15 The multi-layer package substrate produced by the build-up method is formed on one side or both sides of the substrate (for example, a circuit board), and the dielectric layer and the metal layer are sequentially layered to form a high-density metal wiring pattern. A common method of fabricating a package substrate buildup structure is shown in Figs. 1A to 1F. Referring to FIG. 1A, firstly, a package substrate 丨〇1 is provided, at least one of which has a plurality of electrical connections 塾1〇2 and a dielectric layer 〇3. The material of the electrical connection pad 102 is typically copper. The dielectric layer 1〇3 is comprehensively covered by the package base on the UH, and the material is generally ABF (Ajm〇m(;〇
Build up Film )。本實施例之電性連接塾〗G2係選擇性的連 接至導通孔109，並且被介電層1〇3所覆蓋。 5 1312560 由於電性連接塾1()2之結構A致相同，故後續僅顯示其 中:電性連接藝102作為代表說明。接著，對該介電層103 進打表面粗化，也就是以姓刻溶液（如過盆酸酸卸溶液）钱刻 粗化該介電層103表面，得到如圖1B所示之結構。 乂 5 隨後’如® 1C所示，於該介電層103上形成複數個介電 f開口 104以暴露出被介電層1〇3覆蓋之電性連接墊1〇2。接 著，再依序於封裝基板1〇1上形成一晶種層1〇5、以及一阻 層106。4阻層1〇6具有複數個阻層開口 ，且此阻層開口 107之位置對應於介電層開口 1〇4 '然後，以電鍍方式於阻 10層開口 107内形成一金屬層1〇8，其結構如圖1D所示。最後， 如圖1E所示，移除阻層1〇6、以及阻層1〇6覆蓋之晶種層 ，即完成一層增層線路層。重複上述步驟，依所需要之 層數層疊上去即可製作多層封裝基板，例如圖斤所示之結 構。 15 在封裝基板的增層製程中，形成晶種層105之前的介電 層1〇3(如ABF)必須先行粗化處理，以增加咬合力。如此由 晶種層105與金屬層ι〇8所構成的線路（參閱圖m)，方才具 有良好的附著力。 目前，介電層103之表面粗化方式，係利用等向性化學 20蝕刻自平坦表面向下挖深。也就是說，介電層103表面的坑 洞（參閱圖1B)是利用過錳酸鉀溶液咬蝕掉部分介電層所形 成，因此介電層103表面的起伏不明顯。然而，封裝基板的 線路愈細’線路和介電層之間的咬合面積就越小，容易造 成兩者間的咬合力不足，甚至導致線路剝落。此故，當封 1312560 裝基板之線路趨向細線化（Fine Pitch)時，以化學蝕刻方式 粗化之"電層表面已無法提供足夠的咬合力，來避免線路 剝離。 隨著構裝技術的發展，細線化（Fine Pitch)成為封裝基 板產業積極開發之方向之―，以增加可利用的佈線面積。 因此，如何增加封裝基板增層結構中層與層間的附著力， 實為亟待解決之課題。 【發明内容】 有鑑於此，本發明提供一種封裝基板之製造方法，其 Y驟匕括’ (A)提供一模板以及一基板，其中該模板表面具 有複數個凸出冑，該基板表面具有複數個電性連接塾、以 ，二介電層，且該介電層覆蓋該等電性連接墊；⑻將該模 15 20 反^印於該介電層上，在該介電層表面形成複數個溝紋， 穿透該；1電層；（C)將該模板自該介電層移開； 介電層具有該等溝紋之表面，使該介電層表面及 文之内表面粗化，並於該介電層形成複數個介電層 二門=該等電性連接塾;以及⑻於該介電層與該介 有二Li 化金屬^其中該圖案化金屬層包括 線路層以及複數個導電結構，該 1層具有該等溝紋之表面，1導電且置於4，丨 ，該線路層電性連接至過該介電層開 墊。 关至^丨電層下方之該等電性連接 7 1312560Build up Film ). The electrical connection of the present embodiment is selectively connected to the via hole 109 and covered by the dielectric layer 1〇3. 5 1312560 Since the structure A of the electrical connection 塾1()2 is the same, only the following is shown: the electrical connection art 102 is taken as a representative description. Next, the surface of the dielectric layer 103 is roughened, that is, the surface of the dielectric layer 103 is roughened by a solution of a surname (e.g., a solution of a potting acid) to obtain a structure as shown in Fig. 1B.乂 5 Subsequently, as shown in FIG. 1C, a plurality of dielectric f openings 104 are formed on the dielectric layer 103 to expose the electrical connection pads 1〇2 covered by the dielectric layer 1〇3. Then, a seed layer 1〇5 and a resist layer 106 are formed on the package substrate 1〇1. The resist layer 1〇6 has a plurality of resist layer openings, and the position of the resist layer opening 107 corresponds to Dielectric layer opening 1〇4' Then, a metal layer 1〇8 is formed in the via 10 opening 107 by electroplating, and its structure is as shown in FIG. 1D. Finally, as shown in FIG. 1E, the resist layer 1〇6 and the seed layer covered by the resist layer 1〇6 are removed, that is, a layer of the build-up layer is completed. By repeating the above steps, a multi-layer package substrate, such as the structure shown in Fig., can be fabricated by laminating the number of layers required. 15 In the build-up process of the package substrate, the dielectric layer 1〇3 (such as ABF) before the seed layer 105 is formed must be roughened first to increase the bite force. Thus, the wiring composed of the seed layer 105 and the metal layer ι 8 (see Fig. m) has good adhesion. At present, the surface roughening mode of the dielectric layer 103 is etched down from the flat surface by an isotropic chemical 20 etching. That is, the pits on the surface of the dielectric layer 103 (see Fig. 1B) are formed by biting off a portion of the dielectric layer using a potassium permanganate solution, so that the surface of the dielectric layer 103 is not noticeably undulating. However, the thinner the wiring of the package substrate, the smaller the nip area between the wiring and the dielectric layer, which tends to cause insufficient bite force between the two and even cause the line to peel off. Therefore, when the line of the 1312560 package substrate tends to be Fine Pitch, the surface of the electric layer roughened by chemical etching cannot provide sufficient biting force to avoid line peeling. With the development of the packaging technology, Fine Pitch has become an active development direction for the packaging substrate industry to increase the available wiring area. Therefore, how to increase the adhesion between layers and layers in the build-up structure of the package substrate is an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method for fabricating a package substrate, which includes a template and a substrate, wherein the surface of the template has a plurality of convex ridges, and the surface of the substrate has a plurality of Electrically connecting 塾, 、, two dielectric layers, and the dielectric layer covers the electrical connection pads; (8) the modulo 15 20 is printed on the dielectric layer to form a plurality of layers on the surface of the dielectric layer a groove, penetrating the electrode; 1 electrical layer; (C) removing the template from the dielectric layer; the dielectric layer having the surface of the groove to roughen the surface of the dielectric layer and the inner surface of the text And forming a plurality of dielectric layers in the dielectric layer, the gates are electrically connected, and (8) the dielectric layer and the intervening di-phosphorated metal, wherein the patterned metal layer comprises a circuit layer and a plurality of The conductive structure, the 1 layer has the surface of the grooves, 1 is electrically conductive and placed at 4, and the circuit layer is electrically connected to the dielectric layer open pad. Close to the electrical connection below the electrical layer 7 1312560
換句話說，本發明之製造方法係先以機械方式對該介 電層進行預粗化，也就是以模板壓印於介電層上，使 層表面產生垂直方向之凹陷。再以化學㈣方式對該介電 層進行表面粗化’使介電層表面以及溝紋的内表面被餘刻 形成粗糙面。藉此方法，可增加介電層與線路層之間咬^ 面積’而I溝紋的内表面會形成側向齡面，因： 大幅增加了介電層與線路層之間的附著力。此故，藉由本 發明之方法，即使採用細線距（Fine phch)之封裝基板，盆 線路依然具有良好之附著力。 ^ 而且，藉由本發明之方法，後續形成於介電層上之介 電層或防焊層’其與介電層之間的咬合面積也會增加。因 此’提高封裝基板之增層結構中層與層之間的附著力。 15 20 此封裝基板之製造方法之步驟⑼中，㈣該介電芦、 以及形成複數個介電層開口之先後次序不限定”交佳，曰 依序先於該介電層具有該等溝紋之表面形成該介電層開 :及該等電性連接墊；再編介電層具有該等溝 及「口之表面’使該介電層表面、該等溝紋之内表面 _等^==表面粗化。或者，依序先㈣該介電層具有 化·再’使該介1層表面及料敍之内表面粗 開口，以露出該等電性連接墊。 电層 粗化ί本：明之方法中’該介電層表面以模板屋印進行預 粗化時，該极缸主 ^ 深产 、 凸出部的數量、位置配置、形狀、 又 搜不限定，可視製程需要或介電層之材料特性 8 1312560 穿刺二唯= 層時’模板表面上凸*部不可 形狀較佳為半球狀、錐：二絕:性賴該模板之凸出部 :Γ狀凸㈣一，= = :::之 :只=大於介電層即可，較佳為鋼板、不鏞= 板^合金板、銅板、或銅合金板，更佳為鋼板。 形成之篝纹本毛明之方法中，該介電層表面以模板壓印 ==:、深度、及直徑與模板之凸―。 10 15 $曰表面溝紋之形狀較佳為 不規則狀之溝紋，更佳為錐狀溝紋。 柱狀或 行射t本：明之方法中’該介電層具有該等溝紋之表面進 m且化其表面時’其钱刻方式係為等向性钱刻。蝕 刻ί用之藥水不限定，可視製程需要或介電層之材料特性 而疋，較佳之藥水為過錢酸酸鉀溶液。另外，該藥水的濃 度、以及蝕刻時間亦不限定’可視介電層之材料特性、以 及預定之表面粗造度而定。钱刻完成後，該介電層溝紋之 内表面形貌不定，較佳係形成側向㈣的粗链面。 —另外，在本發明之方法中，該電性連接墊之材料不限 定，較佳為銅、或1呂’更佳為銅。該介電層之材料不限定， 較佳係選自 ABF(Ajinom〇to Build_up Film)、雙順丁 醯二酸 醯亞胺/二氮阱（BT，Bismaleimide triazine)、聯二苯環 丁二烯 (benz〇cyl〇butene ; BCB)、液晶聚合物（Liquid Polymer)、聚亞酸胺（p〇lyimide ; ρι)、聚乙烯醚 (P〇ly(Phenylene ether))、聚四氟乙烯（p〇ly _ra_ 20 1312560 、芳香尼龍（Aramide)'環氧樹脂以及玻璃 ^成之軸，更料娜(他。_ Build, Fi〗m)。 — τ 電層開口之形成方法不限 疋，較“以雷射鑽孔或曝光、顯影形成介電層開口。惟 當利用雷射鑽孔的技術時，復需進行_師_咖)作業 以移除因鑽孔所殘留於介電層開口内的膠潰。 - 在本發明之方法中，於該步驟（F)中該圖案化金屬層材 枓不限定，較佳為銅、錫、鎳、鉻、把、鈦、錫續或其合 金，更佳為銅。 10…在本發明之方法中，於該步驟（F)中該圖案化金屬層之 形成方法不限定，較佳係以下列步驟形成：首先於該介電 層及該介電層開口表面形成一晶種層；接著於該晶種層: 面形成一阻層，該阻層具有複數個阻層開口，且該阻層開 口對應至該介電層開口之位置；然後於該等阻層開口；： 15形成一金屬層；最後移除該阻層、以及被該阻層覆蓋之該 晶種層，即可形成一圖案化金屬層。 在上述圖案化金屬層之形成方法中，該晶種層主要係 作為後述進行電鍍製程所需之電流傳導路徑。其材料係選 自由銅、錫、鎳、鉻、鈦、銅/鉻合金以及錫/鉛合金中任一 20 種材料所組成之群組，較佳地係為使用銅材料，則以濺鍍、 蒸鑛及無電電艘之一者形成，較佳係以無電電鑛方式开^ 成。若該晶種層係以導電高分子作為晶種層，則以旋轉塗 佈（sPin coating )、喷墨印刷（ink-jet printing )' 網印（screen printing)或壓印（imprinting)等方式形成，其中該導電高 10 1312560 :子係選自由聚乙快、聚苯胺以及有機硫聚合物中任—種 封料所組成之群組。該阻層之妯祖 4m工…不限定，較佳地係使用 先性㈣子’例如：乾膜或液態光阻，更佳地係使用乾 ^另形成該等阻層開口之方式亦不限使用任何方法 佺地係使用曝光以及顯影之方式。 10 15 再者，本發明亦提供-種封裝基板，包括：一基板， 2面具有複數個電性連接墊；—介電層，係位於該基板 :電性連接墊之表面上’其中該介電層具有複數個介電 層開口以«該等電性連接墊、以及具有複數個不穿透★亥 二電層之溝紋’且該介電層表面及該等溝紋之内表面為粗 :二’以及I屬層’其包括有一線路層以及複數個導電 4,其中該線路層係、疊置㈣介電層具㈣㈣紋之表 面’該導電結構係穿過該介電„口以供該線路層電性連 接至該介電層下方之該等電性連接墊。 由於本發明之封裝基板之介電層表面具有溝紋且溝纹 的内表面被似彳形成粗糙面，因此介電層與線路層之間咬 口面積i曰加’而且溝紋的内表面會形成側向餘刻，進而提 昇介電層與線路層之間的咬合力。此故，本發明之封裝基 板，即使線路很細依然具有良好之附著力。 此外，本發明之封裝基板復包括一防焊層言史置於該介 電層上’ m讀層具有複數個開口以供設置複數個焊料 凸塊。此防焊層之材料不限定，較佳為綠漆或黑漆。則由 於介電層與防谭層之間的咬合面積增加，因此，介電層與 防知層之間的附著力增加。或者，本發明之封裝基板復包 20 1312560 括另一介電層設置於該介電層上，以形成多層之增層結 構，則由於介電層與介電層之間的咬合面積增加，因此， ;1電層與介電層之間的附著力增加。此故，藉由本發明之 封裴基板，可增加封裝基板之增層結構中層與層間的附著 5 力。 另外，在本發明之封裝基板中，該電性連接墊之材料 不限定，較佳為銅、或鋁，更佳為銅。該介電層之材料不 限定，較佳係選自 ABF(Ajin〇moto Build-up Film)、雙順丁 醯二酸醯亞胺/三氮阱（BT，Bismaleimide triazine)、聯二苯環 10 丁二烯（benZOCylobutene ; BCB)、液晶聚合物（Liquid Crystal Polymer)、聚亞酿胺（p〇lyimide ; ρι)、聚乙烯醚 (P〇Iy(phenylene ether))、聚四氟乙烯（p〇ly ㈣仏 fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組。更佳為ABF(Ajin〇m〇t〇 Build_up Fiim)。 15 在本發明之封裝基板中，該溝紋之形狀不限定，較佳 為半球狀、錐狀、柱狀、或不規則狀之溝紋。且該等溝紋 之内表面形貌不定，較佳為側向蝕刻之粗糙面。 在本發明之封裝基板中，該金屬層之材料不限定，較 佳為銅、錫、鎳、鉻、鈀、鈦、錫/錯或其合金。 ° 此外，在本發明之封裝基板中，復包括一晶種層設置 於該金屬層與該介電層、以及該金屬層與該電性連接塾之 間。該晶種層主要係作為後述進行電鑛製程所需之電流傳 導路徑。其材料係選自由銅、錫、鎳、絡、鈦、銅/鉻合金 以及錫/錯合金令任一種材料所組成之群組，較佳地係為使 12 10 15 20 1312560 用銅材料。該晶種層之材料以可 自由聚乙炔、聚苯胺以及…導電向分子，較佳係選 錢以及有機疏聚合物所组成之群組。In other words, the manufacturing method of the present invention first mechanically pre-roughs the dielectric layer, i.e., embosses the template onto the dielectric layer to cause vertical depressions in the surface of the layer. The dielectric layer is further roughened by chemical (four) means, so that the surface of the dielectric layer and the inner surface of the groove are left to form a rough surface. By this method, the area between the dielectric layer and the wiring layer can be increased, and the inner surface of the I groove can form a laterally aged surface because: the adhesion between the dielectric layer and the wiring layer is greatly increased. Therefore, with the method of the present invention, the pot circuit has good adhesion even with a fine pitch (Fine phch) package substrate. Moreover, by the method of the present invention, the nip area between the dielectric layer or the solder resist layer 'subsequently formed on the dielectric layer and the dielectric layer is also increased. Therefore, the adhesion between the layers in the build-up structure of the package substrate is improved. 15 (20) In the step (9) of the method for manufacturing the package substrate, (4) the dielectric reed and the order of forming the plurality of dielectric layer openings are not limited to "good", and the grooves are preceded by the dielectric layer. Forming the dielectric layer on the surface: and the electrical connection pads; the re-wiping dielectric layer has the grooves and the "surface of the mouth" such that the surface of the dielectric layer, the inner surface of the grooves, etc. ^== The surface is roughened. Or, in order to first (4) the dielectric layer has a chemical layer, and the inner surface of the dielectric layer and the inner surface of the dielectric layer are roughly opened to expose the electrical connection pads. In the method of the invention, when the surface of the dielectric layer is pre-roughened by the stencil printing, the core cylinder is deeply produced, the number of the protruding portions, the positional arrangement, the shape, and the search are not limited, and the visual process needs or the dielectric layer. Material characteristics 8 1312560 Puncture two 'the convex surface of the template surface is not hemispherical shape, cone: two absolutely: the convex part of the template: Γ convex (four) one, = = :: : It: than the dielectric layer, preferably steel plate, not 镛 = plate ^ alloy plate, copper plate, or copper alloy plate, In the method of forming the enamel pattern, the surface of the dielectric layer is embossed with a template ==:, depth, and diameter and the convexity of the template - 10 15 $ 曰 surface groove shape is preferably not Regular groove pattern, more preferably cone-shaped groove pattern. Column or row t: In the method of Ming, 'the dielectric layer has the surface of the groove into the m and the surface is turned on. It is an isotropic ink engraving. The syrup used for etching is not limited, depending on the process requirements or the material properties of the dielectric layer, the preferred syrup is a potassium sulphate solution. In addition, the concentration of the syrup and the etching time are also The material characteristics of the visible dielectric layer and the predetermined surface roughness are not limited. After the completion of the engraving, the inner surface of the dielectric layer groove is indefinite, preferably forming a lateral (four) thick chain surface. In addition, in the method of the present invention, the material of the electrical connection pad is not limited, and is preferably copper or 1 Å, more preferably copper. The material of the dielectric layer is not limited, and is preferably selected from ABF. (Ajinom〇to Build_up Film), Bisuccinimide bismuth imide/diazot trap (BT, Bismalei Mide triazine), benzidine cylbutbutene (BCB), liquid polymer (Liquid Polymer), polyaluminum (p〇lyimide; ρι), polyvinyl ether (P〇ly (Phenylene) Ether)), polytetrafluoroethylene (p〇ly _ra_ 20 1312560, aromatic nylon (Aramide) epoxy resin and glass into the axis, more Na (he. _ Build, Fi m). — τ electric layer The method of forming the opening is not limited, and the dielectric layer opening is formed by laser drilling or exposure and development. However, when the technology of laser drilling is utilized, the operation of the hole is required to remove the drill. The glue remaining in the opening of the dielectric layer is broken. - in the method of the present invention, the patterned metal layer is not limited in the step (F), preferably copper, tin, nickel, chromium, handle, titanium, tin or alloy thereof, more preferably copper. . In the method of the present invention, the method for forming the patterned metal layer in the step (F) is not limited, and is preferably formed by the following steps: first forming a surface on the dielectric layer and the opening surface of the dielectric layer. a seed layer; and then forming a resist layer on the surface of the seed layer, the resist layer has a plurality of resist layer openings, and the resist layer opening corresponds to a position of the opening of the dielectric layer; and then opening in the resist layer; : 15 forming a metal layer; finally removing the resist layer and the seed layer covered by the resist layer to form a patterned metal layer. In the above method of forming a patterned metal layer, the seed layer is mainly used as a current conduction path required for the electroplating process to be described later. The material is selected from the group consisting of any of 20 materials of copper, tin, nickel, chromium, titanium, copper/chromium alloy and tin/lead alloy, preferably by using copper material, by sputtering, One of the steamed or non-electrical power banks is formed, preferably in the form of electroless ore. If the seed layer is made of a conductive polymer as a seed layer, it is formed by spin coating, ink-jet printing, screen printing, or imprinting. Wherein the conductive height is 10 1312560: the daughter is selected from the group consisting of polyacetamide, polyaniline, and organic sulfur polymer. The structure of the resist layer is not limited, and it is preferable to use a precursor (four) sub-for example: a dry film or a liquid photoresist, and more preferably, the method of forming the resist layer opening is not limited. Exposure and development are used in any way. Further, the present invention also provides a package substrate comprising: a substrate having a plurality of electrical connection pads on two sides; a dielectric layer on the surface of the substrate: the electrical connection pad The electrical layer has a plurality of dielectric layer openings to "the electrically connected pads, and a plurality of grooves that do not penetrate the second layer" and the surface of the dielectric layer and the inner surface of the grooves are thick The second 'and the I-type layer' includes a circuit layer and a plurality of conductive layers 4, wherein the circuit layer, the stacked (four) dielectric layer (4) (four) grain surface, the conductive structure passes through the dielectric layer The circuit layer is electrically connected to the electrical connection pads under the dielectric layer. Since the surface of the dielectric layer of the package substrate of the present invention has grooves and the inner surface of the groove is roughened by the like, the dielectric is The bite area between the layer and the circuit layer is increased by 'and the inner surface of the groove will form a lateral residue, thereby increasing the bite force between the dielectric layer and the circuit layer. Thus, the package substrate of the present invention, even The line is very fine and still has good adhesion. Further, the present invention The package substrate further includes a solder mask layer on the dielectric layer. The m read layer has a plurality of openings for providing a plurality of solder bumps. The material of the solder resist layer is not limited, preferably green paint or black. Paint. Since the occlusal area between the dielectric layer and the anti-tank layer increases, the adhesion between the dielectric layer and the anti-knowledge layer increases. Alternatively, the package substrate of the present invention 20 1312560 includes another dielectric The layer is disposed on the dielectric layer to form a multi-layered buildup structure, and since the occlusal area between the dielectric layer and the dielectric layer is increased, the adhesion between the electric layer and the dielectric layer is increased. Therefore, the sealing substrate of the present invention can increase the adhesion between the layers in the layered structure of the package substrate. Further, in the package substrate of the present invention, the material of the electrical connection pad is not limited, and is preferably Copper, or aluminum, more preferably copper. The material of the dielectric layer is not limited, and is preferably selected from the group consisting of ABF (Ajin〇moto Build-up Film), bis-cis-succinimide bismuth imide/triazo trap (BT). , Bismaleimide triazine), biphenyl ring 10 butadiene (benZOCylobutene; BCB), Liquid Crystal Polymer, polystyrene (p〇lyimide; ρι), polyvinyl ether (P〇Iy (phenylene ether), polytetrafluoroethylene (p〇ly (tetra) fluoroethylene)), aromatic nylon A group of (Aramide), an epoxy resin, and a glass fiber is more preferably ABF (Ajin〇m〇t〇Build_up Fiim). 15 In the package substrate of the present invention, the shape of the groove is not limited, and is preferably. It is a hemispherical, tapered, columnar, or irregular groove, and the inner surface of the grooves is indefinite, preferably a laterally etched rough surface. In the package substrate of the present invention, the material of the metal layer is not limited, and it is preferably copper, tin, nickel, chromium, palladium, titanium, tin/error or an alloy thereof. Further, in the package substrate of the present invention, a seed layer is further provided between the metal layer and the dielectric layer, and between the metal layer and the electrical connection port. This seed layer is mainly used as a current conducting path required for conducting an electric ore process as will be described later. The material is selected from the group consisting of copper, tin, nickel, cobalt, titanium, copper/chromium alloys, and tin/stagger alloys, preferably made of copper material for 12 10 15 20 1312560. The material of the seed layer is a group of freely acetylene, polyaniline, and ... conductive molecules, preferably selected from the group and organic polymer.
【實施方式J 本發明之實施例中該等圖 等圖示僅顯示與本發明有關之一 間化之示思圖。惟該 實籽實施拄 疋件，其所顯示支元件非為 二實際實施時之元件數目、形狀等比 例為：:擇性之設計’且其元件佈局型態可能更複雜。 制心：：圖^21 ’為本發明-較佳實施例之封裝基板 衣le-方法剖面不音圖。舌生 . 心圖首先，如圖2A所示，提供_封裝基 ，^至> 一表面具有複數個電性連接墊2犯。在本實 施例中’該電性連接墊202係選擇性地連接至導通孔22〇，、 以電性連接封農基板2()1下表面之電性連接塾2〇2。此導通 孔220連通該封裝基板加之上、下表面，且該導通孔22〇内 壁形成有導電層22：[，並以樹脂222填滿該導通孔22〇。在本 實施例中，該電性連接墊2〇2、以及該導通孔22〇内壁之導 電層221導電層的材料均為銅。[Embodiment J] The drawings and the like in the embodiments of the present invention show only a schematic diagram relating to the present invention. However, the actual seed is implemented as an element, and the number of components and shapes in the actual implementation is not: the design of the alternative and the component layout may be more complicated. Threading: Fig. 21 is a cross-sectional view of the package substrate of the preferred embodiment of the invention. Tongue. Heart diagram First, as shown in Fig. 2A, a package base is provided, and a surface has a plurality of electrical connection pads 2. In the present embodiment, the electrical connection pad 202 is selectively connected to the via hole 22〇 to electrically connect the electrical connection 塾2〇2 of the lower surface of the agricultural substrate 2()1. The via hole 220 communicates with the upper and lower surfaces of the package substrate, and the conductive layer 22 is formed on the inner wall of the via hole 22: [, and the via hole 22 is filled with the resin 222. In this embodiment, the electrical connection pads 2〇2 and the conductive layer of the conductive layer 221 of the inner wall of the via hole 22 are made of copper.
在本實施例中’由於其餘電性連接墊2〇2的結構皆與A 區域之結構大致相同’故後續僅顯示A區域之電性連接墊 202作為代表說明。 接著’請參閱圖2B，其係於圖2A中的A區域放大來看。 如圖2B示’於封裝基板2〇1具有電性連接墊2〇2之表面形成 一介電層203以覆蓋該封裝基板2(Π、以及該電性連接墊202 上。§亥介電層之材料可選自ABF(Ajinomoto Build-up 13 1312560In the present embodiment, since the structures of the remaining electrical connection pads 2〇2 are substantially the same as those of the A region, only the electrical connection pads 202 of the A region are shown as a representative. Next, please refer to Fig. 2B, which is enlarged in the area A of Fig. 2A. As shown in FIG. 2B, a dielectric layer 203 is formed on the surface of the package substrate 2〇1 having the electrical connection pads 2〇2 to cover the package substrate 2 (Π, and the electrical connection pad 202. The material can be selected from ABF (Ajinomoto Build-up 13 1312560
Film)、雙順丁醯二酸醯亞胺/三氮阱（BT, Bismaleimide triazine)、聯一苯環 丁二稀（benzocylobutene, BCB)、液晶聚 合物（Liquid Crystal Polymer)、聚亞醯胺（Polyimide, PI)、聚 乙烯醚（Poly(phenylene ether))、聚四氟乙烯（Poly (tetra-5 fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組。在本實施例中，該介電層203之材料為 ABF(Ajinomoto Build-up Film)。 然後’先以機械方式對該介電層2〇3進行預粗化。如圖 2C所示’將一表面具有複數個凸出部205之模板204壓印於 10該介電層上，使該介電層2〇3表面2〇33產生垂直方向之 凹fe唯壓印時，需避免該模板204之凸出部205穿刺該介 電層203，以免暴露出或者甚至破壞該封裝基板2〇ι上的電 陡連接墊202或其他導電結構（圖中未示）。該模板删之凸出Film), bis(B, Bismaleimide triazine), benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal Polymer), polyimide ( Polyimide, PI), Poly(phenylene ether), Poly(tetra-5 fluoroethylene), Aramide, Epoxy, and Glass Fiber. In this embodiment, the material of the dielectric layer 203 is ABF (Ajinomoto Build-up Film). The dielectric layer 2〇3 is then pre-roughened mechanically. As shown in FIG. 2C, a template 204 having a plurality of protrusions 205 on one surface is imprinted on the dielectric layer, so that the surface 2〇33 of the dielectric layer 2〇3 is formed in a vertical direction. The embossing portion 205 of the template 204 is prevented from puncturing the dielectric layer 203 to avoid exposing or even destroying the electrical steep connection pads 202 or other conductive structures (not shown) on the package substrate 2〇. The template is deleted
該模板204之材料只要硬度大於介電 、或不銹鋼鋼板。在本實施例中，該 一一 1工刊打丨紙艰成之凹陷大小，但不可穿透 該介電層203。另外，岔裙此— 一The material of the template 204 is as long as the hardness is greater than that of dielectric or stainless steel. In the present embodiment, the one-to-one publication punch paper is difficult to penetrate, but the dielectric layer 203 cannot be penetrated. In addition, this skirt - this one
棋敬之材料為鋼板。The material of Chess is steel.
14 !312560 ' 隨後，將該模板204自該介電層203移開。如圖2〇所 示，該模板204移開後，該介電層2〇3表面2〇3a形成複數個 不穿透該介電層203之溝紋206。此溝紋2〇6之形狀、深度、 及直徑大致與模板204之凸出部205相同。在本實施例中， 5 该介電層203表面形成錐狀之溝紋200。 接著，再以化學蝕刻方式對該介電層2〇3進行表面粗 化。由於蝕刻用之藥水（圖中未示）會進入溝紋2〇6中往不同 φ 方向蝕刻（一般為等向性蝕刻）。因此，介電層203之溝紋206 内表面會形成側向蝕刻的粗糙面，其結構如圖2E所示。在 1〇本貫施例中，該藥水之成分可視製程需要或介電層203之材 料特性而定。本實施例採用之蝕刻藥水為過錳酸酸鉀溶 液另外，該藥水的濃度、以及蝕刻時間也可視介電層2〇3 之材料特性、以及預定之表面粗糙度而定。 元成上述步驟之後，如圖2F所示，於介電層上形成 15複數個穿透介電層203之介電層開口 207。此介電層開口 2〇7 之位置需對應於電性連接墊2〇2之位置，以暴露出介電層 響 2G3下面的電性連接塾202。在本實施例中，該介電層開口 204係以曝光、顯影或雷射方式形成。 則述圖2E及圖2F所述餘刻該介電層203具有該等溝 2〇 紋206之表面2〇3、以及形成開口 2〇7之步驟，亦可視製程 需要，先如圖2E’，於該介電層203具有該等溝故2〇6之表 面203&形成開口 2〇7，再如圖2F，，蝕刻該介電層2们具 有肩等溝紋206及開口 207之表面203a，使該介電層表面 2〇3a、該等溝紋2〇6之内表面、以及開口 2〇7之内表面粗 15 1312560 化。惟此後續製程係與本實施例相似，故在此不再為文贅 述此實施態樣’但並非以此限制本發明。 接著，於該介電層203、以及介電層開口 2〇7上形成— 晶種層208。在本實施例中，該晶種層2〇8為銅，其係以無 5電電鏡之方式形成。再於該晶種層2G8上形成-具有複數個 阻層開口 210之阻層209 ’且此阻層開口 21〇之位置對應於介 電層開口 207。在本實施例中，該阻層2〇9為液態光阻，其 開口 210係以曝光、顯影方式形成。隨之，以電鑛方式於^ 層開口210内形成一金屬層211，可得到如圖2(}結構。隨後， 1〇再移除阻層209、以及被阻層2〇9覆蓋之晶種層2〇8，即可得 到如圖2H所示之結構。該金屬層211之材料可為銅、锡、錦二 鉻、把、鈦、錫/錯或其合金。在本實施例中，該金屬層叫 之材料為銅。 15 20 及金屬層211包括有—線路層212以及複數個導電結構 213 ’邊線路層212係疊置於該介電層加具有該等溝紋綱 之表面，而該導電結構213係穿過該介電層開口2G7以供該 線路層2U電性連接至該介電層203下方之電性連接塾2〇 :於本實施例之介電層加先以機械方式進行預粗 ’再以化學_方式進行表面粗化，使 二溝紋2。6的内表面形成粗链面，而於面： = =G3與線路層212之間咬合面積，而™^ …成側向姓刻的粗糙面，更大幅增加了介電層2〇3與 路層212之間的附著力。此故，藉由本發明之方法，即使 16 1312560 採用細線距（Fine Pitch)之封裝基板，其線路依然具有良好 之附著力’而可避免線路剝離。 因此，本實施例可增加介電層2〇3表面粗糙化的效果， 進而增加介電層203和線路層211之間的附著力。 然後，如圖21所示，將本實施例圖211所示之封裝美 加之線路層212視為電性連接墊，依所需要之層數錢上 述步驟數次，以製作多層之結構。隨之，於最頂端之介带 層·上塗覆綠漆作為防焊層214。再於防焊層214形成： 口以顯露防焊層214下面之部分線路層2咖作為電性連接 塾2咖°最後’將複數個焊料凸塊215設置於防焊層214的 與電性連接塾202af性導接，即完成本實施例之封 15 20 如圖2H所示，本實施例介電層與介電層之間、以及介 層與防焊層之間的咬合面積也都增加。因此，藉由 :之=製造之封裝基板’可增加封袭基板之增層結 路層之間、介電層與介電層之間、以及 構中層與層間的附著力。 進而^封裝基板增層結 主張二實_僅係為了方便說明而舉例而已，本發明所 於上述實施例。甲…】軏圍所述為準’而非僅限 【圖式簡單說明】 之剖面示意圖 圖1A至1F係習知之封裝基板製造方法 17 1312560 圖2A至21係本發明—較佳杂a 面示意圖。 土只施例之封裝基板製造方法之剖 【主要元件符號說明】 封裝基板101,201 介電層 103, 203, 203b 晶種層105, 208 阻層開口 107, 210 導通孔109, 220 凸出部205 線路層212 防焊層214 導電層221 介電層表面203a 電性連接墊1〇2, 202, 202a 介電層開口 104, 207 阻層 106, 209 金屬層108,211 模板204 溝紋206 導電結構213 焊料凸塊21 5 樹脂222 1814 !312560 ' Subsequently, the template 204 is removed from the dielectric layer 203. As shown in FIG. 2A, after the template 204 is removed, the surface 2〇3a of the dielectric layer 2〇3 forms a plurality of grooves 206 that do not penetrate the dielectric layer 203. The shape, depth, and diameter of the groove 2〇6 are substantially the same as the projections 205 of the template 204. In this embodiment, 5 the surface of the dielectric layer 203 forms a tapered groove 200. Then, the dielectric layer 2〇3 is subjected to surface roughening by chemical etching. Since the etchant (not shown) will enter the groove 2〇6 and etch in different φ directions (generally isotropic etching). Therefore, the inner surface of the groove 206 of the dielectric layer 203 forms a laterally etched rough surface, and its structure is as shown in FIG. 2E. In the first embodiment, the composition of the syrup may depend on the process requirements or the material properties of the dielectric layer 203. The etching syrup used in this embodiment is a potassium permanganate solution. The concentration of the syrup and the etching time may also depend on the material properties of the dielectric layer 2〇3 and the predetermined surface roughness. After the above steps, as shown in FIG. 2F, a plurality of dielectric layer openings 207 penetrating the dielectric layer 203 are formed on the dielectric layer. The position of the dielectric layer opening 2〇7 needs to correspond to the position of the electrical connection pad 2〇2 to expose the electrical connection port 202 under the dielectric layer 2G3. In the present embodiment, the dielectric layer opening 204 is formed by exposure, development or laser. 2E and FIG. 2F, the dielectric layer 203 has the surface 2〇3 of the trenches 2 and 206, and the steps of forming the openings 2〇7, which can also be processed according to the process, first as shown in FIG. 2E′. The dielectric layer 203 has the surface 203 of the trenches 2 〇 6 and the openings 2 〇 7 are formed, and as shown in FIG. 2F , the dielectric layers 2 are etched to have the shoulders 206 and the surface 203 a of the openings 207 . The surface of the dielectric layer 2〇3a, the inner surface of the grooves 2〇6, and the inner surface of the opening 2〇7 are made rough. However, the subsequent processes are similar to the present embodiment, and thus the present embodiment is not described herein, but the present invention is not limited thereto. Next, a seed layer 208 is formed on the dielectric layer 203 and the dielectric layer opening 2〇7. In the present embodiment, the seed layer 2〇8 is copper, which is formed in the form of a five-electron microscope. Further, a resist layer 209' having a plurality of resist opening 210 is formed on the seed layer 2G8 and the position of the resist opening 21 is corresponding to the dielectric layer opening 207. In the present embodiment, the resist layer 2〇9 is a liquid photoresist, and the opening 210 is formed by exposure and development. Subsequently, a metal layer 211 is formed in the opening 210 of the layer by electro-minening, and a structure as shown in FIG. 2 can be obtained. Subsequently, the resist layer 209 is removed and the seed layer covered by the resist layer 2〇9 is removed. The layer 2 〇 8 can obtain the structure as shown in Fig. 2H. The material of the metal layer 211 can be copper, tin, chrome, handle, titanium, tin/error or its alloy. In this embodiment, The metal layer is called copper. The 15 20 and the metal layer 211 include a circuit layer 212 and a plurality of conductive structures 213 'the circuit layer 212 are stacked on the dielectric layer and have the surface of the groove pattern. The conductive structure 213 is passed through the dielectric layer opening 2G7 for electrically connecting the circuit layer 2U to the electrical connection layer 203 below the dielectric layer 203: the dielectric layer in the embodiment is mechanically added first. Performing pre-roughing and then roughening the surface by chemical method, so that the inner surface of the two groove pattern 2.6 forms a thick chain surface, and the surface area: ==G3 and the biting area between the circuit layers 212, and TM^... The rough surface of the lateral surname further increases the adhesion between the dielectric layer 2〇3 and the road layer 212. Thus, by the method of the present invention, The 16 1312560 adopts a fine pitch (Fine Pitch) package substrate, and the circuit still has good adhesion' to avoid stripping. Therefore, this embodiment can increase the surface roughening effect of the dielectric layer 2〇3, thereby increasing Adhesion between the dielectric layer 203 and the circuit layer 211. Then, as shown in FIG. 21, the circuit layer 212 of the package of the US and Canada shown in FIG. 211 of the present embodiment is regarded as an electrical connection pad, according to the required number of layers. The above steps are performed several times to make a multi-layered structure. Subsequently, green paint is applied as a solder resist layer 214 on the topmost interlayer layer. Further, the solder resist layer 214 is formed to: expose the underlying solder resist layer 214 A part of the circuit layer 2 is electrically connected to the electrical connection 最后2, and finally a plurality of solder bumps 215 are disposed on the solder resist layer 214 to be electrically connected to the electrical connection port 202, that is, the sealing of the embodiment 15 20 is completed. 2H, the occlusal area between the dielectric layer and the dielectric layer and between the dielectric layer and the solder resist layer is also increased in this embodiment. Therefore, the package substrate can be increased by: Between the buildup layers, between the dielectric layer and the dielectric layer And the adhesion between the middle layer and the layer. Further, the package substrate is added to the substrate. The present invention is exemplified for convenience of description. The present invention is based on the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are diagrams showing a conventional method for manufacturing a package substrate. FIG. 2A to FIG. 21 are a schematic view of a preferred embodiment of the present invention. Main component symbol description] package substrate 101, 201 dielectric layer 103, 203, 203b seed layer 105, 208 barrier opening 107, 210 via 109, 220 protrusion 205 circuit layer 212 solder mask 214 conductive layer 221 dielectric layer Surface 203a Electrical connection pads 1〇2, 202, 202a Dielectric layer opening 104, 207 Resistive layer 106, 209 Metal layer 108, 211 Template 204 Groove 206 Conductive structure 213 Solder bump 21 5 Resin 222 18
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW95138758A TWI312560B (en) | 2006-10-20 | 2006-10-20 | Package substrate and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW95138758A TWI312560B (en) | 2006-10-20 | 2006-10-20 | Package substrate and method thereof |
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| TW200820392A TW200820392A (en) | 2008-05-01 |
| TWI312560B true TWI312560B (en) | 2009-07-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9552995B2 (en) * | 2014-11-26 | 2017-01-24 | Intel Corporation | Electrical interconnect for an electronic package |
| TWI628062B (en) * | 2016-03-17 | 2018-07-01 | 欣興電子股份有限公司 | Method for manufacturing circuit board and piezochromic stamp |
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