1303958 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種嵌埋半導體晶片之電路板結構 及其製法，更詳而言之，係有關於一種電路板之開口中具 有承托部用以撐托半導體晶片之結構及其製法。 【先前技術】1303958 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure for embedding a semiconductor wafer and a method of fabricating the same, and more particularly to a support board having an opening in a circuit board The structure for supporting the semiconductor wafer and the method of manufacturing the same. [Prior Art]
隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其主要 ⑩係在一封裝基板(package substrate)或導線架上先裝置半 導體晶片’再將半導體晶片電性連接在該封裝基板或導線 架上，接著以膠體進行封裝。其中球栅陣列式（Ball grid array，BGA)為一種先進的半導體封裝技術，其特點在於採 用一封裝基板來安置半導體晶片，並利用自動對位 (Self-alignment)技術以於該封裝基板背面植置多數個成柵 狀陣列排列之錫球（Solder ball)，使相同單位面積之半導體 I晶片承載件上可以容納更多輸入/輸出連接端（I/O connection)以符合高度集積化（Integration)之半導體晶片 所需，以藉由此些錫球將整個封裝單元銲結並電性連接至 外部裝置。 惟傳統半導體封裝結構是將半導體晶片黏貼於基板 頂面，進行打線接合（wire bonding)或覆晶接合（Flip chip) 封裝，再於基板之背面植以錫球以進行電性連接，如此， 雖可達到高腳數的目的，但是在更高頻使用時或高速操作 時，其將因導線連接路徑過長而產生電氣特性之效能無法 6 19143 1303958 =昇:而有所限制，另外，因傳統时需要多次的連接介 面，相對地增加生產製造成本。 鑑此，4 了能有效地提昇電性品質而符合下世代產口口 之應用，業界紛紛研究採用將晶片埋入承载板内，作直接口 的電性連接，來縮短電性傳導路徑，並減少訊號損失、訊 號失真及提昇在高速操作之能力。 、 請參閲第1Α至1Ε圖’係顯示習知嵌埋半導體之 電路板結構之製法流程圖。 圖所示，首先提供一該核心板1〇係為絕緣板 或凡成刖&線路製程之單層或多層電路板，該核心板⑺ 具有第-表面iOa及第二表面通且分別具有線路層 lla，llb之’並利用例如銳刀（R〇uter)等切割工 心板ίο中形成至少一貫穿之開口 10〇。 如第1B圖所示，於該核心板1〇之第二表面〗训的線 路層m形成有-黏著性較佳之介電層13用以固定晶片， 例如PP (prepreg，預浸材），並將至少一半導體晶片a 置於该核心板10之開口 100中，該半導體晶片U具有一 作用面120及相對於該作用面之非作用面121，且該作用 面120上形成有多數電極墊122[)使該半導體晶片^之非 作用面121接置於該介電層13上。 如第1c圖所示，於該核心板10之第-表面1〇a的線 路層11a及半導體晶片12之作用面12〇形成—係如離型膜 之保護層14。 如第1D圖所示，於該核心板10上進行壓合製程，使 19143 7 1303958 該介電層13 > ^ u 之材料填充於該半導體 之間的間隙中，M 、 片12與核心板10 jτ ’稭以將該半導髀曰H〗〇门 10之開口 1〇〇中，、固定於該核心板 中亚移除該保護層14，以妾丨士 板10及該半導雕 利後績於該核心 干¥體晶片12上進行後續制妒y 製程。 衣釦’例如線路增層 士第1E圖所示，並於該核 +導體…之作用面12〇形成另一介; 如弟1F圖所示，於該介電 。 線路增層結構16以 ，表面上分別形成一 體晶片之電路板，、/ 〃夕θ線路且嵌埋有至少一半導 电峪板，亚以一係如 7 貫穿該線路增層結構」 7通孔之導電結構18 導通。而該線路播線路增層結構16得以電性 介電… 之導電結㈣，且心:結==介電層 晶片12之電極墊122，並於該線路^接至終導體 有電性連接墊164,又於兮岭 9 a…構16表面形成 於。亥邊路增声社播〗^ 如防焊層之絕緣保護層17， 义面形成一係 數個開孔⑺，俾以顯編s亥絕緣保護層17中具有複 164。 1路線路增層結構16之電性連接墊 依上述製程所製成之嵌埋半 雖可縮短電性傳導路徑，f 1日日 私路板結構 升在兩頻運作之能力以克服 儿失”及挺 Φ ^ 白 平導體晶片接置於雷政杯 表面之種種缺失。然，習知制 电路扳 的半導體晶片12之厚度僅 岡1ϋυ ψ 子戾僅約為5〇 19143 8 1303958 板ι〇與介電層13不易密合，未熱壓前即留有約25〇_ 至500 /zm之空隙，因而在後續之壓合製程中介電層丨^之 材料流入該開口 1〇〇時，該半導體晶片η被模流沖曰擊而產 生移位，甚至流入前述空隙中，故無法將半導體晶片Η 定位在設定的位置上。 再者，習知製程採用銑刀於核心板1〇中形 之 :二—般銳刀之尺寸精度約為乃㈣’而雷射切割 Μ精度為1()至25/zm’通常為避免半導體晶片於製程中 移動，其開口之尺寸大都約略等於該半導體晶片之尺寸， ^用銑刀形成之開口摘相較於雷射切割 較難精確配合置於開口_中之半㈣= 使+導體晶片12較易於製程中被模流沖擊而移動。 衣=困難。口此、，如何有效將半導體晶片置於核心板之 卜汗口，以避免料導體晶片被模流沖擊導致移 ^響後續線路增錄程，已成為業者急 題進而 【發明内容】 果74。 鑑於上述習知技術之種種亚 於提供-種嵌埋半導體晶片之電路板、 將半導體晶片有效固定於電路板之開口中。 稭以 本表月之X目的在於提供一種嵌埋半導體 芦路板結構及其製法，藉以降低於該電路 層製程之困難度。 适仃線路增 19143 9 1303958 片之他目的，本發明揭露-種嵌埋半導p 片之电路板結構之製法， 牛*版曰曰 電路板具有-第-表面及相對之第括^供—電路板，該 表面分別且有定.、弟—表面，該第一及第二 層具有-承托部；以雷射切且… 該承乾部的位置形成至少-；路板上相對應於 从蕗出該第二線路層之承 表面之開 置於該電路板之開口令，並㈣=少一半導體晶片 口中之承托部上，且該半導體^ ^4靠在電路板開 面，該作用面上具有複數 曰.二有一作用面與非作用 及半導體晶>{之作用面:於该電路板之第一表面 表面及半導體曰 保護層’·於該電路板之第二 卞♦版日日片之非作用面形成一人 該保護層；以及於 罘"电層，並移除 田石/ …X包路板之弟一表面及半導妒曰片夕从 用面形成一第二介電層，且該第m 曰片之作 開口中、，以將半導體晶片固定===入該電路板之 透過上述製法所形成之本發 電路板結構係包括：瓜埋丰^晶片之 板，且該第一及第二：二表面及相對之第二表面之電路 層，且該第二線路料有^具^第―線路層及第二線路 該承托部位置具有至;一貫; 上，該半在該電路板之開口中的承托部 卜且士、/ 有一作用面與非作用面，且該作甩面 /、複數電極墊；第一介電層，係形成於該電路板之第 19143 10 1303958 二表面及該半導體晶η夕 形士 非作用面；以及第二介電層，儀 ‘第：：：：板之第一表面及該半導體晶片之作用面，且 固^-介電層係壓人該電路板之開 固定於該開口中。 71了卞命耻日日月 本發明亦提供另一嵌埋丰莫雕曰 製法’主要係包括：提#_::：：日彳之電路板結構之 面之電路板，該第—及第一一表面及相對之第： 第二線路厚，… 分別具有一第-線路層’ 部；以雷^切割二具有至少一具開孔之承托 至少一貫穿第-表面及第對應該承托部位置形> 至：ΐ=使該開口與該承耗部之開孔相連通… 心二::脰晶片置於該電路板之開口中 導: ==_板之開口中的承托部上 吏導= 具有-作用面與非作用面 體曰曰j 墊；於該電路板U面具有複數電極 >保護層；於該電路板之第面=晶片之作甩面形成-形成-第-介電/ ::半導體晶片之非作用茂 層引入電路起該承托部之開孔將該第-介f 層引入電路板之開σ卜力m 之開口中，並移除該保護層;以 及半導體晶片之作用面形成—第二介電亥;〜 片之所形成之本發明之嵌埋半導P 路板結構係包括··具第-表面及相對之第 琶路板’且該第—及第 弟-表面之 線路層，且該第n弟—線路層及第二 弟-、、泉路層具有至少一具開孔 19143 11 1303958 ^路板中對應該承托部位置具有該第—及第二 ^之開口以露出該承托部，且該開口係與該承托部之開 札相連通；至少一半導齅曰 R &令月足日日片係置於該電路板之開口中， μ半導體晶片係靠在該電路》 , 主 "毛路板之開口中的承托部上，該 複數電極墊;第一介電声，=面，作用面上具有 η ^ + 、、· 曰係形成於該電路板之第二表面 及该半導體晶片之非作用面， μ 托部之開孔引入該電路板之弟一，*電層係藉由該承 定於電路柘jΜ ^板之開口中，以將該半導體晶片固 ^ . 弟—，丨黾層，係形成於該電路 板之弟-表面及該半導體晶片之作用面。 =知技術，本發明之嵌埋半導體路 开其製法’主要係於電路板第二表面之第 ： ^成可供後續揍置丰導體曰 曰中 (10至25xzm#古夕+日日 承托部，並科用成型精度 —^ 雷射㈣方式於該輕板 貝牙该電路板第-及第二表 成至夕 4該承托部，之後復可於該，路板==之广露 形成第一介電層及第二弟：及弟-表面分別 電路板之開口中，„戈，由；S吏§亥乐二介電層壓入該 弓I入节次猎由该承托部之開孔將該第—介電声 中:以將該半導體晶片固定於該開口^ h 於以雷射切割形成之開口較易金半導俨曰片/ 確配合，且該承托部對該半導體.片尺寸精 而在後續第—介電層或第介 入、；#作用’因 致半導體晶片於該開”發二 開口，不會導 二介電声將兮主遒鹏 夕 卑可藉由该第一或第 电層將料導體晶片固定於該電路板之開 19143 12 1303958 外，由於該半導體晶片有效固定於該電路板之開 ==續於該電路板及該半導體^上進行線路增層= 【實施方式】 以下係藉由特定的具體實施例說明本 :，熟悉此技藝之人士可由本說明書所 二方： 瞭解本發明之其他優盥 内奋t易地 他杈2興功效。本發明亦可藉 實施例加㈣行或助，本說明書中項^ =於不㈣轉應用，在不轉本發明之精進 種修飾與變更。 進仃各 々如弟2A至2F圖係顯示本發明之嵌 路板結構之製法第一實施例之剖面。3 該等圖式均為簡化之干音円 。回思、的是， 封壯币 之不思圖’僅以示意方式說明本發明之 件，1所料厂a ,Γ4式頒示與本發财關之元 /、所,4不m牛非為實際實施時樣 時之元件數目、形狀及尺寸〜貝除貝轭 1 -从从 尺寸比例為—種選擇性之設計，且 〜70件佈局型態可能更形複雜。 如第2A圖所示，首先提供— 係具有—第-表⑽及相對之第路心路板2 二表面2以分別1右1一^卑—表面2b，該第一及第 ^ ^ '、 、、泉路層及第二線路層21，且 吕亥昂二線路層中具有至 ^ 1 ^ σΡ 210。接著利用雷射切 八7、及迅路板2中對應該承扛 貫穿該第—及第1面2…托。ρ 210位置形成至少-210。私士 — / 一 之開口 22以露出該承托部 、貫施例中，該電路板2係為完成前段線路製程之 19143 13 1303958 雙層線路板或多層線路板。本實施例係利用切割精度高之 雷射切割方式於該電路板中形成尺寸較精確之開口 22,以 使该開口之尺寸與後續接置於其中之半導體元件在之尺寸 相匹配，且形成承托部210，以供支撐半導體晶片，俾可 降低後續製程中該半導體晶片發生位置移動之機率。 如第2B圖所示，將至少一半導體晶片23置於該電路 板之開口 22中，且使該半導體晶片23靠在該開口 22中之 承托部210上，藉由該承托部21〇以支撐該半導體晶片 • 23。而該半導體晶片23係具有一作用面23()及與該作用面 相對之非作用面231，且該作用面230上形成複數電極墊 232。該半導體晶片23係可為主動式或被動式晶片，例如 選自電容矽晶片，記憶體晶片，ASIC ( AppHcati〇n Specific Integrated Circuit)晶片，或 Cpu 晶片等。 如第2C圖所示，於該電路板2之第一表面&、第一 線路層20及該半導體晶片23之作用面230形成一係如離 鲁型膜之保護層24,以避免外界環境之污染或製程中的外力 破壞半導體晶片23之作用面230。 如第2D圖所示，於該電路板2之第二表面2b、第二 線路層21及該半導體晶片23之非作用面形成第一介電層 25，並進行壓合製程，其中，該第一介電層25係為 ABF(Ajinomoto Build-up Film )- BCB(Benzocyclo_buthene)、LCP(Liquid Crystal Polymer)、 PI(Poly_imide)、PPE(Poly(phenylene ether))、 PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、 14 19143 1303958 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光或 非感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維之預浸 材（Prepreg，PP)等材質所構成；較佳地，該第一介電層係由 黏著性較佳之預浸材製成用以固定晶片。 如第2E圖所示，移除該保護層24，並於該電路板2 之第一表面2a、第一線路層20及該半導體晶片23之作用 面230形成一第二介電層26。此外，該電路板2之第一表 面2a、第一線路層20及該半導體晶片23之作用面230亦 _可不形成該保護層24,而直接形成該第二介電層26,且使 該第二介電層26壓入該電路板2之開口 22中，以將該半 導體晶片23固定於該開口 22中；其中，該第二介電層26 中形成複數相對於該半導體晶片23之電極墊232的開孔 261，以露出該半導體晶片23的電極墊232。該第二介電 層 26 係可例如為 ABF(Ajinomoto Build_up Film )、 BCB(Benzocyclo-butliene)、LCP(Liquid Crystal Polymer)、 • Pl(Poly-imide)、PPE(Poly(phenylene ether))、 PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光或 非感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維之預浸 材（Prepreg，PP)等材質所構成，較佳的，該第二介電層係由 細線路增層效果較佳的ABF製成。 因此，本發明之製法之第一實施例中，主要係利用切 割精度高之雷射切割方式於該電路板形成尺寸較精確之貫 穿開口，以降低後續接置於其中之半導體晶片被壓合介電 15 19143 13 03958 層之模流沖擊而位置移動之機率士… 第二線路層的承托部支撐該半導雕曰π Γ藉由该開口中之 程中由壓入該電路板開口‘ ：：晶片’進而可在履續製 效固定於該開口中。 —；ι電層將該半導體晶片有 如弟2F圖所示，之後，復可 一 '線路層20’以及第二介 、二：-力琶層25與! 成一線路增層結構27,並有一弟一線路層21表面开 2 8貫穿該線路料結構2 7 =f料通孔之導電結構 21，使該第一線路層2〇、第二4路層20及第二線路層 27得以電性導通。而 ：：路層21及線路增層結構 270、疊置於該介電層上W自結構27係包括介電層 層中之導電結構27/，且^ί路層271，以及形成於該介電 該半導體_之购^!：==接至 表面形成有電性連接墊273。 、…日自結構27 此外，該線路增層、纟士椹 層之絕緣保護層Μ， ” Χ设形成有一係如防焊 口 290,俾以顯露該 ，、有I數個開 4線路增層結構表 透過上述製法所形成之嵌埋彻 構係包括驾2,至少一半導f::;s二…板結 25以及第二介電層％。 ' 、第—介電層 該電路板2係具有—第—表面2a及相對之第主 該第-表面2a及第二表面2b分別二之:二表面 路層够且該第二線路層2”具有至有二線 而該電路板2中對應該承托部2iq位置=部2】: 19143 16 1303958 之開口 22以露出該承托部21 〇。 该半導體晶片23係置於該電路板之開口 2 ，且该 ::Γ:係靠在該承托部210上。該半導體晶片二 係具有一作用面230及相對之非作用面 230上具有複數電極墊232。 祕用面 該第-介電層25係形成於該電路 半導體晶片之非作用面231。 表面及' >該第二介電層26係形成於該電路板2之第一表面2a 及该半導體晶片23之作用面23〇，且 -λ ^ ^ ± π亥乐二介電層26係 二;;电路板2之開口 22中，以將該半導體晶片”固定 對：：：二中”其中’該第二介電層26中復形成複數相 對^ + ½脰曰曰片23之電極墊232的 半導體晶片的電極墊232。 以路出》亥 於本實施例中，該嵌埋半導艚曰 .里千¥版日日片之電路板結構復包 =-形成於该弟二介電層26表面之線路增層結構η，該 線路增層結構27係包括介電層27()、4置於該 線路層271，以及形成於該介電層中之導電結構^且兮 導電結構272電性連接至該半導體晶片23之電極塾说， 並於該線路增層結構27表面形成有電性連接塾奶，又今 層結構27表面復形成有—具防焊性質之絕緣保護^ i29,且該絕緣保護層29中具有複數個開口謂，俾以顯 I备鑪線路增層結構表面之電性連接墊2乃。 '、 如第3Α至3Ε圖所示，係顯示本發明之嵌埋 片之電路板結構之製法第二實施例m ’旦曰曰 19143 17 1303958 本實施例之製法係與前述第一實施例大致相同，其不 同之處在於本實施例中，該電路板之第二表面的第二線路 層中形成具開孔之承托部。 如第3A圖所示，係為本發明之製法第二實施例之電 路板的上視圖及剖視示意圖，首先提供一電路板2，該電 路板2係具有一第一表面2a及相對之第二表面孔，該第 一及第二表面2a，2b分別具有第一線路層2〇及第二線路層 21，且該第二線路層21中具有至少一開孔211&之承托部 # 211。接著利用雷射切割方式於該電路板2中對應該承托 211位置形成至少-貫穿該第-及第二表面2a，2b之開口° 22以露出該承托部211，且使該開口 22與該開孔加相 連通。本實施例係利用切割精度高之雷射切割方式於該帝 路板中形成尺寸精度高之開口 22，以使該開口之尺寸與後 續接置於其中之半導體元件在之尺寸相匹配，且形承 部叫’以供支撐半導體晶片，俾可降低後續製程中該半 籲導體晶片被模流沖擊而移動位置。 板2 ^ 所示，將至少一半導體晶片23置於該電路 22中：…，且使該半導體晶片”靠在位於該開口 晶月2r部、2U上’藉由該承托部211以支撐該半導體 "，而该半導體晶片23係具有一作用面230及盥哕 :=對之非作…1，且該作用™ 導體 如第3C圖所示，於該電路板2 曰H u 心弟表面2a及該半 曰 之作用面230形成一保護層24。 19143 18 1303958 如第3D圖晰-〜 體晶片23之二：’於該電路板2之第二表面及該半導 程，以料第Λ 成第一介電層25’並進行塵合製 引入該電路板2: 2225 =托部211之開孔21U 定於該轉板2之開σ22中。’而可將該半導體晶片23固 之第了Λ所示’移除該保護層24，並於該電路板2 表面2a及該半導體 二介電層26。 入 A之作用面230形成-第 體晶片23之ιΙΤ"琶層％中形成複數相對於該半導 的電極墊232。 232的開孔261，以露出該半導體晶片 因此，本發明之製法的第二 割精度高之雷射切_ 、例中，主要係科甩切 穿開口，以降低後二路板形成尺寸較精確之貫 動，同時可透過露出該開口；‘亡::：片產 托部之開孔將該第-介電^而可在後續製程冲藉由該承 該半導體晶片固定於該=，該電路板之開口中，而將 請參閱第3F圖，之後 25,26表面形成一線路增層結構;於°亥弟及弟二介電層 中形成有複數個導電結構、且忒線路增層結構27 23之電極墊232，並以—係二电性連接至該半導體晶片 貫穿該線路增層結構27、第;;電錄導通孔之導電結構28 使该第—線路層2()、第 a路層2G及第二線路層2】，With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, which are mainly 10 devices that are first mounted on a package substrate or lead frame. It is connected to the package substrate or lead frame, and then encapsulated by a gel. Among them, Ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized in that a package substrate is used to place a semiconductor wafer, and a self-alignment technology is used to implant the back surface of the package substrate. A plurality of solder balls arranged in a grid array are arranged so that the I/O connection can be accommodated on the semiconductor I wafer carrier of the same unit area to conform to the height integration (Integration). The semiconductor wafer is required to solder and electrically connect the entire package unit to the external device by means of the solder balls. However, in a conventional semiconductor package structure, a semiconductor wafer is adhered to a top surface of a substrate, and a wire bonding or Flip chip package is applied, and a solder ball is implanted on the back surface of the substrate for electrical connection. It can achieve the goal of high number of feet, but in the case of higher frequency use or high speed operation, it will not be able to produce electrical characteristics due to the long connection path of the wire. 6 19143 1303958 = liter: there is a limit, in addition, due to the tradition When multiple connection interfaces are required, the manufacturing cost is relatively increased. In view of this, 4 can effectively improve the electrical quality and meet the application of the next generation of mouth, the industry has studied the use of the embedded in the carrier board, as a direct electrical connection to shorten the electrical conduction path, and Reduce signal loss, signal distortion and improve the ability to operate at high speeds. Please refer to Fig. 1 to Figure 1 for a flow chart showing the structure of a circuit board structure of a conventional embedded semiconductor. As shown in the figure, firstly, a core board 1 is provided as an insulating board or a single layer or a multi-layer circuit board of a circuit manufacturing process, and the core board (7) has a first surface iOa and a second surface pass and respectively have lines The layers 11a, 11b are formed by at least one opening 10 利用 in the cutting core plate ίο such as a rake. As shown in FIG. 1B, a dielectric layer 13 having a better adhesion is formed on the wiring layer m of the second surface of the core board 1 to fix a wafer, such as PP (prepreg), and At least one semiconductor wafer a is disposed in the opening 100 of the core board 10. The semiconductor wafer U has an active surface 120 and an inactive surface 121 opposite to the active surface, and a plurality of electrode pads 122 are formed on the active surface 120. [] The non-active surface 121 of the semiconductor wafer is placed on the dielectric layer 13. As shown in Fig. 1c, the wiring layer 11a of the first surface 1a of the core board 10 and the active surface 12 of the semiconductor wafer 12 are formed as a protective layer 14 of a release film. As shown in FIG. 1D, a bonding process is performed on the core board 10, so that the material of the dielectric layer 13 > ^ u is filled in the gap between the semiconductors, M, the chip 12 and the core board. 10 jτ 'straw in the opening 1〇〇 of the semi-conducting 髀曰H 〇 10 10, fixed in the core plate to remove the protective layer 14 to the gentleman board 10 and the semi-guided engraving The post-production y process is performed on the core dry body wafer 12. The clothing buckle 'is shown, for example, in the line layer 1E, and forms another layer on the action surface 12 of the core + conductor... as shown in the figure 1F, the dielectric is used. The circuit build-up structure 16 has a circuit board on which a monolithic wafer is formed on the surface, and/or a θ θ line is embedded with at least half of the conductive raft, and a series of layers such as 7 penetrates the line build-up structure. The conductive structure 18 is turned on. The line-layering structure 16 is electrically conductive (4), and the core: the junction = the electrode pad 122 of the dielectric layer wafer 12, and the electrical connection pad is connected to the terminal conductor. 164, and formed on the surface of the 9 9 9 a... structure 16 .亥边路增声社播〗 〖 If the insulation layer of the solder mask is 17, the surface of the prosthesis forms a number of openings (7), and the 绝缘 绝缘 insulation layer 17 has a complex 164. The electrical connection pads of the 1-way line build-up structure 16 can shorten the electrical conduction path according to the embedded half made by the above process, and the daily private board structure rises to the ability of two-frequency operation to overcome the loss. And the Φ ^ white flat conductor wafer is placed on the surface of the Leizheng cup. However, the thickness of the semiconductor wafer 12 of the conventional circuit board is only about 1ϋυ ψ 戾 戾 戾 only about 5〇19143 8 1303958 board 〇 The dielectric layer 13 is not easily adhered, and a gap of about 25 〇 to 500 /zm is left before the hot pressing, so that the semiconductor material flows into the opening 1 后续 in the subsequent pressing process. The wafer η is displaced by the slamming of the stencil, and even flows into the gap, so that the semiconductor wafer 无法 cannot be positioned at the set position. Further, the conventional process uses a milling cutter to form the core plate 1〇: The dimensional accuracy of the second-like sharp knife is about (4)' and the laser cutting precision is 1 () to 25/zm'. Generally, in order to avoid the semiconductor wafer moving in the process, the size of the opening is about equal to the size of the semiconductor wafer. , ^The opening formed by the milling cutter is compared with the laser It is difficult to precisely fit the half of the opening _ (four) = make the + conductor wafer 12 easier to be moved by the mold flow during the process. Clothing = difficult. Here, how to effectively place the semiconductor wafer on the core board In order to avoid the impact of the mold-conductor wafer by the mold flow, the subsequent line increase recording process has become an urgent problem for the industry. [Inventive content] 74. In view of the above-mentioned prior art, the invention provides a buried semiconductor wafer. The circuit board effectively fixes the semiconductor chip in the opening of the circuit board. The purpose of the straw in this form is to provide an embedded semiconductor reed board structure and a manufacturing method thereof, thereby reducing the difficulty of the circuit layer manufacturing process.目的 增 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 a plate having a surface and a surface, the first and second layers having a receiving portion; being cut by a laser and... the position of the bearing portion forming at least -; the corresponding on the road plate Pull out the second line The opening surface of the layer is placed on the opening of the circuit board, and (4) = less than one of the receiving portions of the semiconductor wafer opening, and the semiconductor ^ ^ 4 is placed on the open surface of the circuit board, the active surface has a plurality of turns. Second, there is a working surface and a non-acting and semiconductor crystal>{acting surface: the first surface surface of the circuit board and the semiconductor germanium protective layer'·the second active surface of the circuit board Forming a protective layer for one person; and removing the electric layer from the 电" electric layer, and removing a surface of the stone/...X road board and a semi-conductive film forming a second dielectric layer from the surface, and the The opening of the semiconductor wafer to fix the semiconductor wafer === into the circuit board through the above-mentioned manufacturing method, the basic circuit board structure includes: a plate of the melon chip, and the first and the Two: a circuit layer of the second surface and the opposite second surface, and the second circuit material has a first circuit layer and a second circuit, the support portion has a position; consistently; the upper half is on the circuit board The support part of the opening, the bismuth, / has a working surface and a non-active surface, and the surface is /, a plurality of electrode pads; a first dielectric layer formed on the surface of the 19143 10 1303958 two surfaces of the circuit board and the semiconductor crystal n-type non-active surface; and a second dielectric layer, the instrument '::::: The first surface and the active surface of the semiconductor wafer, and the dielectric layer is pressed into the opening of the circuit board. 71 卞 耻 耻 日 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌a surface and a relative surface: the second line is thick, ... each having a first-circuit layer portion; the support portion having at least one opening is at least one through-the surface and the first pair is supported Part position shape> to: ΐ = the opening is connected to the opening of the receiving portion... Heart two:: the 脰 wafer is placed in the opening of the circuit board: ==_ the receiving portion in the opening of the board The upper surface of the board has a plurality of electrodes and a protective layer on the U side of the board; the first surface of the board = the surface of the wafer is formed - formed - the first - dielectric / :: semiconductor wafer non-acting layer introduction circuit from the opening of the receiving portion to introduce the first - f layer into the opening of the circuit board opening σ force m, and remove the protective layer; And the active surface of the semiconductor wafer is formed - the second dielectric layer; the formed embedded semi-conductive P-plate structure of the present invention comprises: And the opposite circuit board 'and the first and second brother-surface circuit layers, and the nth brother-line layer and the second brother-, and the spring road layer have at least one opening 19143 11 1303958 ^ The opening of the plate corresponding to the position of the receiving portion has the first and second openings to expose the receiving portion, and the opening is connected with the opening of the receiving portion; at least half of the guiding R & The day-to-day film is placed in the opening of the circuit board, and the μ semiconductor chip is placed on the receiving portion of the circuit, the opening of the main "hairboard, the plurality of electrode pads; the first dielectric sound, = The surface has η ^ + , , · 曰 is formed on the second surface of the circuit board and the non-active surface of the semiconductor wafer, and the opening of the μ pedestal is introduced into the circuit board, the electric layer system The semiconductor wafer is fixed on the surface of the circuit board and the active surface of the semiconductor wafer by the opening in the opening of the circuit board. = knowing the technology, the embedded semiconductor circuit of the invention is manufactured by the method of 'the main part of the second surface of the circuit board: ^ can be used for the subsequent installation of the conductive conductor 10 (10 to 25xzm #古夕+日承托Department, and the use of molding precision - ^ laser (four) way in the light board shell teeth of the board - and the second table into the evening 4 of the support part, after the re-appreciation, the road board == Guanglu Forming the first dielectric layer and the second brother: and the younger-surface in the opening of the circuit board respectively, „戈,由;吏吏海乐二 dielectric laminated into the bow I into the festival hunting by the supporting department The opening of the first dielectric sound: the semiconductor wafer is fixed to the opening, and the opening formed by the laser cutting is more suitable for the gold semi-conducting cymbal, and the supporting portion is The size of the semiconductor. The chip is fine and in the subsequent first-dielectric layer or the first intervention; the #action' causes the semiconductor wafer to open at the opening, and does not lead to the second dielectric sound. The first or first electrical layer fixes the material conductor wafer outside the opening 19143 12 1303958 of the circuit board, since the semiconductor wafer is effectively fixed to the circuit board ==Continue to carry out line build-up on the circuit board and the semiconductor device = [Embodiment] The following is a description of specific embodiments: those skilled in the art can understand the present invention. The other inventions are easy to use, and the invention can also be applied by (4) or help. In the present specification, the item ^= is not applied to the application, and the modification and modification of the invention are not carried out. The drawings of the first embodiment of the method for manufacturing the embedded board structure of the present invention are shown in Fig. 2A to 2F. 3 These patterns are simplified dry sounds. Recalling, the strong currency I don't think about it. I only explain the parts of the invention in a schematic way. The number of components in a factory, a, Γ4, and the yuan of the money, and the number of components in the actual implementation. , shape and size ~ beibei yoke 1 - from the size ratio of the choice of selectivity, and ~70 layout patterns may be more complex. As shown in Figure 2A, first provide - have - first Table (10) and the opposite road clover 2 two surfaces 2 to 1 right 1 ^ ^ h - surface 2b, the first And the ^ ^ ', , , and the second circuit layer 21, and the Lu Haiang two circuit layer has a ^ ^ ^ ^ σ Ρ 210. Then use the laser cut eight 7 and the Xun Road board 2 in the corresponding Through the first and first faces 2...to. The position of ρ 210 forms at least -210. The opening 22 is used to expose the receiving portion, and in the embodiment, the circuit board 2 is completed in the front line process. 19143 13 1303958 Double-layer circuit board or multi-layer circuit board. In this embodiment, a relatively precise opening 22 is formed in the circuit board by using a laser cutting method with high cutting precision, so that the size of the opening is subsequently placed. The semiconductor components therein are matched in size and form the receiving portion 210 for supporting the semiconductor wafer, which reduces the probability of positional movement of the semiconductor wafer in subsequent processes. As shown in FIG. 2B, at least one semiconductor wafer 23 is placed in the opening 22 of the circuit board, and the semiconductor wafer 23 is placed on the receiving portion 210 in the opening 22, by the receiving portion 21〇 To support the semiconductor wafer • 23. The semiconductor wafer 23 has an active surface 23() and an inactive surface 231 opposite to the active surface, and a plurality of electrode pads 232 are formed on the active surface 230. The semiconductor wafer 23 can be an active or passive wafer, for example, selected from a capacitor chip, a memory chip, an ASIC (AppHcati) specific integrated circuit, or a Cpu chip. As shown in FIG. 2C, the first surface & the first circuit layer 20 of the circuit board 2 and the active surface 230 of the semiconductor wafer 23 form a protective layer 24 such as a detachable film to avoid the external environment. The contamination or the external force in the process destroys the active surface 230 of the semiconductor wafer 23. As shown in FIG. 2D, a first dielectric layer 25 is formed on the second surface 2b of the circuit board 2, the second circuit layer 21, and the non-active surface of the semiconductor wafer 23, and a pressing process is performed. A dielectric layer 25 is ABF (Ajinomoto Build-up Film) - BCB (Benzocyclo_buthene), LCP (Liquid Crystal Polymer), PI (Poly_imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene) ), FR4, FR5, 14 19143 1303958 BT (Bismaleimide Triazine), aromatic nylon (Aramide) and other photosensitive or non-photosensitive organic resins, or may be mixed with epoxy resin and glass fiber prepreg (Prepreg, PP) and other materials Preferably, the first dielectric layer is made of a prepreg having better adhesion for fixing the wafer. As shown in FIG. 2E, the protective layer 24 is removed, and a second dielectric layer 26 is formed on the first surface 2a of the circuit board 2, the first wiring layer 20, and the active surface 230 of the semiconductor wafer 23. In addition, the first surface 2a of the circuit board 2, the first circuit layer 20, and the active surface 230 of the semiconductor wafer 23 may not form the protective layer 24, but directly form the second dielectric layer 26, and make the first The second dielectric layer 26 is pressed into the opening 22 of the circuit board 2 to fix the semiconductor wafer 23 in the opening 22; wherein the second dielectric layer 26 forms a plurality of electrode pads relative to the semiconductor wafer 23. The opening 261 of the 232 is to expose the electrode pad 232 of the semiconductor wafer 23. The second dielectric layer 26 can be, for example, ABF (Ajinomoto Build_up Film), BCB (Benzocyclo-butliene), LCP (Liquid Crystal Polymer), • Pl (Poly-imide), PPE (Poly (phenylene ether)), PTFE. (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide) and other photosensitive or non-photosensitive organic resins, or may be mixed with epoxy resin and glass fiber prepreg (Prepreg, PP Preferably, the second dielectric layer is made of ABF with better thin layer build-up effect. Therefore, in the first embodiment of the method of the present invention, the through-opening of the semiconductor chip is preferably formed by using a laser cutting method with high cutting precision to form a through-opening of the circuit board with a relatively precise size. Electricity 15 19143 13 03958 The mode flow impact of the layer and the movement of the position... The support of the second circuit layer supports the semi-guided 曰 Γ 压 by the opening in the opening by pressing the circuit board opening ': The wafer 'in turn can be fixed in the opening in a continuous manner. - The electric layer of the semiconductor wafer has the same as shown in Figure 2F. After that, the circuit layer 20' and the second dielectric layer and the second dielectric layer 25 are combined with each other. A conductive layer 21 is formed on the surface of the circuit layer 21 to penetrate the conductive structure 21 of the wiring material structure, so that the first circuit layer 2, the second 4 layer 20 and the second circuit layer 27 are electrically connected. . And: a road layer 21 and a line build-up structure 270, stacked on the dielectric layer, the self-structure 27 includes a conductive structure 27/ in the dielectric layer, and a layer 271, and is formed in the dielectric layer The semiconductor _ purchase ^!:== is connected to the surface to form an electrical connection pad 273. In addition, the line is added to the layer, and the insulation layer of the gentleman's layer is Μ, ” Χ 形成 形成 形成 形成 形成 形成 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 290 The embedded structure formed by the above-mentioned method includes the driver 2, at least half of the f::;s...the junction 25 and the second dielectric layer %. ', the first dielectric layer, the circuit board 2 Having the first surface 2a and the opposite first main surface 2a and the second surface 2b respectively: the two surface layer is sufficient and the second circuit layer 2" has two lines and the circuit board 2 is The opening 22 of the position 2iq position = part 2]: 19143 16 1303958 should be supported to expose the receiving portion 21 〇. The semiconductor wafer 23 is placed in the opening 2 of the circuit board, and the ::Γ: is placed on the receiving portion 210. The semiconductor wafer has an active surface 230 and a relatively non-active surface 230 having a plurality of electrode pads 232 thereon. The secret surface 25 is formed on the non-active surface 231 of the circuit semiconductor wafer. The surface and the second dielectric layer 26 are formed on the first surface 2a of the circuit board 2 and the active surface 23 of the semiconductor wafer 23, and -λ ^ ^ ± πHale dielectric layer 26 In the opening 22 of the circuit board 2, the semiconductor wafer is "fixed to::: two", wherein the second dielectric layer 26 is formed into a plurality of electrode pads of the opposite surface Electrode pad 232 of the semiconductor wafer of 232. In the present embodiment, the circuit board structure of the buried semi-conducting 里. 千千版 日日片包包 =- formed on the surface of the second dielectric layer 26 The circuit build-up structure 27 includes a dielectric layer 27(), 4 disposed on the circuit layer 271, and a conductive structure formed in the dielectric layer, and the germanium conductive structure 272 is electrically connected to the semiconductor wafer 23. The electrode 塾 says that an electrical connection is formed on the surface of the line build-up structure 27, and the surface of the current structure 27 is formed with an insulation protection with solder resistance, and the insulating protective layer 29 has a plurality of The opening is said to be the electrical connection pad 2 of the surface of the build-up structure of the furnace. ', as shown in Figures 3 to 3, showing a circuit board structure of the embedded chip of the present invention. Second Embodiment m' Dan 19143 17 1303958 The system of the present embodiment is substantially the same as the first embodiment. The difference is that in this embodiment, the receiving portion having the opening is formed in the second circuit layer of the second surface of the circuit board. FIG. 3A is a top view and a cross-sectional view of a circuit board according to a second embodiment of the method of the present invention. First, a circuit board 2 is provided. The circuit board 2 has a first surface 2a and a first surface. Two surface holes, the first and second surfaces 2a, 2b respectively have a first circuit layer 2 and a second circuit layer 21, and the second circuit layer 21 has at least one opening 211 & . Then, at least the opening 22 of the first and second surfaces 2a, 2b is formed in the circuit board 2 by the laser cutting method to expose the receiving portion 211, and the opening 22 is The openings are connected in phase. In this embodiment, the opening 22 having high dimensional accuracy is formed in the emperor board by using a laser cutting method with high cutting precision, so that the size of the opening matches the size of the semiconductor component subsequently placed therein, and the shape is matched. The support is called 'for supporting the semiconductor wafer, and the lower half of the conductor wafer is moved by the mold flow to move the position in the subsequent process. As shown in the board 2 ^, at least one semiconductor wafer 23 is placed in the circuit 22: and the semiconductor wafer is placed "on the 2r portion of the opening, 2U" by the support portion 211 to support the semiconductor wafer 23 a semiconductor ", and the semiconductor wafer 23 has an active surface 230 and 盥哕:= is not used for 1, and the active TM conductor is as shown in Fig. 3C on the surface of the circuit board 2 曰H u 2a and the active surface 230 of the half turn form a protective layer 24. 19143 18 1303958 as shown in Fig. 3D - 2 of the body wafer 23: 'on the second surface of the circuit board 2 and the half lead, The first dielectric layer 25' is introduced into the circuit board 2 by dusting: 2225 = the opening 21U of the bracket 211 is defined in the opening σ22 of the rotating plate 2. 'The semiconductor wafer 23 can be fixed First, the protective layer 24 is removed, and the surface 2a of the circuit board 2 and the semiconductor dielectric layer 26 are formed. The active surface 230 of the A is formed into a layer %% of the first wafer 23 a plurality of apertures 261 opposite the semiconducting electrode pads 232. 232 to expose the semiconductor wafer. Thus, the second cut of the method of the present invention High-precision laser cutting _, in the case, the main department is to cut through the opening to reduce the size of the rear two-way plate to form a more precise movement, and at the same time to expose the opening; 'death::: piece production Opening the first dielectric to be etched in the subsequent process by the semiconductor wafer in the opening of the circuit board, and referring to FIG. 3F, and then forming a line on the surface of 25, 26 a layered structure; an electrode pad 232 having a plurality of conductive structures and a germanium line build-up structure 27 23 formed in the dielectric layer of the Hedi and the second dielectric layer, and electrically connected to the semiconductor wafer through the line The layered structure 27, the; the conductive structure 28 of the electrical via hole enables the first circuit layer 2 (), the a channel layer 2G and the second circuit layer 2],
以電性|、g 7 ^ 2】及線路增；^ 0士播H 〜〜結構27係包括介電 19143 19 1303958 於該介電層上之線路層271，以及形成於該介電層 電結構2 7 2。且該線路增層結構2 7表面形成執 功。此外，該線路增層結構表賴形成有_絕耗=塾 且該絕緣保護層29申具有複數個開口 ，俾以 °亥線路增層結構27表面之電性連接墊273。 、 透過上述製法所形成之嵌埋半導體晶片之電路板社 構係包括：電路板2’至少一半導體晶片23、第： 25以及第二介電層26。 电^ 該電路板2係具有一第一表面2a及相對之第二表 2b’該第-及第二表面2心分別具有第—及第二線路層 〇,2卜且該第二線路層21中具有至少一開孔2山之承： 部2Π，而該電路板2中相對應於該承托部2ΐι的位置形 成有至少一貫穿之開口 22以露出該承托部21〇，且該7口 22係與該承托部211之開孔2113相連通。 汗 該半導體晶片23係置於該電路板之開口 22中，且該 +導體晶片23係靠在該承托部211上。該半導體晶片^ 係具有一作用面230及相對之非作用面231，且該^用面 230上具有複數電極墊232。 該第一介電層25係形成於該電路板2之第二表面2匕 及該半導體晶片23之非作用面231，且該第一介電層乃 係透過該承托部211之開孔2 i! a流人該電路板2之^口 22中，以將該半導體晶片23固定於該電路板2之開口 中。 该第二介電層26係形成於該電路板2之第一表 19143 20 1303958 及該半導體晶片23之作用面230，其中，該第二介電層％ 中復形成複數相對於該半導體晶片23之電極墊232的開孔 261 ’以露出該半導體晶片23的電極墊232。 之後復可於該嵌埋半導體晶片23之電路板的第二介 電層26表面形成於一線路增層結構27。此外，該線路增 層結構27表面復形成有一絕緣保護層29。 因此，本發明之嵌埋半導體晶片之電路板結構及苴靠 法Ϊ要雜供—具第-及第二表面之電路板，且該電路柄 之第一及第二表面分別具有第一及第二線路層，而該第二 線路層具有至少—承托部（或具㈣狀承托部）Γ湘 雷射切割方式以於該電路板中相對應於該承把.部的位置形 成貫穿之開口以露出該承托部（或使該開口與該承托部々 開孔相連通);將至少-半導體晶片置於該開口中，以㈣ 該承托部切該該半導體晶片；之後於該電路板二 面及第-表面分別形成第一介電層及第二，：; 第二介電層壓入嗲雷跋把夕„ , 且使邊 节門口中…二 之開σ中以固定該半導體晶片於 遠開口中（或猎由該承托部之開σ將該第—介電 电路，，口），以將該半導體晶片固定於該開口中。/ 相較於習知技術，本發明之 結構及其製法，主要係於電路板第二表面之工= 形成可供後續接置半導俨θ 罘一、.泉路層中 較高之κ托部’並利用成型精度 季乂问之田象切割以於該電路土贯度 第-及第二表面且尺寸較精該電路板 部；之後復可於該電路板之第二二=該承托 及乐表面分別形成第一 19143 21 1303958 介電層及第二介+爲 X. ;丨电層，且使該弟二介電層壓入該電路 開口中，或藉由該料部之開孔將該第一 口，以將該半導體晶片有效固定於該開口中。本發明;開 該具較精確尺寸之開口與置於其中之半導體晶片之尺 寸相匹配，且該承托部對該半導體晶片亦 =後續第一介電層或第二介電層流入該開口中二 +導體晶片在該^中產生偏移，俾可藉由該第一或 弟-介電層將該半導體晶片固定於該電路板之開口中。此 外’由於該半導體晶片固定於該電路板之開口巾，俾可尸夂 低後續於該電路板及該半導體晶片上進行線 ^ 困難度。 衣往^ 上述實施例僅為例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發日狀精神減.下，對上述實施例進行修飾 與變化。因此，本發明之權利保護範圍申 專利範亂所列。 申5月 【圖式簡單說明】 第1A至1F圖，係顯示習知嵌埋半導體晶片之 結構之製法流程圖； 敬 第2A至2F圖，係顯示本發明之嵌埋半導體晶片之電 路板結構之製法第一實施例之流程圖；以及… 第3A圖，係顯示本發明之嵌埋半導體晶片之電路板 結構之製法第二實施例的電路板上視及剖視示意圖。 第3B至3F圖，係顯示本發明之嵌埋半導體晶片之電 19143 22 1303958 路板結構之製法第二實施例之流程圖。 【主要元件符號說明】Electrical property, g 7 ^ 2] and line increase; ^ 0 broadcast H ~ ~ structure 27 includes dielectric 19143 19 1303958 on the dielectric layer of the circuit layer 271, and formed in the dielectric layer electrical structure 2 7 2. And the surface of the line build-up structure 27 forms a function. In addition, the line build-up structure is formed with _depletion = 塾 and the insulating protective layer 29 has a plurality of openings, and the electrical connection pad 273 of the surface of the layer 27 is added. The circuit board structure for embedding the semiconductor wafer formed by the above method comprises: the circuit board 2' at least one of the semiconductor wafer 23, the 25th and the second dielectric layer 26. The circuit board 2 has a first surface 2a and an opposite second surface 2b'. The first and second surface 2 cores have first and second circuit layers, respectively, and the second circuit layer 21 The bottom plate has at least one opening 2: a portion 2, and at least one through opening 22 is formed in the circuit board 2 at a position corresponding to the receiving portion 2ΐ to expose the receiving portion 21〇, and the 7 The port 22 is in communication with the opening 2113 of the receiving portion 211. The semiconductor wafer 23 is placed in the opening 22 of the circuit board, and the + conductor wafer 23 rests on the receiving portion 211. The semiconductor wafer has an active surface 230 and an opposite non-active surface 231, and the surface 230 has a plurality of electrode pads 232 thereon. The first dielectric layer 25 is formed on the second surface 2 of the circuit board 2 and the non-active surface 231 of the semiconductor wafer 23, and the first dielectric layer is penetrated through the opening 2 of the receiving portion 211. i! a stream is placed in the opening 22 of the circuit board 2 to fix the semiconductor wafer 23 in the opening of the circuit board 2. The second dielectric layer 26 is formed on the first surface 19143 20 1303958 of the circuit board 2 and the active surface 230 of the semiconductor wafer 23, wherein the second dielectric layer is formed in plural relative to the semiconductor wafer 23 The opening 261' of the electrode pad 232 exposes the electrode pad 232 of the semiconductor wafer 23. Then, a surface of the second dielectric layer 26 of the circuit board embedded with the semiconductor wafer 23 is formed on a line build-up structure 27. In addition, an insulating protective layer 29 is formed on the surface of the line build-up structure 27. Therefore, the circuit board structure and the immersion method of the embedded semiconductor wafer of the present invention are required to be supplied to the circuit board having the first and second surfaces, and the first and second surfaces of the circuit handle have the first and the second a second circuit layer, wherein the second circuit layer has at least a receiving portion (or a (four) shaped receiving portion) a Xiaoxiang laser cutting method for forming a penetrating position in the circuit board corresponding to the position of the bearing portion Opening to expose the receiving portion (or to connect the opening to the receiving portion opening); placing at least a semiconductor wafer in the opening, and (4) cutting the semiconductor wafer by the receiving portion; Forming a first dielectric layer and a second surface on the two sides and the first surface of the circuit board, respectively; the second dielectric layer is laminated into the 嗲 跋 , , and the opening σ of the edge of the side gate is fixed to fix the The semiconductor wafer is mounted in the distal opening (or the first dielectric circuit, the opening by the opening of the receiving portion) to fix the semiconductor wafer in the opening. / Compared to the prior art, the present invention The structure and its method are mainly based on the second surface of the circuit board = forming for subsequent connection Guide θ 罘 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 And then the second part of the circuit board = the support and the music surface respectively form a first 19143 21 1303958 dielectric layer and a second dielectric + is X.; the electric layer, and the second dielectric layer Pressing the first opening into the opening of the circuit or by the opening of the material portion to effectively fix the semiconductor wafer in the opening. The invention opens the opening with a more precise size and is placed therein The dimensions of the semiconductor wafer are matched, and the receiving portion is offset by the semiconductor wafer or the subsequent first dielectric layer or the second dielectric layer flowing into the opening. The first or di-dielectric layer fixes the semiconductor wafer in the opening of the circuit board. Further, since the semiconductor wafer is fixed to the opening of the circuit board, the semiconductor chip and the semiconductor are subsequently removed. The difficulty of performing the wire on the wafer. The above embodiment is merely illustrative. The present invention may be modified and altered without departing from the spirit of the present invention, and the present invention may be modified and changed without departing from the spirit of the present invention. The scope of the invention is disclosed in the patent application. May 5 [Simple Description of the Drawings] Figures 1A to 1F show the flow chart of the structure of the conventional embedded semiconductor wafer; 2A to 2F, A flow chart showing a first embodiment of a method for fabricating a circuit board structure of an embedded semiconductor wafer of the present invention; and FIG. 3A is a circuit board showing a second embodiment of a circuit board structure for embedding a semiconductor wafer of the present invention; A top view and a cross-sectional view. Figures 3B to 3F are flow charts showing a second embodiment of the method of fabricating the 19193 22 1303958 circuit board structure of the embedded semiconductor wafer of the present invention. [Main component symbol description]
10 核心板 10a 、 2a 第一表面 10b 、 2b 第二表面 100 、 22 、 290 開口 11a 、 lib 、 162 、 271 線路層 lib 、 121 、 231 非作用面 12 > 23 半導體晶片 120 、 230 作用面 122 、 232 電極墊 13 、 15 、 161 、 270 介電層 14、24 保護層 16、27 線路增層結構 163 、 272 導電結構 164 、 273 電性連接墊 17、29 絕緣保護層 171、211a、261 開孔 18、28 導電結構 2 電路板 20 第一線路層 210、21 1 承托部 21 第二線路層 25 第一介電層 26 第二介電層 23 1914310 core board 10a, 2a first surface 10b, 2b second surface 100, 22, 290 opening 11a, lib, 162, 271 circuit layer lib, 121, 231 inactive surface 12 > 23 semiconductor wafer 120, 230 active surface 122 232 electrode pad 13 , 15 , 161 , 270 dielectric layer 14 , 24 protective layer 16 , 27 line build-up structure 163 , 272 conductive structure 164 , 273 electrical connection pad 17 , 29 insulation protective layer 171 , 211a , 261 Hole 18, 28 Conductive structure 2 Circuit board 20 First circuit layer 210, 21 1 Support part 21 Second line layer 25 First dielectric layer 26 Second dielectric layer 23 19143