1301203 測試點。 但是，習知之技術有著無法避免之缺失，其如下列所 述： (1) 錯誤率高。所謂的目視檢查檢視測試點即是指以 肉眼檢視各個測試點之間的距離，若是功能較少，複雜性 較低的電路板，其功能電路的測試點也許只有數十個，若 以肉眼檢視其測試點是否設計適當，檢示結果的錯誤率也 不會太高，但是相較於功能性較為繁多的電路板，如：電 腦主機板，其功能電路所需所標示的記錄點少說也以千點 計算，並不易檢視出測試點之錯誤所在，如此即難以產生 正確的線路測試輸出；其次，依現今邏輯電路軟體而言， 當匯入分析結果檔案時，其所能取得之分析資訊多為文字 列表，即是列出錯誤的測試點編碼資訊與相對應之座標設 定，再由逐一比對以尋求測試點之設置位置，若數量眾多， 則資訊比對容易錯誤而產生不必要的人為疏失。 (2) 時間成本過高，習知之技術中，若以人工作業， 則為逐步審視每一測試點之配置距離，但舉凡任一種電路 板，如電腦主機板，其所標示的記錄點即千點以上，若逐 一省視，十分耗費時間成本；其次5若是當匯入分析結果 檔案於到邏輯電路軟體時，也多以文字列表呈現，研發人 員需逐步比對不合格之測試點於電路板上之定點配置，但 測試點數量較多時，配置錯誤之測試點相對應較為增加， 如此研發人員於比對作業即會花費大量的時間；再者，即 使便是配合邏輯電路軟體分析測試點，但也是將各測試點 1301203 - 逐一與其它測試點相比對，即可能重複檢測到測試點之間 - 的距離，或是將明顯於不同位置之測試點進行不必要的點 距比對，進而花費不必要的時間成本。 【發明内容】 . 有鑑於此，為改進習知技術之缺失，增進使用者之便 利性，並簡化邏輯電路測試流程以提高生產效率，本發明 係提出邏輯線路之點距分析方法。 本發明係一種邏輯線路之點距分析方法，係應用一邏 輯電路設定檔案直接產生可匯入邏輯電路軟體之測試點距 離分析結果，其邏輯電路軟體可為現今業者常使用的邏輯 電路設計軟體Allegro，係透過邏輯電路軟體先輸出一邏 輯電路設定檔案，其檔案具有電路板進行測試時，所需之 各測試點的相關資訊，包含各測試點編碼資訊以及與測試 點編碼資訊相對應之測試點座標設定，接著利用一點距分 析程序以逐步比對字串的方式，遵循一編碼規則以取得包 參 含於邏輯電路設定檔案中的複數個測試點編碼資訊，並以 同樣方式取得所有測試點編碼資訊的測試點座標設定，然 後載入一電路區域劃分規則以將電路板劃分複數個電路區 域，係依這些測試點座標設定以指定各測試點編碼資訊所 對應之電路區域，再載入一點距分析規則，分析於同電路 區域中，各成對的測試點座標設定之間的預測距離值為多 少，最後再將不符合點距分析規則的測試點座標設定標記 出來，並將其測試點編碼資訊、成對的測試點座標設定與 對應電路區域記錄生成一分析結果檔案，以匯入邏輯電路 1301203 • 軟體。 - 當邏輯電路軟體匯入分析結果檔案時，會以圖像來顯 示其分析結果。邏輯電路軟體會先載入電路板之線路設定 與測試點配置，接著載入分析結果檔案，係顯示電路區域 • 的劃分與各測試點所對應的電路區域，然後依照分析結果 . 將不符合點距分析規則的測試點與所屬的電路區域以顯眼 的顏色或是特殊符號加以標記，藉此協助研發人員快速了 I 解線路設計之錯誤所在，以便進行修正。 本發明係一種邏輯線路之點距分析方法，係具備下述 數點優於先前技術之作法，並具備如下所述之顯著功效增 進。 (1) 錯誤率小，於習知技術中，測試點之點距分析多 半由人工以肉眼檢視其電路圖上測試點之配置，或是將分 析結果檔案匯入邏輯電路軟體以人工比對錯誤測試點之配 置位置，但隨著電路板的功能性增加，所需檢視的測試點 • 也增加，相對的，發生人為疏失的機率也相對性提高；而 本發明係以點距分析程序自動於電路板上劃分數個電路區 域，並自動分析各電路區域中成對測試點座標設定之間的 預測距離值，且能以特定圖式加以標記錯誤的測試點座標 設定以及所在之電路區域’如此研發人貝完整的檢視所有 錯誤測試點之所在，以降低測試結果的錯誤率。 (2) 降低時間成本，於習知技術中，測試點之點距分 析多半由人工方式進行作業，要是電路板的功能複雜，所 需配置之測試點會相對性增加，以肉眼檢視則需花費不少 1301203 時間，若以邏輯電路軚體協助分析，係為逐一比對各測試 點其匕測试點之間的趣離，則可能重複檢測到測試點之間 的距離；而本發明係利用點距分析程序全自動分析成對的 测試點座標設定之間的預測距離，並標記突顯錯誤之測試 點所在位置與對應之電路區域，使研發人員於省視時大幅 節省時間成本，此外利用劃分電路區域可避免成對的測試 點座&没定重複檢視，而且若是電路區域内無測試點或只 有一個測試點，則無需檢測，同時也能減少檢測所需的時 間成本。 為使對本發明的目的、構造特徵及其功能有進一步的 了解’茲配合相關實施例及圖式詳細說明如下： 【實施方式】 請參照第1圖’其為本發明之系統架構圖，本圖所欲 表達的意義在於一般通用的邏輯電路軟體11〇時常無法有 效在進行邏輯電路的測試點分析，因此為提升測試點·分析 的便利性，係在邏輯電路軟體11Q外掛一個中介的點距分 析程序120以及儲存各種點距資訊的點距資料庫13〇來協 助遊輯電路軟體110進行測試點座標設定的點距分析。 其中，點距資料庫130包含一區域資料庫131與一分 析貧料庫132，區域資料庫131係儲存複數個電路區域劃 分規則，、而分析資料庫132儲存複數個點距分析規則，各 毛路區域心規則與各點距分析規則係適用於相對應的電 =板歧。邏輯電路軟體nG係能輪出一邏輯電路設定播 111且/、有一檢修程序112，邏輯電路設定檔案111係 1301203 包含所有測試點編碼資訊以及相對應的測試點座標設定， 檢修程序112用以顯示匯入樓案所包含的資訊。 點距分析程序120包含一擷取程序121、一分析程序 122與一檢視程序123,擷取程序121係用以擷取邏輯電路 設定檔案111中所包含的所有測試點編碼資訊以及相對應 的測試點座摞設定，且能從區域資料庫131中載入一電路 區域劃分規則，係藉由測試點座標設定以區分各個測試點 編碼設定所對應的電路區域，並形成區分結果資訊以傳送 > 至分析程序122。 而檢視程序123係檢視所取得的電路區域劃分規則是 否適用於此電路板的線路設定，所需得的規則劃分方式若 不適用於此線路設定，則可令擷取程序121取得一個新的 電路區域劃分規則以重新劃分電路區域。 分析知序122於取得區分結果資訊後，自分析資料庫 132載入一個點距分析規則，係逐步檢視與分析同一電路 _區域裡’成對測試點座標設定之間的預測距離值，若任何 電路區域中’有檢視到有不符合點距分析規則之成對的測 試點座標設定存在時，除了會記錄此成對的測試點座標設 定’還會記錄其對應的測試點編碼資訊與測試點座標設定 所屬的電路區域。但於檢視過程當中，檢視到對應此電路 區域之測試點座標設定只有一個或是是零個時，會標記此 電路區域，但不進行點距分析，而是直接檢視下一個電路 區域。當分析完成時，分析程序122會將分析結果生成分 析結果棺案並匯入至邏輯電路軟體110，以利用檢修程序 1301203 • 112顯示分析結果。檢修程序112會載入電路板的線路設 - 定並以圖像顯示，再將測試點依其測試點座標設定以圖示 映射於圖中且標明測試點編碼資訊，最後將不合格的測試 點以及所在的電路區域用特殊顏色、圖示或符號作視覺化 • 的突顯標記，以協助研發人員明確知道不合格的測試點之 . 所在位置。 請參考第2圖，其為本發明之方法流程圖，係應用一 ^ 邏輯電路設定檔案111直接產生可匯入邏輯線路軟體之測 試點距離分析，其方法含下列步驟： 步驟S201，透過字串比對方式查找邏輯電路設定檔案 111中複數個測試點編碼資訊，此邏輯電路設定檔案111 係由一邏輯電路軟體110輸出，並利用一擷取程序121以 字串比對方式查找出所有測試點編碼資訊。 步驟S202，自邏輯電路設定檔案111擷取對應各測試 點編碼資訊之複數個測試點座標設定，擷取程序121係以 • 測試點編碼資訊為基本字串，再次進行查找並取得所有對 應各測試點編碼資訊的測試點座標設定。 步驟S203，載入一電路區域劃分規則，依照此些座標 設定以指定各測試點編碼資訊所對應之複數個電路區域， 擷取程序121係從一區域資料庫131以載入電路區域劃分 規則以將電路板劃分成各個不同之電路區域，並將各測試 點編碼資訊依照其測試點座標設定指定每一測試點編碼資 訊所對應的電路區域，以形成一區分結果資訊再傳送至一 分析程序122。 11 1301203 - 步驟S204，載入一點距分析規則，依序自各電路區域 - 分析區域中所包含各成對之測試點座標設定之間所對應之 一預測距離值。分析程序122於接收區分結果資訊時，係 從分析資料庫132載入點距分析規則，並逐步檢視在同電 . 路區域中各成對的測試點座標設定之間的預測距離值，然 而於檢視過程中，若檢視出某電路區域中未包含有成對的 測試點座標設定，即是指僅一個測試點座標設定或沒有任 何測試點座標設定對應此電路區域，則標記此電路區域但 不進行點距分析。 步驟S205，當任一預測距離值不符點距分析規則時， 標記預測距離值所對應成對之測試點座標設定及對應電路 區域，並記錄於一分析結果檔案，以匯入邏輯電路軟體 110。當進行分析預測距離值時，如果有任何成對的測試點 座標設定所分析出來的預測距離值並不符合點距分析規 則，則將其成對的測試點座標設定進行標記並記錄其所有 • 對應資訊。然而，在分析結果檔案中更記錄一顯示屬性資 訊，以提供邏輯電路軟體110讀取進行差異顯示。測試點 於進行點距分析時，係會遇到各種不同的分析結果，在分 析結果檔案中，我們能以不同的顯示設定來表示不同的意 義，如：不合格的測試點以紅線圈選標示，則在記錄測試 點座標設定的所對應資訊時，將紅線的顯示設定值依附測 試點座標設定的對應資訊以記錄於分析結果檔案中，當邏 輯電路軟體110匯入分析結果檔案時，其電路設定與分析 結果係由檢修程序輸出顯示，此時不合格的測試點座標設 12 1301203 定即會以紅線圈選標#，如此研發人員便能俠速了解點距 分析結果並進行電路的設計修正。 ^清參考第3圖，其為本發明之邏輯電路設定檔案lu ^袼式7K意圖’如槽案格式圖細所示之播案格式，其 .包含電路板編碼，係用以擷取相對應之電路區域劃分規則 、及』距刀析規則。Tp即是指測試點，其後方包含與其對 應的測試點編媽資訊與測試點座標設定。 _查月《考第圖與第圖，其分為本發明之電路區域 /刀月彳n W刀後的簡單示意圖，測試點配置圖係表示 操取程序121從邏輯電路設定辟⑴取制試點資訊 時，將測試點分別映射至電路板上的晝面，此時擷取程序 21肖未載入區域劃分規則H或劃分圖402即代表著 f取耘序121從區域資料庫13丨載入電路區域劃分規則 :έ於私路板上劃分數個電路區域並依照所有測試點座 標設定以指定所屬的電路區域，此外還可對各個電路區域 進行編碼歧標上職點編碼:#訊。 咕i…第5圖，此為本發明之測試點標記圖，當分析 =序122將所有分析結果整合形成分析結隸案，並匯入 ^輯包路|人體11〇日夺，邏輯電路軟體m會將分析結果檔 =所包含之資訊映射至電路板上簡示其分析結果。邏輯 i路权體11G係先將電路板的線路歧與測試點配置設定 載入，接著匯入分析結果檔案並梅取出所使用的區域劃分 ^則以心I路區域’其次操取電路區域的分析結果，將 未進行點距分析的電路區域以黑色粗框標記，不合格測試 13 1301203 點座標設定則以紅線圈選，其所對應的電路區域係以紅色 粗框標記，並將標記完成的電路板相關貧料以檢修程序輸 出並以視覺化顯示，其顯示方式如標記圖500所示，電路 區域B6包含的測試點皆不符合點距分析規則，而不合格的 理由在於（1)其中有兩個測試點位置重疊，（2)其中三個測 試點的記置位置重疊，（3)其中有兩個測試點之點距太過相 近。而上述不合格的測試點皆以紅線圈選標記，電路區域 B6本身則以紅色粗框標記，藉以顯示出此電路區域内有不 合格的測試點存在。而電路區域C4與C6所具有之測試點 不滿兩點，所以並未進行點距分析，因此以黑色粗框標記。 請參照第6圖，其為本發明之分析結果檔案格式範 例，分析結果格式圖600中所示之檔案格式包含有電路板 編碼、所使用之電路區域劃分規則、不合規則之測試點編 碼資訊、測試點座標設定以及預測距離值，並以【M】表明 不合規則之測試點資訊；此外分析結果檔案具有的資訊還 可以包含未進行分析的電路區域，係將其電路區域的編碼 寫入其中，並以【N】表示此電路區域並未進行點距分析。 雖然本發明之實施例揭露較隹方式如上所述，然其並 非用以限定本發明，任何熟習相關技藝者，在不脫離本發 明之精神和範圍内，當可作些許之更新與潤飾，因此本發 明之專利保護範圍須視本說明書所附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1圖係本發明之系統架構圖； 14 1301203 第2圖係本發明之方法流程圖； 第3圖係本發明之趣輯電路設定檀案格式不意圖， 第4A圖係本發明之測試點配置圖； 第4B圖係本發明之電路區域劃分示意圖 第5圖係本發明之測試點標記示意圖；以及 第6圖係本發明之分析結果檔案格式示意圖。 【主要元件符號說明】1301203 Test point. However, the technique of the prior art has an inevitable deficiency, as described below: (1) The error rate is high. The so-called visual inspection inspection test point refers to visually checking the distance between each test point. If the circuit board has less function and less complexity, the test points of the functional circuit may only be dozens, if it is visually inspected. Whether the test point is properly designed or not, the error rate of the test result is not too high, but compared with the more functional circuit board, such as the computer motherboard, the recorded points required for the functional circuit are less In thousands of points, it is not easy to check the error of the test point, so it is difficult to produce the correct line test output. Secondly, according to the current logic circuit software, when the analysis result file is imported, the analysis information that can be obtained Mostly a list of words, that is, the wrong test point code information and the corresponding coordinate setting are listed, and then the comparison is made one by one to find the set position of the test point. If the number is large, the information comparison is easy to be mistaken and unnecessary. Man-made negligence. (2) The time cost is too high. In the conventional technology, if manual operation is used, the configuration distance of each test point is gradually reviewed. However, for any type of circuit board, such as a computer motherboard, the marked points are thousands. If you click above, it will take a lot of time and cost. Secondly, if you import the analysis result file into the logic circuit software, it will be presented in a text list. The R&D personnel need to gradually compare the unqualified test points on the circuit board. On the fixed point configuration, but the number of test points is large, the test points of the configuration error are relatively increased, so that the researcher will spend a lot of time on the comparison operation; in addition, even with the logic circuit software analysis test point However, it is also possible to compare each test point 1301203 - one by one with other test points, that is, it is possible to repeatedly detect the distance between the test points - or to perform unnecessary dot pitch comparison on test points that are distinct at different positions. In turn, unnecessary time costs are incurred. SUMMARY OF THE INVENTION In view of the above, in order to improve the lack of the prior art, improve the convenience of the user, and simplify the logic circuit test flow to improve the production efficiency, the present invention proposes a method for analyzing the pitch of the logic line. The invention relates to a method for analyzing the pitch of a logic line, which is a logic circuit setting file directly generating a test point distance analysis result which can be imported into a logic circuit software, and the logic circuit software can be a logic circuit design software commonly used by the current industry Allegro The logic circuit software first outputs a logic circuit setting file, and the file has the relevant information of each test point required for testing the circuit board, and includes test information of each test point and test points corresponding to the test point code information. The coordinate setting, and then using the one-point distance analysis program to gradually compare the strings, follow an encoding rule to obtain the plurality of test point coding information contained in the logic circuit setting file, and obtain all the test point codes in the same manner. The test point coordinate setting of the information, and then loading a circuit area division rule to divide the circuit board into a plurality of circuit areas, according to the coordinates of the test point coordinates to specify the circuit area corresponding to each test point coding information, and then load a little distance Analyze the rules and analyze them in the same circuit area. The value of the predicted distance between the test point coordinates is set. Finally, the test point coordinate setting that does not meet the point distance analysis rule is marked, and the test point coding information, the paired test point coordinate setting and the corresponding circuit area are set. The record generates an analysis result file for import into logic circuit 1301203 • Software. - When the logic circuit software is imported into the analysis result file, the analysis result is displayed as an image. The logic circuit software will first load the line setting and test point configuration of the board, and then load the analysis result file, which shows the division of the circuit area and the circuit area corresponding to each test point, and then according to the analysis result. The test points from the analysis rules and the associated circuit areas are marked with conspicuous colors or special symbols to help the developer quickly resolve the error in the circuit design for correction. The present invention is a method for analyzing the pitch of a logical line, which has the following advantages over the prior art and has significant efficiency improvements as described below. (1) The error rate is small. In the prior art, the point distance analysis of the test points is mostly performed by manually visually checking the configuration of the test points on the circuit diagram, or by importing the analysis result files into the logic circuit software to manually compare the error tests. The position of the point is configured, but as the functionality of the board increases, the number of test points to be inspected also increases, and the probability of human error is relatively increased. The present invention automatically uses the point distance analysis program to circuit the circuit. The board divides several circuit areas, and automatically analyzes the predicted distance between the paired test point coordinate settings in each circuit area, and can mark the wrong test point coordinate setting and the circuit area in the specific pattern. People complete the inspection of all the wrong test points to reduce the error rate of the test results. (2) Reduce the time cost. In the prior art, the point distance analysis of the test points is mostly performed manually. If the function of the circuit board is complicated, the test points of the required configuration will increase relative, and the visual inspection will cost A lot of 1301203 time, if the logic circuit assists the analysis, it is to compare the interesting points between the test points of each test point one by one, then the distance between the test points may be repeatedly detected; and the present invention utilizes The point distance analysis program automatically analyzes the predicted distance between the paired test point coordinate settings, and marks the location of the test point where the error is highlighted and the corresponding circuit area, so that the research and development personnel can save time and cost in a timely manner, and further utilize the division. The circuit area avoids the paired test point holders and does not have to repeat the inspection, and if there is no test point or only one test point in the circuit area, no detection is required, and the time cost required for the detection can be reduced. In order to further understand the objects, structural features and functions of the present invention, the following detailed description will be given with reference to the related embodiments and drawings: [Embodiment] Please refer to FIG. 1 which is a system architecture diagram of the present invention. The meaning of the expression is that the general-purpose logic circuit software 11 can not effectively perform the test point analysis of the logic circuit. Therefore, in order to improve the convenience of the test point and analysis, an intervening point distance analysis is attached to the logic circuit software 11Q. The program 120 and the point distance database 13 for storing various point distance information assist the game circuit software 110 in performing the point distance analysis of the test point coordinates setting. The point distance database 130 includes a regional database 131 and an analysis poor storage library 132. The regional database 131 stores a plurality of circuit area dividing rules, and the analysis database 132 stores a plurality of point spacing analysis rules. The road area heart rule and each point distance analysis rule are applicable to the corresponding electric=plate difference. The logic circuit software nG can rotate a logic circuit setting broadcast 111 and/or has a maintenance program 112. The logic circuit setting file 111 is 1301203, including all test point code information and corresponding test point coordinate settings, and the maintenance program 112 is used to display The information contained in the remittance case. The point distance analysis program 120 includes a capture program 121, an analysis program 122, and a view program 123. The capture program 121 is configured to capture all test point code information and corresponding tests included in the logic circuit setting file 111. The 摞 摞 setting, and a circuit area division rule can be loaded from the area database 131, by using the test point coordinate setting to distinguish the circuit area corresponding to each test point code setting, and forming a difference result information for transmission > To the analysis program 122. The viewing program 123 checks whether the obtained circuit area division rule is applicable to the line setting of the circuit board. If the required rule division mode is not applicable to the line setting, the capture program 121 can obtain a new circuit. The area division rule is to re-divide the circuit area. After the analysis sequence 122 obtains the difference result information, the self-analysis database 132 loads a point distance analysis rule, which is a stepwise view and analysis of the predicted distance value between the paired test point coordinate settings in the same circuit_area, if any In the circuit area, when there is a pair of test point coordinate settings that do not meet the point distance analysis rule, in addition to recording the pair of test point coordinate settings, the corresponding test point code information and test points are also recorded. The coordinates of the circuit area to which the coordinates are set. However, during the inspection process, when the test point coordinate setting corresponding to the circuit area is only one or zero, the circuit area is marked, but the dot distance analysis is not performed, but the next circuit area is directly inspected. When the analysis is complete, the analysis program 122 will generate an analysis result file and import it into the logic circuit software 110 to display the analysis result using the service program 1301203 • 112. The inspection program 112 will load the circuit board setting and display it as an image, and then set the test point according to its test point coordinate to map the figure and indicate the test point coding information, and finally the unqualified test point. And the circuit area in which it is located is highlighted by special colors, icons or symbols to help developers clearly know the location of the unqualified test points. Please refer to FIG. 2 , which is a flowchart of the method of the present invention. The method 1 includes a logic circuit setting file 111 to directly generate a test point distance analysis that can be imported into the logic circuit software, and the method includes the following steps: Step S201, through the string The comparison mode finds a plurality of test point coded information in the logic circuit setting file 111. The logic circuit setting file 111 is outputted by a logic circuit software 110, and uses a capture program 121 to find all test points in a string comparison manner. Encoding information. In step S202, a plurality of test point coordinates corresponding to each test point coded information are retrieved from the logic circuit setting file 111, and the capture program 121 uses the test point coded information as a basic character string to perform a search again and obtain all corresponding tests. Test point coordinates setting for point coded information. Step S203, loading a circuit area division rule, according to the coordinate settings to specify a plurality of circuit areas corresponding to each test point coded information, the capture program 121 is from a regional database 131 to load the circuit area division rule. The circuit board is divided into different circuit areas, and each test point code information is set according to the test point coordinates to specify a circuit area corresponding to each test point code information, to form a differentiated result information and then transmitted to an analysis program 122. . 11 1301203 - Step S204, loading a one-point distance analysis rule, sequentially corresponding to a predicted distance value between each pair of test point coordinates included in each circuit area - analysis area. The analysis program 122 loads the point-distance analysis rule from the analysis database 132 when receiving the discrimination result information, and gradually checks the predicted distance value between each pair of test point coordinate settings in the same electric path area, however, During the inspection process, if a pair of test point coordinate settings are not included in a certain circuit area, that is, only one test point coordinate setting or no test point coordinate setting corresponds to the circuit area, the circuit area is marked but not Perform a point distance analysis. Step S205: When any of the predicted distance values does not conform to the point distance analysis rule, the pair of test point coordinates and the corresponding circuit area corresponding to the mark predicted distance value are recorded in an analysis result file to be imported into the logic circuit software 110. When analyzing the predicted distance value, if any of the paired test point coordinates set the predicted distance value that is not in accordance with the point distance analysis rule, mark the paired test point coordinate settings and record all of them. Corresponding information. However, a display attribute information is further recorded in the analysis result file to provide the logic circuit software 110 to read and display the difference. When the test point is used for the point distance analysis, the system will encounter various analysis results. In the analysis result file, we can express different meanings with different display settings. For example, the unqualified test points are marked with red coils. When the corresponding information set by the test point coordinates is recorded, the display setting value of the red line is attached to the analysis result file according to the corresponding information set by the test point coordinate, and when the logic circuit software 110 merges into the analysis result file, the circuit thereof The setting and analysis results are outputted by the inspection program. At this time, the unqualified test point coordinates 12 1301203 will be selected with the red coil #, so that the developer can understand the point distance analysis result and design the circuit. . ^ Clear reference to Figure 3, which is the logic circuit setting file of the present invention. The file format is shown in the figure of the slot format, which includes the circuit board code, which is used to retrieve the corresponding file. The circuit area division rules, and the distance from the knife analysis rules. Tp refers to the test point, and the rear contains the test point information and test point coordinates set corresponding to it. _Chayue "test map and map, which is divided into a simple schematic diagram of the circuit area / knife 彳 n W knife of the present invention, the test point configuration diagram indicates that the operation program 121 is set up from the logic circuit (1) In the information, the test points are respectively mapped to the facets on the circuit board. At this time, the capture program 21 is not loaded with the region division rule H or the segmentation map 402, that is, the f fetch sequence 121 is loaded from the region database 13丨. Circuit area division rule: divides several circuit areas on the private board and sets the circuit area according to all the test point coordinates. In addition, the coding area of each circuit area can be coded: #讯.咕i... Figure 5, this is the test point mark diagram of the present invention. When the analysis = sequence 122, all the analysis results are integrated to form an analysis and the case is merged into the package. The human body is 11 days old, and the logic circuit software is used. m will map the analysis result file=the information contained on the board to the board to show its analysis results. The logical i-way weight 11G first loads the circuit board's line disambiguation and test point configuration settings, then imports the analysis result file and extracts the area used by the ^ division, then the heart I-area area 'the second operation circuit area' As a result of the analysis, the circuit area where the dot distance analysis is not performed is marked with a thick black frame, and the unqualified test 13 1301203 point coordinate setting is selected with a red coil, and the corresponding circuit area is marked with a red thick frame, and the mark is completed. The board related poor material is outputted by the inspection program and displayed visually. The display mode is as shown in the marking diagram 500. The test points included in the circuit area B6 are not in accordance with the point spacing analysis rule. The reason for the failure is that (1) There are two test point positions overlapping, (2) the position of the three test points overlap, and (3) the distance between the two test points is too close. The above unqualified test points are marked with a red coil, and the circuit area B6 itself is marked with a thick red frame to indicate that there is an unqualified test point in the circuit area. However, the test points of circuit areas C4 and C6 are less than two points, so the point distance analysis is not performed, so it is marked with a thick black frame. Please refer to FIG. 6 , which is an example of the analysis result file format of the present invention. The file format shown in the analysis result format diagram 600 includes circuit board coding, circuit area division rules used, and non-rule test point coding information. Test point coordinate setting and predicted distance value, and [M] indicates the test point information of the irregular rule; in addition, the information of the analysis result file may also include the circuit area that is not analyzed, and the code of the circuit area is written therein. And [N] indicates that the circuit area is not analyzed by the pitch. Although the embodiments of the present invention are disclosed as described above, it is not intended to limit the present invention, and those skilled in the art can make some updates and retouchings without departing from the spirit and scope of the present invention. The patent protection scope of the present invention is defined by the scope of the patent application attached to the specification. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system architecture diagram of the present invention; 14 1301203 FIG. 2 is a flow chart of the method of the present invention; FIG. 3 is a schematic diagram of the circuit design of the present invention. The test point configuration diagram of the present invention; FIG. 4B is a schematic diagram of the circuit area division of the present invention; FIG. 5 is a schematic diagram of the test point mark of the present invention; and FIG. 6 is a schematic diagram of the analysis result file format of the present invention. [Main component symbol description]
110 邏輯電路軟體 111 邏輯電路設定標案 112 檢修程序 120 點距分析程序 121 擷取程序 122 分析程序 123 檢視程序 130 點距資料庫 131 區域貧料庫 132 分析資料庫 300 檔案格式圖 401 測試點配置圖 402 區域劃分圖 500 標記圖 600 分析結果格式圖 15110 logic circuit software 111 logic circuit setting standard 112 inspection program 120 point distance analysis program 121 capture program 122 analysis program 123 view program 130 point distance database 131 area poor library 132 analysis database 300 file format map 401 test point configuration Figure 402 Area division diagram 500 Marking diagram 600 Analysis result format Figure 15