TWI300933B - Method of reducing settling time in flash memories and improved flash memory - Google Patents

Description

1300933 18451twf.doc/y IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a flash memory device and a method of reading data therefrom. [Prior Art] NAND-type EEPROM (Electrically Erasable and Editable Read-Only Memory) or Flash Memory has been developed for solid-state mass storage applications such as portable music players, mobile phones, and digital cameras. And it has been considered as a replacement for hard drives (HDDs). , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The parasitic capacitance and the word line to word line capacitance provide the Rc delay due to the selected word line. The highest power f of the unselected word line is the same. I am able to read accurately until the line of characters is dissipated. The voltage of this two cars. The age effect between the small word lines is particularly strong. For example, 'Chen's US Patent No. 6,291,297 (US '297) ==Describes the choice between the selected gate of the selected word line and the adjacent word line, the knife-gate flash memory crystal The manner in which this reference is made in the cell is fully incorporated herein. These RC delays provide the total access time from the flash memory storage unit. In general, the access time is about 10 勤 for a cell of less than 512 _, and 25 Μ for a value higher than 1 Gb. Although at least conceptually, metal shunts are so narrow 'doors', but because of the additional cost associated with them and the difficulty of providing shunt metal in narrow pitches, use 1300933 18451twf.doc/y metal shunts Generally not preferred. Therefore, there is still a need for an improved read flash memory memory, and from - flashing _ =: = = fast [invention] The present invention provides a "plant-on-fast method" in which - the word line is smashed In the data sub-line read operation, the method includes the following steps: after the - segment, the read operation is delayed by the - slave line voltage. 1 , 疋 兀 以 以 ... 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸 夸兀 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The unselected character i is: after the delay 岐, the selected character is biased with the selected word line voltage. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention are set forth in the preferred embodiments of the present invention, and in conjunction with the accompanying drawings. FIG. 1 shows a memory cell array. The circuit is only memory Zhao, which is formed on a wafer substrate. If the == operator will be compiled, Figure 1 is a NAND fast memory array

Circuit diagram of 1300933 18451twf.doc/y. Various components, such as column and row decoders, inductive circuits, and other control circuits, are not shown to avoid obscuring the disclosure of the present invention. However, these components are well known to those skilled in the art. An exemplary memory array is divided into a number of memory "blocks." Each block has a number of "pages,". A page has a lot of memory "cells," for example, a 1 Gb memory has 1 24 blocks, and one block has 64 pages. Each page has 2 K bytes (ie, 16 κ bits). A word line contains one or more pages. In the direction of the bit line, a cell string or two cell strings are provided for the block. A cell string has 16 bits, 32 bits or 64 bits. The memory array illustrated in Fig. 1 includes a plurality of parallel bit lines BL0, BL1, ···· to BL16383 in the illustrated embodiment, which are coupled to respective memory cells 'this memory cell is used in the memory array The individual bit lines in the middle are defined by the intersection of the word lines. In a preferred embodiment, although the other unit cell structures such as SONOS or split gate flash memory cells are covered, the individual unit cells are floating gates. Flash memory cell. Parallel word lines WL〇, WL1, WL2 · · · WL15 is formed on the substrate to form a control gate for individual flash memory cells. Select transistor and each bit line Associated with and coupled to signals SS and GS. Block selection signal BK is used to select a store The cell block, cs, represents the common source line. A cell string is connected to a bit line through the ss selection transistor on one side and connected to the cs through the GS transistor. During the data access, the global word is shared. The meta-line signals GWL0, GWL1, ···. to GWL15 pass 1300933 18451twf.doc/y The word line drive transistor 'transceives the word line WL〇 to WL15 respectively. The different types of memory cells have different materials. The condition of the 敎 敎 - - - - - - - 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从The higher bias voltage can be coupled to this H word H. The near-free mosquito bias must be dissipated before it can be accurately read from the selected word line. Figure 2 shows the word line of the 1 flash memory f column. Resistor-capacitor model. Specifically, ' @ 2 displays word line to character (four) combined capacitance (Ccoup), other parasitic capacitance (Cpar), and word line resistance (magic. For a 0·13 μιη transistor generation That is, for a transistor having a channel length of 〇13 _, the following conditions may exist: (1) Sub-line to word Line Coupling Capacitance (Ccoup): 〇·〇96ίΡ/cell; (11) Parasitic capacitance in a word line (Cpar): 0.064 fF/cell; • (111) total word line to word line coupling Capacitance (16384 cells): 1.57 pF ; (iv) Total parasitic capacitance · 1.05 pF ; (v) Word line width: 013 μπι ; (vi) Word line length (16 X 1024 χ 2 X 013 μηι · 4259 卿; (vii) Word line resistance (4259 μιη/0·13 μιη X 60) : = 2 X 1〇6 Ω, assuming that the word line is made of η+ polysilicon and its sheet resistance is 6 〇ohm ; and 1300933 1845 ltwf.doc/y (viii) character line RC (1.57 pF + 1·〇5 pF) x 2 χ ι〇6 Ω ·· 5 In a method of reading a conventional floating gate flash memory cell, the word line voltage of the selected word line is set to 〇V to distinguish between a programming state (a threshold voltage higher than 1 V) or an erase State (threshold voltage is below "V." Set the unselected word line to a higher voltage, such as 4 V. The voltage from the unbiased unselected word line of the higher bias is coupled to the selected word line and must It is dissipated before it can be read. Therefore, during the read cycle, # must provide sufficient tolerance to account for this settling time. - Similarly, when reading a separate gate such as the US '29^ Appropriate tolerances must also be provided during the other cell structure of the unit cell. During the reading of these split gates, the select gate of the memory cell is biased at approximately 4.6 V to serve as a transmission, electricity. Pass transistor. Select the word line at 1. 5 V bias and unselect the word line at 9 - bias. Each word line is in its _ with #^ select = pole. Select 4.5 on the gate V and 9 adjacent to the unselected word line; fit to the selected word line. In the unit cell structure, the word line and the selection The space is very narrow, for example - a layer having an effective oxide thickness of 14 〇 A. For this reason, the shank between the selected word line and the selected gate is particularly strong, and the coupling capacitance causes an increase in the settling time, and the reading is performed. It is necessary to take a review of '0'. Figure 3 - General description When reading the operation signal by this conventional technique, mark the different nodes along the word line of the - block memory block to test, for example, WL1B records close to f Crystal _ ^ material element 1 the beginning of the reference, WL1M refers to the polycrystalline element line wu

1300933 18451twf.doc/y WL1E refers to the beginning of the last eight WL2 character lines of the polycrystalline stone character line wu, L2B refers to the polycrystalline stone eve t ^ WL2E „ , WL: ^ It is convenient to see 'only ^ Character_Description. In material = On' Assume that the character "two offsets" is not selected during reading and that the meta-line is biased at li5V. In Figure 3, selected for reading, WL〇, WL1, and wu to muscle 5 were not selected. The sister selects the transistor block selection signal BK from its respective word line to simultaneously turn on each word line. The unselected word lines yL 〇, WL1 and wl3 to WL5 of this string are biased at the high voltage 'yarn 6 ¥. The 6 v bias is coupled from the adjacent unselected word "$ line WL1 and WL 3 to the selected word line WL 2, resulting in a peak of the voltage along the selected word line WL2. Additional time is allocated during the read cycle to Wait for WL2 to be set to its 15 V bias before attempting to read. This extra time provides sufficient tolerance to allow dissipation of the coupling voltage to allow accurate determination (g卩, read) of the read cell is in the programmed state Or erase the state. The simulation illustrates the effect of this improper coupling on the settling time of the selected word line. Figure 4 is a graph showing the effect of the coupling voltage on the settling time of the selected word line WL2. The narrow 200ASiO2 spacers are spaced apart from each other. The word line thickness is set to 0.2 μηη and the gate length is set to 0·13 μηη. Each word line has a 2048-bit cell or 32Κ F length, where F is The minimum size that can be photolithographically defined during the fabrication of the memory array, such as 0.13 μm. The bit line spacing (ie, bit 1300933 18451 twf.doc/y line width plus bit line to bit line spacing) is 〇·26 Ππι( , 2 F), and thus the word line length is 4259 μιη. The resistance of the word line is about 2 Μ Ω. The word line to word line coupling capacitance is 0.096 fp per side of the unit cell. The other parasitic capacitance is about every The cell is 0.064 fF. As can be seen from curve A of Figure 4, the unselected word line (WL1) is biased to a high voltage, for an analogy of 6 volts. Node WL1B rises rapidly to this high voltage, while WL1 The end node (WL1E) and the intermediate node (WL1M) have a certain delay in reaching a high bias voltage. As shown in the curve section B of Figure 4, the selected meridian WL2 is biased to a lower voltage 'here At 1.5 volts, the undetermined WL1 is simultaneously biased to a high voltage. The voltage at the start node WL2B of WL2 is quickly stabilized at 1.5 V because its W 蠡 is closest to the word line driver transistor. However, the word line The voltage at the intermediate node (WL2M) initially jumps to about 3 V due to the high voltage voltage coupling from the adjacent unselected word line (eg, WL1), and it slowly decays, reaching the selected word after about 16 ps. The 1.5 V bias voltage of the line. Similarly, the end node of the selected word line (WL2E) The voltage at the first jumps to about 3.6 V and takes a similar amount of time to set the selected word line bias to 1.25 V. A new method of reading the flash memory cell is proposed, which reduces The set time of the selected word line. The reading method is applicable to different flash memory cells, such as floating gates, split gates, SONOS, etc., which experience the setting of the time tolerance required to read data from the unit cell. Time. Figure 5 illustrates a portion of the new flash memory and its timing. 1300933 18451twf.doc/y

The new flash memory array includes a phase storage cell block having a plurality of reference word lines, and the reference block of the clothing w has the same characteristics (for example, a light capacitance, a parasitic band 2 and the day) The cell array shows only five word lines and resistors in the cell array block. An exemplary block shown includes sixteen character lines. Similarly, it is understood that Figure 1 is shown to include five word lines, but should include a sufficient number of t 4 blocks to reflect the coupling of the cell array blocks and the parasitic capacitance. Thus, the number of word lines provided in the 711 lines in the exact array block is the same, but == and crystal, in the exemplary embodiment between nine lines and ten_^ word lines. Again v, as described below, the reference block is used to provide - voltage ^ to chase, - select the word line (ie, selected for reading) ^

For comparison with the - reference voltage. This comparison result (10) = the start of the read voltage of the selected dice 4. Although the attenuation can be directly from the selected word line = monitoring 'but it is not the best choice compared to the provided - reference block, because j is in each block, the connection between each word line and the comparison circuit Instead of just the word line connections from the reference block. Select the word line of the memory cell array, such as WL2 of the cell array block for reading. Also select or specify a -word line from the reference block, such as RWL2. In comparison with the h5 V of the selected word line of the above-mentioned prior art (or other sub-line voltage), the reference parameter, 1|6 is biased with a lower voltage of 0 V, and combined with FIG. 4 above. As with the conventional techniques described for the un-elements, the remaining unselected reference character lines are biased at 6 $he is not selected for the word line voltage). The unselected word lines of the cell array block (ie, WL(), WL1, WL3, WL4) are biased with the same 12 1300933 18451 twf.doc/y voltage (ie, 6 V) that is not selected for the reference word line. The bias voltage (eg, 1·5 V) is initially biased at the selected word line, but initially biased with a pen voltage (eg, 0 V) that reads the voltage below the selected word line. The selected word line WL2 of the above-described unit cell array block is in an initial delay period (denoted as "D"). At this time, the voltage of the reference word line RWL2 is coupled by the adjacent unselected reference word line pulled to 6 V as described above. Similarly, the selected word line WL2 is coupled by a high voltage coupled to the adjacent word line. After the gas voltage at the selected reference word line RWL2 reaches a peak value, it attenuates the coupling voltage to 0 V, i.e., applies a ground voltage of 1 to RWL2. A similar attenuation occurs in the selected element line WL2 because the word line array block is ~ similarly constructed and biased. Since the power of the selected word line WL2 during this period is 〇V (relative to the 1. 5 V of the prior art), it is the farthest node (WL2E) of the farthest node (RWL2E) of the reference word line. Only coupled to a peak of 2.9 V (as seen in Figure 6), which is lower than the 3 6 φ V described above in connection with Figure 4. This new reading method is tested by the simulation method of the unit cell structure, as shown in Fig. 4. The above test results are shown in Figure 6. The curve portion (B) of Figure 6 shows the voltage at RWL2e coupled to a peak of about 2·9 V and then attenuated to 〇v. When the voltage of RWL2E approaches or reaches the voltage bias of 1·5 V of a selected word line in this embodiment, a control signal ACT (shown as curve (A)) is generated to trigger the voltage reading with the selected word line. Bias is applied to select word line WL2, i.e., the voltage bias is switched from 〇v to 15v. The 13 1300933 18451 twf.doc/y curve portion (c) of Fig. 6 shows the voltage switching at WL2 in response to the control signal ACT. In fact, the ACT money is used to control the gwl voltage in a manner well known to those skilled in the art, i.e., the gwL selected word line read voltage is switched from, for example, 〇v to 15 v. In this reading method, during the -first delay period D (between T1 and T2 in FIG. 5), the lower-lower sub-line is reduced by _, such as L5 V) This helps speed up along the selected word line, and the curtain is electrically subtracted at its farthest node WL2E'. In the described embodiment of the invention, it will be understood that the time spent by the farmer is to consume the voltage and voltage, since the reading operation should not be performed. After the net ΟV 1 ^ Λ7 ^ L is late and the switch power is switched from the point WL2B ·#, ΓΓ on the selected word line, the starting point of the selected word line is twice, and the speed is pulled to the required voltage. . When the voltage at node WL2E is set

At voltage, the voltage at node WL2M also rapidly increases to two V fast S == minutes (Q shows all nodes A/. of the selected word line recall. I.5 V selected word line bias voltage, all sections % That is, start the node deduction ~ "' point WL2E. In this pole "the middle Lang" point W^2M and the end node in about 7叩, compared with the 16模拟 shown in the entire simulation of Figure 4, After the force of 7 叩, all the nodes have selected the bias of the word line [m by delaying the yoghurt is #定~- 犄 between the slaves until the voltage along the word line, the coupling voltage of the end node of the sub-element Attenuation or base 1300933 18451twf.doc/y This attenuation is reduced (or 0V) between the selected word line bias voltage and the node voltage. This faster setup time greatly reduces read time. An access window required to store a cell of a selected word line. Figure 7 shows an embodiment of an exemplary circuit 1 for generating a control signal ACT. Figure 7 also shows a timing diagram of the circuit. Generally, the reset signal RST coupled to the PMOS transistor M1 is set to a low potential, and the PMOS transistor is engaged with Between the source voltage vcc and the nm〇S transistor M2. The circuit includes a comparator 12 having an input coupled to a reference voltage VR and coupled to a voltage at the node. The VR can be set to 1·5 V, or two biases Another trigger voltage of the voltage (ie, between the selected word line voltage and the unselected word bias voltage), and more preferably less than the peak value of the selected word line, and more Preferably, it is set to about the selected word line bias voltage. At the beginning, the electric charge is 0. In this miscellaneous piece, the ride (ουτ) is high. The output of the comparator 12 has a = ==: The edge map Tr4々~ The selected word is green, the sequence is not, and the RWL2E is high when the out is low, and the other voltages that are not in the VR.MWue or the ancient array/existence are high. The 3 2 = lightning loss _ tiger (10) becomes low. It becomes high. 〇 UT = i5sv discharges to the reference sign 〇υ τ;

pulse. Switching Trigger - Setting ACT to High pUL 1300933 18451 twf.doc / y In a consistent embodiment, positive edge trigger circuit 14 includes a delay chain 16 that includes a plurality of delay elements such as a countable number of φ inverted (four) 18. The positive edge trigger circuit 14 also includes a NAND gate 2A having a first input coupled to receive the output of the delay chain 16, and a second input coupled to receive the signal OUT. In operation, nand 2〇 produces a low output signal except when both inputs are high. Therefore, the signal from the inverted certificate 22 is high only when ^AND 20 produces a low output. The input of NAND 20 is high only when the signal 〇υτ switches from low to φ to 鬲 and the time that the low k number QUT passes through the delay element 16 is within ^. In a y exemplary embodiment, the delay is about 2 ns. * The output of the N^ND gate 20 is coupled to an inverter 22 which supplies a signal PUL to the NM0S transistor M2, when the transistor M2 is turned on,

• That is, when PUL is high and RST is high, the NMOS transistor in turn transmits signal PUL to latch circuit 24. In an embodiment, the latch circuit 24 includes a pair of inverters 26, 28, the output of which is coupled to the input of the inverter 28, and the output of the inverter 28 is coupled to the inverter 26. Input. The latch circuit 24 is configured to operate and maintain the enable output of the positive edge trigger circuit 14 for subsequent use as described above. After reading, a new command (ie, read, write, or erase command) will be entered. When a new command is entered, the RST is started to reset the act. The above described readout method is most effective in flash memory arrays that utilize only a single driver transistor, which is typically placed at the start node WLB closest to the character 1300933 18451 twf.doc/y line. If a drive transistor is present, the voltage at the node that takes the longest to dissipate the engagement voltage can be prioritized. Typically, this node will be the node farthest from the drive transistor. If = two driver transistors are used, each at each end of the respective word line, then the voltage of the word line will be more stable. However, the use of more than one driver transistor is generally undesirable for size, cost, complexity, and/or power considerations. However, even if the flash memory array utilizes two driver transistors per word line, the method described in this article can be used to further improve setup time. In this embodiment, the intermediate node of the selected word line is preferably used as the input to the comparator 12 of the control signal k-generation circuit 10. Uyr - although the above described read-and-take method has been described in connection with a read protocol, wherein the bias voltage is set to a positive voltage, such as 1·5 V, at the selected word line, and Set it to a higher voltage, such as 6 V, at the selected word line, but the method is not so limited. For example, for a standard floating gate flash memory cell, wherein the read condition is 0 V at the selected word line and 4 ν at the unselected word line, initially The selected word line is biased to a negative voltage until the trigger signal ACT, such as when the reference word line is attenuated to 〇V. Correspondingly, the reference voltage VR of the circuit of FIG. 7 is set. Although the new reading method has been described above with reference to the reading conditions for a particular class of flashing cells, those skilled in the art. It will be appreciated that the method can be generally applied to any of the following flash phase memory cell junctions 17 1300933 18451 twf. doc / y construction, which is not (4) character phase word line coupling, and the towel is selected as 6 words 兀The line has a bias voltage different from the unselected word line bias voltage, although the invention has been described in terms of illustrative embodiments, it is not limited thereto. Rather, the appended claims are to be construed as broadly construed and construed in the claims of the invention BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings illustrate preferred embodiments of the present invention and other aspects of the present disclosure, wherein: FIG. 1 is a circuit diagram of a portion of a fast memory having a plurality of NANDf memory cells. ^体5己明. Figure 2 is a diagram showing the capacitance and resistance inherent in the flash memory of Figure 1. Fig. 3 is a view showing a conventional technique reading condition of a flash memory device. Fig. 4 is a view showing a setting condition of a different node using the reading condition of Fig. 3. An example of the _flash condition according to the present invention is shown in the scorpion I line. 1 Beck and condition, display along the selected character line Figure 2 === simulation diagram of the set time of the same Thunder node. Circuit diagram of the circuit-embodiment. [Description of main component symbols] 1300933 18451twf.doc/y BLO, BL1, ... BL16383: Bit lines WLO, WL1, WL2 ... WL15: Word line SS, GS: Signal BK: Block selection signal CS: Common source Lines GWLO, GWL1, . . . GWL15: Co-sliding word line signal Ccoup: Engaged capacitance φ Cpar: Parasitic capacitance WL1B: The closest starting portion of the driving transistor $polycrystalline word line WL1 WL1M: refers to the polycrystalline word line WL1 The middle portion 蠡, WL1E · refers to the end portion WL2B of the polysilicon character line WL1: the beginning portion WL2M of the polycrystalline word line WL2 closest to the driving transistor: the middle portion φ WL2E of the polycrystalline word line WL2: refers to the polycrystalline word End portion T1 of the element line WL2: time at which the start of the read operation RWL0 to RWL4: reference block word line D: initial delay period _ RWL1B: node RWL1M from the start of the reference word line RWL1: intermediate with the reference word line RWL1 Node RWL1E: node RWL2B farthest from the reference word line RWL1: node 19 with the start of the reference word line RWL2 1300933 18451twf.doc/y RWL2M: node RWL2E and reference character in the middle of the reference word line RWL2 The farthest node of line RWL2 ACT: control signal 10: an exemplary circuit for generating a control signal ACT

Ml : PMOS transistor M2 : NMOS transistor 々

Vcc : power supply voltage RST : reset signal 12 · comparator y : VR : reference voltage OUT : output of comparator 12 / -tA Qin 14 : trigger circuit PUL : output of trigger circuit 16: delay chain 18 : inverter 20 : NAND gate 22: inverter 24: latch circuit 26, 28: inverter 20

Claims (1)

1300933 18451twfl.doc/006 96_8_14 D, T砑 search range: ι · A method of biasing word lines in a flash memory array, i select a number of lines selected for use in data access during the first reading The method comprises the steps of: drinking an unselected word line voltage biased unselected word line; delaying a delay period; The read time period reads, by the selected word line voltage, the selected word line to perform the read operation. 2. The method of biasing a word in a flash memory array as described in claim i, wherein the unselected word line voltage is greater than the selected word line voltage to perform the Read operation. 3. The method of biasing a word line in a flash memory array as described in the above-mentioned item, wherein the step further comprises generating a control signal to trigger biasing of the selected word line voltage Step 4 of selecting the selected character line. If the method of applying the bias word in the (4) memory array as described in item 3 of the full-time application, the control signal rib should be - the line voltage. < 5. The method of controlling a bias word in a flash memory array according to the fourth aspect of the patent, wherein the controlling the signal generating step comprises: comparing the voltage of the reference character line with a reference voltage; providing the comparison result to a positive edge trigger circuit; and latching an output of the positive edge trigger circuit. 6. As described in the first paragraph of the patent application, the -_ memory array 21 1300933 l8451twfl.d〇c/〇〇6 96-8-14 A method of biasing a word line in a column, further comprising the steps of: providing a reference memory cell array comprising a plurality of reference word lines; wherein the unselected word line voltage is not selected a reference word line waiting for a voltage at a node on a selected reference word line to drop to a reference voltage; and after the voltage reaches the reference voltage, generating a control signal to trigger a voltage offset of the selected word line Press the selected word line. 7. A method of biasing a word line in a flash memory array as described in claim 6 wherein said selected reference word line is driven by a drive transistor, and wherein said node is remote The driving transistor, the method further comprising the step of comparing the node voltage with the reference voltage. 8. A method of biasing word lines in a flash memory array as described in claim 6 wherein said selected reference sub-line and selected word line are maintained during said delay period At a voltage lower than the voltage of the image. 9. The method of biasing word lines in a flash memory array as recited in claim 1, wherein a voltage from at least some of said unselected word lines is coupled to said selected word line, Wherein the delay period corresponds to a time taken for the coupling voltage at the selected word line to drop to a reference voltage, the method further comprising generating a control signal after the delay period to trigger The step of biasing the selected word line voltage to the selected word line. 22 1300933 - 18451twfl .doc/006 96-8-14 10 - A flash memory device, comprising: at least one memory block comprising a plurality of word lines; and a bias circuit for using an unselected word line The unselected word line voltage biases the word line and biases the selected word line with a selected word line voltage to perform an f-buy operation, wherein during the read operation, After a delay period from the unselected word line voltage biasing the unselected word line, the selected word line is biased with the selected word line voltage. 11. The flash memory emplacement of claim 10, further comprising means for generating a second retort after the delay period to trigger biasing the selected word line. Work, straw 12, as described in the patent application scope, the flash memory is set to 2, wherein the unselected word line voltage is greater than the selected word line partial pressure 13. As described in the scope of claim U The control signal generating means includes: "a clothing thief for comparing a reference voltage with a detection voltage. - a positive edge trigger circuit responsive to the comparator - wheel-out latch circuit, In response to the positive edge trigger circuit - the wheeled out and 14 · the flashing case body as described in claim 13 of the patent scope, the further step comprises - a reference memory block comprising a plurality of 侔 = 兀 line Wherein the control signal generates a component response - test = the voltage detected by the body block. 23 I30093J twfld〇c/〇〇6 96-8-14 15·If the scope of patent application is one, which comes from at least some of the above: the flash memory describes the selected character line, and the selected character is The voltage of the line is coupled to the method of biasing the word magnetic in the selected array of *-/flash bodies, the method comprising: for reading during the lean material access, the second word, the selected word field voltage Biasing unselected word line; - biasing said selected word at a first voltage of a reference voltage, said delay period corresponding to a selected point of said selected word line falling to said reference voltage Time, the reference voltage is greater than the first voltage, and less than the unselected word line voltage; the voltage, after the reference voltage, generates a control signal to trigger a selected word line voltage Biasing the selected word line to perform the read operation, the selected word line voltage being greater than the first voltage, ϋ less than the unselected word line voltage; and responsive to the control signal The selected word line voltage biases the selected word line. 17. A method of biasing a word line in a flash memory array as described in claim 6 wherein said control signal generating step comprises: providing a reference store comprising a plurality of reference word lines Cell block ·, 24 1300933 18451 twfl .doc/006 曰 曰 替换 替换 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Voltage and the reference voltage. 2. The method for applying a dusty word line in a fast array according to claim 17 of the patent scope, the further comprising the steps of: providing a comparison result by the body direction = positive edge trigger circuit; and signal weight lock The output of the __ circuit is provided to provide a voltage coupling of the bias line in the control array to a essay to lose a_ & 疋 考 考 兀 检测 检测 检测 检测 检测 检测 检测 检测A method of selecting a reference ridge, as described in claim 19, in the method of selecting a identifiable element line in the printed body, wherein during the delay period, and said selected character line Maintaining the reference voltage in the first power jack is substantially equal to the selected word line electric grinder. 25