TWI394461B - Image deblocking filter and image processing device utilizing the same - Google Patents

Description

Image deblocking filter and image processing device

The present invention relates to image processing technology, and in particular to a shadow block filter and an image processing apparatus using the image deblocking filter.

The current video coding technology standard generally treats a video frame as a combination of video blocks, and each block is an intra frame code or an inter frame code. The basic unit. For example, the MPEG-4 standard developed by the Moving Picture Experts Group (MPEG) divides video frames into macroblocks (Macroblock). Different standard technical aids for different sizes of video blocks. The H.264 standard supports video blocks of 16x16, 16x8, 8x16, 8x8, 8x4, 4x8, and 4x4 pixels.

In-frame or inter-frame coding based on video blocks, although using video frames in temporal and spatial similarity to obtain high compression ratios, causes block-like discontinuities in the boundaries between blocks in the video sequence. . Different video coding techniques, such as H.264, VC-1, and MPEG2, use different deblocking methods to mitigate the above-mentioned blockiness. A variety of deblocking formulas are also used in a single video encoding technique.

Different deblocking methods are usually designed with a dedicated deblocking circuit. Integrating these proprietary circuits into one device to support different video coding methods may complicate circuit design and increase the difficulty of circuit miniaturization. When the device wants to support a new deblocking method, the circuit design is necessary. Change again. It is more flexible to use a general purpose processor to perform different video coding methods, but it is relatively inefficient.

In order to solve the above problems, the present invention provides an image deblocking filter, comprising: a command memory, an execution unit, and a decision unit. The instruction memory is configured to store a plurality of instructions, wherein the first one of the plurality of instructions represents three arithmetic operations and two bit operations acting on three variable operands and two constant operands. The execution unit is configured to execute an instruction stored in the instruction memory and includes a first arithmetic logic unit, wherein the first arithmetic logic unit is configured to execute the first instruction in a single frequency cycle. The determining unit is configured to execute an instruction stored in the instruction memory, thereby determining a first extraction path and a second extraction for extracting a part of the plurality of instructions from the instruction memory to the execution unit One of the extraction paths of the path. When the execution unit executes the instruction according to the first extraction path or the second extraction path, respectively performing a deblocking formula in the first or second image compression standard, and the determined extraction path includes the The first instruction, wherein when the execution unit executes the first instruction, instructing the image deblocking filter to perform the three arithmetic operations and two bit operations, comprising: a left shift operation as a first bit operation Implementing a first variable operation element; performing a first addition operation as a first arithmetic operation, performing the first variable operation element and a second variable operation element after the left shift; and the mode according to the first instruction Setting a second addition operation or a subtraction operation as a second arithmetic operation, wherein the second addition operation includes a result of the first addition operation plus a third variable operation element, and the subtraction operation includes the first addition Subtracting the third variable operation element from the result of the operation; performing a third addition operation as a third addition operation on the second arithmetic operation And a first constant operation element; and a right shift operation as a second bit operation, shifting the result of the third addition operation to the right according to the value of a second constant operation element.

Embodiments of the present invention also provide an image processing apparatus including an image deblocking filter, the image deblocking filter including a command memory, an execution unit, and a decision unit. The instruction memory is configured to store a plurality of instructions, and the first one of the plurality of instructions represents three arithmetic operations and two bit operations acting on three variable operands and two constant operands. The execution unit is configured to execute an instruction stored in the instruction memory, and includes a first arithmetic logic unit, the first arithmetic logic unit configured to execute the first instruction in a single frequency cycle. The determining unit is configured to execute an instruction stored in the instruction memory, thereby determining a first extraction path and a second extraction for extracting a part of the plurality of instructions from the instruction memory to the execution unit One of the extraction paths of the path. When the execution unit executes the instruction according to the first extraction path or the second extraction path, respectively performing a deblocking formula in the first or second image compression standard, and the determined extraction path includes the The first instruction, wherein when the execution unit executes the first instruction, instructing the image deblocking filter to perform the three arithmetic operations and two bit operations, comprising: a left shift operation as a first bit operation Implementing a first variable operation element; performing a first addition operation as a first arithmetic operation, performing the first variable operation element and a second variable operation element after the left shift; and the mode according to the first instruction Setting a second addition operation or a subtraction operation as a second arithmetic operation, wherein the second addition operation includes a result of the first addition operation plus a third variable operation element, and the subtraction operation includes the first addition Subtracting the third variable operator from the result of the operation; a third addition operation as a third arithmetic operation, a result of the second arithmetic operation and a first constant operation element; and a right shift operation as a second bit operation, according to a second constant operation The value of the element shifts the result of the third addition described above to the right.

100, 101‧‧‧ image processing device

151‧‧‧ processor

152‧‧‧ main memory

153‧‧‧ Non-volatile memory

154‧‧‧Many storage devices

155‧‧‧Content Protection Unit

156‧‧‧ demodulator

157‧‧‧Tuner

158‧‧‧Power supply

159‧‧‧Crystal Oscillator

160‧‧‧I/O unit

161‧‧‧Optical output unit

162‧‧‧Video output unit

163‧‧‧Antenna

164‧‧‧埠

165, 200‧‧‧ image deblocking filter

170‧‧‧Network interface

171‧‧‧Network

210‧‧‧Internal memory

211‧‧‧Configuration register

212‧‧‧Main finite state machine

213‧‧‧Dynamic Link Library FSM

214‧‧‧ instruction memory

215‧‧‧Information loaded into FSM

216‧‧‧Write back to FSM

217‧‧•Video Decoder

218‧‧‧ external memory

220‧‧‧Execution unit

230‧‧‧Image data

220‧‧‧Execution unit

300‧‧‧ pixels loaded into FSM

310‧‧‧Decision level

312‧‧‧Mode Register

313, 323, 333‧‧‧ pixel register

314, 324, 334‧‧‧ extraction level

315, 325, 335‧‧ ‧ decoding level

316, 326, 336 ‧ ‧ executive level

322, 332‧‧‧ Path register

320‧‧‧ computing level

330‧‧‧ computing level

340‧‧‧pixel update FSM

351-353‧‧‧ memory area

B1-B24‧‧‧ Block

51-54‧‧‧ edge

55‧‧‧Macro Block

56‧‧‧Area

50‧‧‧ pixel unit

L00-L04‧‧‧ Directive

L10-L14‧‧‧ Directive

L20-L24‧‧‧ Directive

L30-L34‧‧‧ Directive

41, 42‧‧ ‧ busbar

3261, 3262‧‧‧Arithmetic Logic Unit

3263‧‧‧Multiplexer

3264‧‧‧pixel transfer circuit

51-56‧‧‧ register

61-65‧‧‧Operating subcircuit

600‧‧‧ part of the circuit of the arithmetic logic unit

FIG. 1A is a block diagram showing an embodiment of an image processing apparatus 100 including an image deblocking filter 165.

1B is a block diagram showing the structure of a second embodiment of an image processing apparatus that receives digital content from a network.

2 is a block diagram of an embodiment of a shadow deblocking filter; FIG. 3 is a block diagram of an embodiment of an execution unit of a shadow deblocking filter; FIG. 4 is a schematic diagram of an image; Figure 9 shows a schematic diagram of the operational level structure; Figure 10 shows a schematic diagram of the arithmetic logic unit; Figure 11 shows the instruction set of the decision stage; and Figure 12 shows the instruction set of the arithmetic stage.

An embodiment of an image deblocking filter and an image processing apparatus using the same is described as follows:

1. System Overview

The image deblocking filter disclosed in the present invention can be implemented in various image processing devices. Such as CD player, multimedia player, digital camera, set-top box, personal digital assistant (PDA), laptop or desktop computer or any device with image processing capabilities, such as TV, mobile Telephone or video conferencing device, etc. FIG. 1A is a block diagram showing the structure of an image processing apparatus 100 including an image deblocking filter 165.

1.1 Embodiment of Image Processing Apparatus

The image deblocking filter 165 is integrated in the central processing unit of the image processing apparatus 100, that is, the processor 151. The processor 151 may be packaged from a single wafer or a multi-chip, and the multi-wafer may be connected by a bus bar. The power supply 158 supplies power to each element in the image processing apparatus 100. The quartz oscillator 159 provides a clock signal to the processor 151 and other components in the image processing device 100. FIG. 1A shows the connection relationship of the components in the image processing apparatus 100, and the connection is permeable to the serial bus bar or the parallel bus bar. The input and output device includes a control button, a seven-segment display, and an infrared receiver or transceiver that communicates with the remote controller. One of the plurality 164 is coupled to an external computer for debugging the image processing apparatus 100.埠164 may be in accordance with the Electronic Industries Association (EIA) Recommendation No. 232 (Recommended Standard-232, referred to as RS-232) and/or Recommendation No. 11 (Recommended Standard-11, Referred to as RS-11), the physical connection port, Serial ATA (SATA) and/or High Definition Multimedia Interface (HDMI). The non-volatile memory 153 stores operating systems and applications executed by the processor 151. The processor 151 loads the running program and data to the main memory 152 and stores the digital content in the mass storage device 154. The main memory 152 may be a random access memory (RAM), such as a static random access memory (SRAM) or a dynamic random access memory (Dynamic RAM, DRAM for short). ). The non-volatile memory 153 may be an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only) Memory, referred to as EEPROM), such as reverse (NOR) flash memory or reverse (NAND) flash memory. The content protection unit 155 provides access control for the digital content generated by the image processing apparatus 100. The content protection unit 155 includes the memory and necessary devices required to implement a universal interface for digital video broadcasting (DVB-CI) and/or conditional access (DVB-CA). The image processing device 100 can obtain digital content from the digital signals transmitted from the antenna 165, the tuner 157, and the demodulator 156. FIG. 1B shows another embodiment in which the image processing apparatus 101 acquires digital content from a network such as the Internet through a network access interface. The video output unit 162 includes a filter and an amplifier for filtering and amplifying the video signal output by the processor 151. The audio output unit 161 includes a digital analog converter for converting the audio signal output by the processor 151 from a digital format to an analog format.

1.2 embodiment of image deblocking filter

2 is a block diagram showing the structure of an image deblocking filter 200 of the embodiment of the image deblocking filter 165 of FIGS. 1A and 1B. The constituent elements of the image deblocking filter 200 in Fig. 2 can be constituted by circuits. The image deblocking filter 200 is connected to the video decoder 217 and the external memory 218. The video decoder 217 is used for decoding images or video in various formats, such as MPEG-1, MPEG-2, and MPEG-4 developed by MPEG, and International Telecommunications Union-telecommunication (Telecommunication). H.263 and H.264 developed by ITU-T), or QuickTime ^TM developed by Apple Computer Inc. of the United States, or VC-1 technology developed by Microsoft Corporation of the United States. The video decoder 217 can write the set value in the configuration register 211, and the main finite state machine (FSM) 212 controls the image solution according to the set value in the configuration register 211. The operations of the block filter 200. The external memory 218 may include a main memory 152 or a cache memory having a memory capacity of the internal memory 210. A preferred embodiment of the internal memory 210 described above includes an SRAM. The external memory 218 stores the deblocking command and the image data decoded by the decoder 217. The dynamic link library (DLL) FSM 213 loads the deblocking instruction from the external memory 218 to the instruction memory 214, and the data loading FSM loads the image data from the external memory 218 to the internal memory 210. The execution unit 220 obtains the deblocking instruction from the instruction memory 214, acquires the image data from the internal memory 210, executes and applies the acquired instruction to the acquired image data to perform deblocking, and stores the decompressed image data in the internal memory. Body 210. The FSM 216 is written back to store the decompressed image data to the external memory 218.

2 image deblocking filter operation example

FIG. 3 shows an embodiment of execution unit 220. The constituent elements of the execution unit 200 in FIG. 3 may be composed of circuits. The above instruction memory 214 may include memory regions 351-353. After the decoder 217 completes decoding of a piece of image data (for example, a still image, a video frame, or a macroblock), the image data is output to the external memory 218, and the main FSM 212 determines the format of the image data, and A corresponding register setting value suitable for the deblocking mode of the format is written in the configuration register 211 described above. The data loading FSM 215 loads the decoded image data into the internal memory 210 to become the image data 230.

A deblocking mode includes complex deblocking decisions, and each deblocking decision is associated with one of the complex decoding formulas. Each deblocking decision is made up of a complex decision level instruction stored in the memory region 351, and each deblocking formula is composed of complex arithmetic level instructions of the memory regions 352 and 353. The pixel loading FSM 300 writes a register setting value corresponding to the deblocking mode in the mode register 312, and loads the image data 230 from the internal memory 210 to the pixel register 313. In the decision stage 310, the fetch stage 314 fetches the decision level instruction from the memory area 351 based on the set value in the mode register 302, the decode stage 315 decodes and the execution stage 316 executes the above-determined decision level instruction to determine a An instruction fetch path corresponding to the deblocking formula is written in the path register, for example, the path register 322, in the path register, corresponding to the determined extraction path. And 332. The register value of the path register 323 described above can be forwarded to the path register 333.

The pixel data in the pixel register 313 can be transferred to the pixel register 323. In operation stage 320, extraction stage 324 retrieves the operation level instructions from memory area 352 based on the set values in path register 322 described above, decoding stage 325 decodes and execution stage 326 executes the above-derived operation level instructions to generate and The intermediate data or the deblocked pixel values are stored in the pixel register 323. The pixel data in the pixel register 323 can be transferred to the pixel register 333. The set values in the path register 322 described above can be forwarded to the path register 332. Similarly, in the operation stage 330, the extraction stage 334 retrieves the operation level instruction from the memory area 353 based on the set value in the path register 332, the decoding stage 335 decodes and the execution stage 336 executes the above-mentioned acquired operation level instruction. To generate and store intermediate data or deblocked pixel values in pixel register 333. The set value of the path register 332 can be received from the output of the execution stage 316 of the decision stage 310 or the upper path register 322.

The above-described extraction stage 324, decoding stage 325, and execution stage 326 form three stages of pipeline construction in the above-described arithmetic stage 320. The path register 322 and the pixel register 323 described above may be included in the extraction stage 324. The above-described decoding stage 325 and the above-described execution stage 326 can be integrated into a single stage that can perform instruction decoding and execution in a single clock cycle. Similarly, the above-described extraction stage 334, decoding stage 335, and execution stage 336 form three stages of pipeline construction in the above-described arithmetic stage 330. The path register 332 and the pixel register 333 described above may be included in the extraction stage 334. The above-described decoding stage 335 and the above-described execution stage 336 can be integrated into a single stage that can complete instruction decoding and execution in a single clock cycle.

The pixel update FSM 340 stores the deblocked pixel values in the internal memory 210 to update the image material 230. The write-back FSM 216 transmits and stores the updated image data 230 to the external memory 218.

The instruction set of the image deblocking filter 220 described above will be explained in the following paragraphs. Figure 11 shows the decision level instruction. The text in the "Description" column uses a pseudo code to describe the operation when the operation level executes the individual instructions.

Each instruction in the instructions SAC, APR, and MFA is accompanied by a mode setting bit, where a bit specifies that the instruction belongs to dual or non-dual mode, and another bit specifies that the instruction is an end instruction (end) or Non-end instruction (not-end). When the operation stage executes an instruction in the dual mode, the instruction directs the operation stage to perform a single instruction stream and multiple data streams (SIMD) operation. When the operation stage executes the end instruction, the end instruction instructs the operation stage to move the set of instructions after the end instruction from the above operation stage to another operation stage.

R1, R2, R3, TP and TF are register names, and A, A1 and A2 are variables, called constant operands. F1-F4 is a two-state flag. The symbol "=" represents a designation or assignment operation, that is, a variable or a register that specifies the value to the right of the symbol "=" to the left of the symbol "=". "TF=(| R1-R2 |<R3)?1:0" means that if (| R1-R2 |<R3) is true, the value of TF is specified as 1 when executing the SAC instruction, if (| R1-R2 |<R3) is not true, the value of TF is specified as 0. When the operation stage executes the JMP instruction, it switches to the address execution instruction pointed to by the scratchpad A only when the flag F1 is true. When the operation stage executes the APR instruction, when the flag F1 is true, the value of A1 is assigned to the temporary register TP, and when the flag F1 is not true, the value of A2 is assigned to the temporary register TP. The symbol "&" represents a logical AND operation. Figure 12 shows the computed level instruction set.

TR is the name of the scratchpad. A and S are variables and are called constant arithmetic elements. The above symbols "<<" and ">>" represent the left and right shift operations of the bit, respectively. Specifically, x is indicated by the real variable x and the positive integer variable y ((y denotes that x is the complement of two and shifts y bit to the right. Shift to the right and fill in the most significant bit (Most Significant Bit, The value of MSB) should be the same as the value of the most significant bit before x-displacement. Similarly, x((y means that x is the complement of two and shifts y-bit to the left. After shifting to the left, the least significant bit is filled in. The value of (Least Significant Bit, LSB for short) should be 0. The ASH instruction is accompanied by a mode setting bit to specify the operation between the registers R2 and R3. When the above mode setting bit is used to specify the addition operation "+" When the ASH command indicates TR=[(R1<<1)+R2+R3+A]>>S. When the mode setting bit is used to specify the subtraction "-", the ASH command indicates TR=[( R1<<1)+R2-R3+A]>>S. The above function Clip( ) is called a trimming function and is defined as follows:

The above variables b and c are the lower limit and the upper limit for cutting the variable a, respectively. When the execution stage executes the trimming instruction, such as CLP or UCP, the trimming instruction instructs the image deblocking filter to perform a trimming operation to limit the value of the operand of the instruction to the upper and lower limits.

FIG. 4 shows the image block of the image data 230 and the edge between the blocks. The image data 230 includes a region 56, and the region 56 includes blocks B17-B24 and macroblocks 55 formed by blocks B1-B16. As illustrated, blocks B1-B24 each contain 16 pixels, which are represented by squares in the figure. The arrangement of the blocks and pixels shown in FIG. 4 shows their arrangement in the image data 230. The data loading FSM 215 loads the image data 230 from the external memory 218 to the internal memory 210, and the pixel loading FSM 300 loads a unit pixel set of the image data 230 into the pixel register 313 for the image 230. Edge deblocking. For example, pixel loading FSM 300 loads unit pixel set 50 into pixel register 313, including pixels P0-P3 of block B17 and pixels Q0-Q3 of block B1. The arrows 51-54 represent the horizontal edges of the macro block 55, respectively. The edge represented by the arrow contains two columns on either side of the arrow. For example, the edge represented by arrow 51 includes blocks B1-B4 and B17-B20. When the deblocking of the edge represented by the arrow 51 is performed, the pixel loading FSM 300 can load the 8 pixels to the right of the pixels P0-P3 and Q0-Q3 as the next unit of the subsequent deblocking operation. Pixel collection. So on and so forth.

The deblocking operation may be applied to the luminance (luma) and chroma (chroma) of the unit pixel set 50, respectively. The deblocking order of the vertical and horizontal edges of the image has been described in each image coding standard, and therefore will not be described herein.

2.1 Example 1 of the execution instruction

Deblocking formulas for various different instruction encoding standards are represented by different instruction fetch paths (or called instruction execution paths), and each fetch path contains complex arithmetic level instructions that are extracted to the arithmetic stage. The decision stage 310 described above executes an instruction to output the above extracted path. For example, the decision stage 310 outputs an extraction path corresponding to the following deblocking formula: P1bSLT4(P2, P1, P0, Q0)=P1+Clip3(-TC0, TC0, (P2+((P0+Q0+1)>> 1)-(P1<<1))>>1) (2)

Where TC0 is a variable. The function Clip3(x, y, z) in equation (2) is defined in H.264 as:

Equation (2) is a formula used to calculate the pixel P1 value in the H.264 standard. The decision stage 310 executes the decision level instruction corresponding to the deblocking strategy, so that the boundary strength and the sampling flag (SF) of each edge of the image data 230 are used to determine the command L00-L04. Extract the path. The above SF may contain the flag FilterSamplesFlag defined in the H.264 standard. Figure 5 shows the above extraction path containing instructions L00-L04. The annotations of the above instructions L00-L04 are also displayed after the symbol "//" below each instruction, where W, X, Y and Z are variables.

The above-described extraction stage 324 sequentially extracts the above-described instructions L00-L04 to the above-described decoding stage 325. The decoding stage 325 and the execution stage 326 respectively decode and execute the above instructions L00-L04. The instruction L00 represents X=-P1, and the result of X=-P1 is output after being executed. The instruction L01 represents Y=(P0+Q0+1)>>1, and the result of Y=(P0+Q0+1)>>1 is output after being executed. The instruction L02 represents Z=[(-P1)<<1+Y+P2]>>1, and the result of Z=[(-P1)<<1+Y+P2]>>1 is output after being executed. The instruction L03 represents W=Clip(Z, -TC0, TC0), and the result of W=Clip(Z, -TC0, TC0) is output after being executed. After the instruction L04 is executed, the result of the formula (2) is output to update the pixel P1.

Each execution level, such as the execution levels 326 and 336 described above, includes two arithmetic logic units (ALUs). When an instruction represents a bit in its dual mode, the decoding stage (eg, decoding stage 325 or 335) generates two instances of the instruction when decoding the instruction, and the above two instances of the instruction are The two sets of operand sets corresponding to the two instances are output to the above-mentioned execution stage to which the decoding stage is connected. A multiplexer can select and output two sets of pixel sets from the pixel register as the set of two sets of operands to the two ALUs. The two ALUs in the execution stage respectively perform the above two instances of the above instructions on the two sets of operand sets in the same clock cycle. The pixels included in one of the above two sets of operand sets are symmetric to the other set of pixels.

For example, as shown in FIG. 9, the above-described execution stage 326 includes ALUs 3261 and 3262. When the above instruction L00 in which the bit of the dual mode is in the actuated state is decoded, the above decoding stage 325 generates and outputs two instances of the instruction L00 to the above-described execution stage 326. The multiplexer 3263 outputs the pixels P1 and Q1 to the ALUs 3261 and 3262 in the pixel register, respectively. As shown in FIG. 6, the decoding stage 325 generates the instruction L10 as an example of the copy instruction of the instruction L00, wherein the operation of the pixel Q1 and the instruction L00 of the operation element of the instruction L10 in the geometric arrangement of the pixel unit 50 with reference to the above-mentioned arrow 51. The pixel P1 of the element is symmetrical. The above ALU 3261 in the above execution stage 326 is executed on the operation unit P1 in one clock cycle. The row instruction L00, and the ALU 3262 described above, executes the instruction L10 on the operand Q1 in the same clock cycle, wherein the instruction L10 is a copy instance of the instruction L00, and the pixel Q1 is symmetric pixel P1. Similarly, the above decoding stage 325 generates the instructions L11, L12, L13, and L14 as the copy instruction instances of the instructions L01, L02, L03, and L04, and the ALU 3262 executes the above-described copy instruction instance.

Figure 10 shows a partial structural diagram of the ALU in the execution stage. The arrows in Fig. 10 show the connection relationship of the respective elements therein. Circuit 600 may be an implementation of any one of execution stages 320 or 330 to execute an ASH instruction in a single clock cycle. The registers 51-55 store the operands R1, R2, R3, A and S of the ASH instruction, respectively. The arithmetic sub-circuit 61 shifts the value of the register 51 to the left by one bit, and outputs the result of the left shift. The arithmetic sub-circuit 62 performs an addition operation on the output of the arithmetic sub-circuit 61 and the value of the register 52, and outputs the result of the above-described addition to the arithmetic sub-circuit 63. The register 56 stores an instruction-decoded mode setting bit for specifying addition or subtraction between the registers R2 and R3. The arithmetic sub-circuit 63 performs an addition or subtraction operation on the received arithmetic element based on the bit value stored in the temporary memory 56, and outputs the operation result. The arithmetic sub-circuit 64 performs an addition operation on the output of the arithmetic sub-circuit 63 and the value of the register 54, and outputs the result of the above-described addition to the arithmetic sub-circuit 65. The arithmetic sub-circuit 65 performs a right shift on the output of the arithmetic sub-circuit 64 in accordance with the number specified by the value of the register 55, and outputs the result of the right shift.

When the decoding mode setting bit of an instruction indicates that the instruction is an end instruction, the decoding stage 325 notifies the extraction stage 334 instead of the extraction stage 324 to acquire a set of instructions after the end instruction. The decode stage 325 can move the register set value in the path register 322 to the path register 32 to complete the notification job. In addition, as shown in FIG. 9, the pixel transfer circuit 3264 transfers pixels from the pixel buffer 323 to the pixel register 333 in response to the set bit of the end command transmitted in the bus bar 41. The above-described decoding stage 335 and the above-described execution stage 336 respectively decode and execute the above-described instruction set, thereby implementing a pipeline execution framework between execution stages. For example, the decode stage 325 described above can sequentially decode the instructions in FIG. 7, from the first instruction to the last instruction. When decoding to the end finger When the mode setting bit is the command L22 of the actuated state, the decoding stage 325 notifies the fetching stage 324 not to acquire the command L23-24 after the command L22, and notifies the fetching stage 334 to acquire the command L23-24. The above decoding stage 335 and execution stage 336 respectively decode and execute the above-described instruction L23-24. The control circuit 3265, under the control of the control signal in the bus bar 42, activates the pixel data output by the execution stage 326 to be written back to the respective registers in the pixel register 323.

2.2 Example 2 of the execution instruction

The VC-1 standard also utilizes various formulas for deblocking, including: a0=(2×(p3-p6)-5×(p4-p5)+4)>>3 (4)

A1=(2×(p1-p4)-5×(p2-p3)+4)>>3 (5)

A2=(2×(p5-p8)-5×(p6-p7)+4)>>3 (6)

The above p1-p8 are pixel values, which may be pixel brightness or chroma. For example, the decision stage 310 outputs the corresponding deblocking formula (4). The execution path is as shown in FIG. 8, and includes instructions L30-L34. Where a0-a2, I, J, X and W are variables. The above-described fetch stage 324 sequentially fetches instructions L30-L34 to decode stage 325. The decoding stage 325 and the execution stage 326 decode and execute the instructions L30-L34, respectively. The instruction L30 represents X = (p3 - p6), and is outputted to output an operation result of X = (p3 - p6). The instruction L31 represents W = (p4 - p5), and after being executed, the operation result of W = (p4 - p5) is output. The instruction L32 represents I=2W=2 (p4-p5), and is outputted to output an operation result of I=2W=2 (p4-p5). The instruction L33 represents J=2I+W=5 (p4-p5), and after being executed, the operation result of J=2I+W=5 (p4-p5) is output. The instruction L34 represents a0=(2X-J+4)>>3, and after being executed, the operation result of a0=(2X-J+4)>>3 is output, that is, the result of the formula (4). Similarly, the above decision stage 310 can output the execution paths corresponding to the formulas (5) and (6). The above-described fetch stage 324 sequentially fetches instructions from the above-described execution path to the above-described decode stage 325. The decoding stage 325 and the execution stage 326 respectively decode and execute the instructions in the execution path.

As described above, the image processing apparatus can store various instructions for implementing the deblocking methods of various video or video technologies or compression standards (for example, VC-1, MPEG2, and H.264). The more image processing devices integrated with the image or video technology or standard corresponding instructions, the more standard support flexibility can be provided. Each compute stage contains two ALUs to implement SIMD. In addition, the two arithmetic stages respond to the register setting bits of the end instruction to balance the burden of executing the instructions with each other, thereby achieving a pipeline architecture between the computing stages and increasing the overall efficiency of the deblocking filter. In summary, the above deblocking filter circuit applicable to various image processing devices can be applied to set-top boxes, media players, televisions, and video conferencing devices.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

220‧‧‧Execution unit

300‧‧‧pixel loaded finite state machine

310‧‧‧Decision level

312‧‧‧Mode Register

313, 323, 333‧‧‧ pixel register

314, 324, 334‧‧‧ extraction level

315, 325, 335‧‧ ‧ decoding level

316, 326, 336 ‧ ‧ executive level

322, 332‧‧‧ Path register

320‧‧‧ computing level

330‧‧‧ computing level

340‧‧‧Pixel update finite state machine

351-353‧‧‧ memory area

Claims (10)

An image deblocking filter includes: a command memory for storing a plurality of instructions, wherein a first one of the plurality of instructions represents three arithmetic operations acting on three variable operands and two constant operands Two bit operations; an execution unit for executing instructions stored in the instruction memory, and including a first arithmetic logic unit, wherein the first arithmetic logic unit is configured to execute the first instruction in a single clock cycle And a determining unit configured to execute the instruction stored in the instruction memory, thereby determining to extract a part of the plurality of instructions from the instruction memory to the first extraction path and the second extraction path of the execution unit; An extraction path, wherein when the execution unit executes the instruction according to the first extraction path or the second extraction path, respectively performing a deblocking formula in the first or second image compression standard, and the determined extraction path includes the foregoing a first instruction; wherein when the execution unit executes the first instruction, the image is deblocked Performing the above three arithmetic operations and two bit operations, comprising: performing a left shift operation as a first bit operation, implementing a first variable operation element; and performing a first addition operation as a first arithmetic operation And performing the first variable operation element and the second variable operation element after the left shift; setting a second addition operation or a subtraction operation as a second arithmetic operation according to the mode of the first instruction, wherein the foregoing The two addition operation includes the result of the first addition operation plus a third variable operation element, and the subtraction operation includes the result of the first addition operation minus the third variable operation element; a third addition operation as a third arithmetic operation, a result of the second arithmetic operation and a first constant operation element; and a right shift operation as a second bit operation, according to a second constant operation The value of the element shifts the result of the third addition described above to the right. The image deblocking filter according to claim 1, wherein the plurality of instructions include a cropping instruction with an upper limit value and a lower limit value, and the execution unit executes the above-mentioned one cropping instruction separately: two pairs of pens The variable operation unit performs a fourth addition operation; when the result of the fourth addition operation is within the range of the upper limit value and the lower limit value, the result of the fourth addition operation is output; when the fourth addition operation is performed When the result is greater than the upper limit value, the upper limit value is output; and when the result of the fourth addition operation is less than the lower limit value, the lower limit value is output. The image deblocking filter of claim 1, wherein the execution unit includes a first and a second operation stage, the first operation stage includes the first arithmetic logic unit, and the first operation stage transmits The instruction set after the first instruction in the extraction path is determined to be sent to the second operation level in response to the mode setting of the first instruction, and the second operation stage executes the instruction set. The image deblocking filter of claim 3, wherein the execution unit further comprises a second arithmetic logic unit, wherein the first and second arithmetic logic units respectively perform the first step in the same clock cycle Two instances of the instruction are applied to the two sets of operands in response to the mode setting of the first instruction. The image deblocking filter of claim 1, wherein the image deblocking filter is run in a set top box. An image processing device includes an image deblocking filter, and the image deblocking filter includes: a command memory for storing a plurality of instructions, wherein a first one of the plurality of instructions represents three arithmetic operations and two bit operations acting on three variable operands and two constant operands; And an instruction for storing in the instruction memory, and including a first arithmetic logic unit, wherein the first arithmetic logic unit is configured to execute the first instruction in a single clock cycle; and a determining unit is configured to execute And storing, in the instruction memory, an instruction to extract a part of the plurality of instructions from the instruction memory to one of the first extraction path and the second extraction path of the execution unit; wherein the execution unit Performing a deblocking formula in the first or second image compression standard respectively according to the first extraction path or the second extraction path execution instruction, and the determined extraction path includes the first instruction; wherein When the unit executes the first instruction, instructing the image deblocking filter to perform the above three arithmetic operations The two bit operations include: a left shift operation as a first bit operation, implemented in a first variable operation element; a first addition operation as a first arithmetic operation, implemented in the left shifting a first variable operation element and a second variable operation element; a second addition operation or a subtraction operation as a second arithmetic operation according to the mode of the first instruction, wherein the second addition operation comprises the first addition a third variable operation element is added to the result of the operation, and the subtraction operation includes the result of the first addition operation minus the third variable operation element; and a third addition operation as a third arithmetic operation is performed on the second The result of the arithmetic operation and a first constant operation element; and a right shift operation as a second bit operation, shifting the result of the third addition operation to the right according to the value of a second constant operation element. The image processing device of claim 6, wherein the plurality of instructions include a cropping instruction with an upper limit value and a lower limit value, and the execution unit executes the above-described one cropping instruction separately: two-variable arithmetic operation The element performs a fourth addition operation; when the result of the fourth addition operation is within the range of the upper limit value and the lower limit value, the result of the fourth addition operation is output; when the result of the fourth addition operation is greater than The upper limit value is outputted when the upper limit value is exceeded, and the lower limit value is output when the result of the fourth addition operation is less than the lower limit value. The image processing device of claim 6, wherein the execution unit includes a first and a second operation stage, the first operation stage includes the first arithmetic logic unit, and the first operation level is transmitted in the above It has been decided to extract a set of instructions following the first instruction in the path to the second operation level in response to the mode setting of the first instruction, and the second operation stage executes the instruction set. The image processing device of claim 8, wherein the execution unit further comprises a second arithmetic logic unit, wherein the first and second arithmetic logic units respectively execute the first instruction in the same clock cycle Two instances are respectively applied to the two sets of operands in response to the mode setting of the first instruction. The image processing device of claim 6, wherein the image deblocking filter is a set-top box.