TWI392948B - Active device array substrate - Google Patents

Description

Active device array substrate

The present invention relates to an active device array substrate, and more particularly to a circuit layout having a simultaneous application to a wafer-to-glass bonding process (COG process) and a wafer-to-film bonding process (COF process) ( Circuit layout) active device array substrate.

With the rapid development of liquid crystal display technology, a new generation of liquid crystal displays is developing in the direction of high brightness, wide viewing angle, fast response rate, high image resolution and full color. In addition to the liquid crystal panel, the liquid crystal display must also have a driver chip for driving the liquid crystal panel to achieve the result of development.

Most of the driving chips of liquid crystal displays today are by Chip On Glass (COG), Chip On Film (COF), Chip On Board (COB) or coil. A process such as Tape Automated Bonding (TAB) is bonded to the liquid crystal panel. In the die-film bonding process, the driving wafer is packaged on a flexible circuit board (FPC) to form a die-thickness package, and the die-film package is electrically connected to the liquid crystal display panel. In the die-glass bonding process, the driving wafer is directly electrically connected to the liquid crystal display panel in a flip chip manner.

When the active device array is fabricated, the die-glass bonding process is generally simultaneously performed on the non-display area (peripheral area) of the active device array substrate. Or a grain-film bonding process with matching peripheral lines. However, from the order-to-production process, design changes due to changes in customer demand, material price fluctuations, or other factors are difficult to avoid, and design changes will result in considerable cost burdens. In the conventional liquid crystal display panel, the circuit design on the peripheral area is only applicable to the die-glass bonding process or the die-film bonding process. Once the design is completed, it cannot be changed, so the design change cannot be made in a mobile manner. This leads to low production efficiency and increased production costs. Therefore, how to improve the design of the peripheral circuit is one of the problems to be overcome in the fabrication of the active device array substrate.

The present invention provides an active device array substrate having a circuit layout that can be simultaneously applied to a wafer-to-glass bonding process and a wafer-to-film packaging process.

The invention provides an active device array substrate comprising a substrate, a pixel array and a peripheral circuit. The substrate has an active area and a peripheral area connected to the active area. The pixel array is disposed on the active area. The peripheral line is disposed on the peripheral area, wherein the peripheral line has a first driving circuit bonding area and a second driving circuit bonding area, and the first driving circuit bonding area partially overlaps with the second driving circuit bonding area, and the peripheral line includes A plurality of first dedicated bonding pads, a plurality of second dedicated bonding pads, and a plurality of common bonding pads. Wherein the first dedicated bonding pad is located in the first driving circuit bonding region, the second dedicated bonding pad is located in the second driving circuit bonding region, and the common bonding pad is located The overlapping area of the first driving circuit bonding region and the second driving circuit bonding region, and the second dedicated bonding pads are electrically connected to the corresponding common bonding pads.

In an embodiment of the invention, the first dedicated bonding pad is located outside the overlapping area of the first driving circuit bonding region and the second driving circuit bonding region.

In an embodiment of the invention, a portion of the second dedicated bonding pads are located in an overlapping region of the first driver circuit bonding region and the second driver circuit bonding region.

In an embodiment of the present invention, the active device array substrate further includes a driving chip disposed on the first driving circuit bonding region, wherein the driving wafer is electrically connected to the common bonding pad and the first dedicated bonding pad, and is driven. The wafer is not bonded to the second dedicated bond pad.

In an embodiment of the present invention, the active device array substrate further includes an anisotropic conductive paste (ACP) disposed between the driving die and the peripheral line, wherein the driving wafer has a plurality of positions corresponding to the common bonding pad and The bump of the first special bonding pad, and the bump is electrically connected to the common bonding pad and the first dedicated bonding pad through the anisotropic conductive adhesive.

In an embodiment of the invention, the active device array substrate further includes an anisotropic conductive film (ACF) disposed between the driving wafer and the peripheral line, wherein the driving wafer has a plurality of positions corresponding to the common bonding pad. And a bump of the first dedicated bonding pad, and the bump is electrically connected to the common bonding pad and the first dedicated bonding pad through the anisotropic conductive film.

In one embodiment of the invention, a portion of the second dedicated bond pads are located below the drive wafer.

In an embodiment of the present invention, the active device array substrate further includes a die-bonding package (COF package) disposed on the second driver circuit bonding region, wherein the die-die bonding package and the common bonding The pad and the second dedicated bond pad are electrically connected, and the wafer-to-die bond package is not bonded to the first dedicated bond pad.

In an embodiment of the invention, the active device array substrate further includes an anisotropic conductive paste (ACP) disposed between the die-die bonded package and the peripheral line, wherein the wafer-die bonded package has a plurality of The positions correspond to the pins of the common bonding pad and the second dedicated bonding pad, and the pins are electrically connected to the common bonding pad and the second dedicated bonding pad through the anisotropic conductive adhesive.

In an embodiment of the invention, the active device array substrate further includes an anisotropic conductive film (ACF) disposed between the wafer-die bonded package and the peripheral line, wherein the wafer-die bonded package has a plurality of The positions correspond to the pins of the common bonding pad and the second dedicated bonding pad, and the pins are electrically connected to the common bonding pad and the second dedicated bonding pad through the anisotropic conductive film.

In an embodiment of the invention, the active device array substrate, wherein an overlapping area of the first driving circuit bonding region and the second driving circuit bonding region accounts for between 30% and 50% of an area of the first driving circuit bonding region.

In an embodiment of the invention, the active device array substrate, wherein an overlapping area of the first driving circuit bonding region and the second driving circuit bonding region occupies between 35% and 55% of an area of the second driving circuit bonding region.

In summary, the present invention can be applied to a wafer-glass bonding process and a wafer-film packaging process by designing a wiring layout in a peripheral region of the active device array substrate. In addition, the edge of the board is only slightly increased by the design of the overlap area.

The above described features and advantages of the present invention will be more apparent from the following description.

[First Embodiment]

FIG. 1A is a schematic diagram of an active device array substrate according to an embodiment of the invention. Referring to FIG. 1A , the active device array substrate 100 includes a substrate 110 , a pixel array 120 , and a peripheral line 130 . The active device array substrate 100 can be applied, for example, to a liquid crystal display (LCD), an organic light emitting display (OLED), a plasma display (PDP), a field emission display (FED), or the like. Further, the present invention does not limit the type of the active device array substrate 100. For example, the active device array substrate 100 may be a generally common thin film transistor array substrate, and the thin film electrode body is, for example, an amorphous germanium thin film transistor or a polycrystalline germanium thin film transistor. In addition, the active device array substrate 100 may also be a color filter on Array substrate (COA substrate) integrated with a color filter layer.

The substrate 110 has an active area 110a and a peripheral area 110b, wherein the peripheral area 110b and the active area 110a are connected to each other. The substrate 110 is, for example, a rigid substrate or a flexible substrate. In this embodiment, the material of the substrate 110 is, for example, It is an inorganic transparent material (such as glass, quartz, other suitable materials and combinations thereof), organic transparent materials (such as polyolefins, polybenzazoles, polyalcohols, polyesters, rubbers, thermoplastic polymers, thermosetting polymers, poly Aromatic hydrocarbons, polymethyl methacrylates, polycarbonates, other suitable materials, derivatives and combinations thereof, inorganic opaque materials (for example, bismuth, ceramics, other suitable materials or combinations thereof) Or a combination of the above.

Referring to FIG. 1A , the pixel array 120 is disposed on the active region 110 a of the substrate 110 . In detail, the active device array substrate 100 includes a plurality of scan lines 122 and data lines 124, and the scan lines 122 and the data lines 124 are perpendicular to each other and define a plurality of pixels 120a. In addition, a plurality of pixels 120a located on the active area 110a constitute a pixel array 120.

In the above, the peripheral line 130 is disposed on the peripheral region 110b of the substrate 110. The peripheral line 130 is used to connect the pixel array 120 on the active area 110a with a control circuit (such as a control circuit board).

FIG. 1B is a partially enlarged schematic view of a peripheral line according to an embodiment of the invention. Referring to FIG. 1B, the peripheral line 130 has a first driving circuit bonding region 130a and a second driving circuit bonding region 130b, and the first driving circuit bonding region 130a and the second driving circuit bonding region 130b partially overlap. In the present embodiment, the area A3 of the overlapping area 130c of the first driving circuit bonding region 130a and the second driving circuit bonding region 130b occupies between 30% and 50% of the area A1 of the first driving circuit bonding region 130a. Further, in the present embodiment, the area A3 of the overlapping area 130c of the first driving circuit bonding region 130a and the second driving circuit bonding region 130b occupies between 35% and 55% of the area A2 of the second driving circuit bonding region 130b.

As shown in FIG. 1B, a plurality of first dedicated bonding pads 132, a plurality of second dedicated bonding pads 134, and a plurality of common bonding pads 136 are disposed in the peripheral line 130, wherein the first dedicated bonding pads 132 are located in the first driving circuit. In the region 130a, the second dedicated bonding pad 134 is located in the second driving circuit bonding region 130b, and the common bonding pad 136 is located in the overlapping region 130c of the first driving circuit bonding region 130a and the second driving circuit bonding region 130b, and second The dedicated bond pads 134 are electrically connected to the corresponding common bond pads 136.

In the present embodiment, the first dedicated bonding pad 132 is located outside the overlapping region 130c of the first driving circuit bonding region 130a and the second driving circuit bonding region 130b. Further, a portion of the second dedicated bonding pad 134 is located within the overlapping region 130c of the first driving circuit bonding region 130a and the second driving circuit bonding region 130b as shown in FIG. 1B.

1C and 1D are schematic cross-sectional views of the A-A' direction and the B-B' direction of Fig. 1B, respectively. Referring to FIG. 1B and FIG. 1C simultaneously, in the embodiment, the first dedicated bonding pad 132 may be composed of the first conductive layer 112a, the insulating layer 114, the protective layer 116, and the second conductive layer 118a, and the first The dedicated bond pads 132 are electrically insulated from one another.

Referring to FIG. 1B and FIG. 1D simultaneously, in this embodiment, the second dedicated bonding pad 134 may be composed of the first conductive layer 112b, the insulating layer 114, the protective layer 116, and the second conductive layer 118b, and The two dedicated bonding pads 134 are electrically connected to each other.

Similarly, in the present embodiment, the common bonding pad 136 may be composed of the first conductive layer 112c, the insulating layer 114, the protective layer 116, and the second conductive layer 118c. Shared bond pad 136 and corresponding second dedicated The bond pads 134 are electrically connected to each other as shown in FIG. 1D. In this embodiment, the first conductive layers 112a, 112b, and 112c belong to the same layer of patterned conductive film, and the second conductive layers 118a, 118b, and 118c also belong to the same layer of patterned conductive film.

By designing the above-described wiring layout in the peripheral region 110b, the active device array substrate 100 can be simultaneously applied to the wafer-glass bonding process and the wafer-film packaging process without substantially increasing the edge of the board. Hereinafter, the structure of the active device array substrate 100 after fabrication by the wafer-glass bonding process and the wafer-film packaging process will be described with reference to the second embodiment and the third embodiment, respectively.

[Second embodiment]

2A is a partially enlarged schematic view showing an active device array substrate according to an embodiment of the present invention. 2B to 2C are schematic cross-sectional views of the A-A' direction and the B-B' direction of Fig. 1B, respectively. Referring to FIG. 2A, the active device array substrate 200 in this embodiment is similar to the active device array substrate 100 in the first embodiment, but the main difference is that the active device array substrate 200 further includes a driving chip. 240 is disposed on the first driving circuit bonding region 130a of the peripheral region 110b. In addition, in the embodiment, the active device array substrate 100 further includes an anisotropic conductive paste 250 disposed between the driving wafer 240 and the peripheral line 130.

Referring to FIG. 2B to FIG. 2C , the driving wafer 240 is electrically connected to the first dedicated bonding pad 132 and the common bonding pad 136 , and the driving wafer 240 is not engaged with the second dedicated bonding pad 134 . Further, in the present embodiment, a portion of the second dedicated bonding pad 134 is located in an area not covered by the driving wafer 240, as shown in FIG. 2C.

In detail, the driving wafer 240 has a plurality of positions corresponding to the common The bonding pads 136 and the bumps 242 of the first dedicated bonding pads 132 are electrically connected to the common bonding pads 136 and the first dedicated bonding pads 132 through the anisotropic conductive paste 250.

The bumps 242 of the driving wafer 240 are generally made of a conductive metal. For example, for example, gold bumps 242 made of highly conductive gold (Au), and the bumps 242 are contacted. Pad 244 is coupled to drive wafer 240 as shown in Figures 2B-2C. The anisotropic conductive paste 250 is mainly composed of an adhesive and conductive particles, and the composition of the adhesive is, for example, a resin.

When the driving wafer 240 is pressed together with the active device array substrate 200, the bumps 242 on the driving wafer 240 pass through the conductive particles in the anisotropic conductive paste 250 and the second conductive layer 118a on the active device array substrate 200. 118c contacts, and achieves the purpose of electrical connection. In other words, in the die-glass bonding process, the anisotropic conductive paste 250 is used as a medium for electrically connecting the driving wafer 240 and the active device array substrate 200.

In other possible embodiments, the active device array substrate 200 may also include an anisotropic conductive film (ACF) disposed between the driving wafer 240 and the peripheral line 130. The bumps 242 on the driving wafer 240 are electrically connected to the common bonding pads 136 on the active device array substrate 200 and the first dedicated bonding pads 132 through the anisotropic conductive film.

[Third embodiment]

3A is a partially enlarged schematic view showing an active device array substrate according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along line B-B' of Fig. 1B. Referring to FIG. 3A, the active device array substrate 300 in this embodiment is similar to the active device array substrate 100 in the first embodiment, but both The main difference is that the active device array substrate 300 further includes a wafer-bonding package (COF package) 340 disposed on the second driving circuit bonding region 130b. In addition, in the embodiment, the active device array substrate 300 further includes an anisotropic conductive paste 250 disposed between the wafer-bond bonding package 340 and the peripheral line 130.

Referring to FIG. 3B , the die-die bonding package 340 is electrically connected to the common bonding pad 136 and the second dedicated bonding pad 134 , and the wafer-die bonding package 340 is not bonded to the first dedicated bonding pad 132 .

In detail, the die-die bonding package 340 has a plurality of pins 342 corresponding to the common bonding pads 136 and the second dedicated bonding pads 134 , and the pins 342 pass through the anisotropic conductive paste 250 and the common bonding pads 136 . And the second dedicated bonding pad 134 is electrically connected.

The pins 342 of the wafer-bond bonded package 340 are generally made of a conductive metal. For example, the pins 342 are made of, for example, copper (Cu) having high conductivity.

When the wafer-die bonding package 340 is pressed together with the active device array substrate 300, the pins 342 on the wafer-bond bonding package 340 pass through the conductive particles in the anisotropic conductive paste 250 and the active device array substrate 300. The second conductive layer 118b is in contact with 118c to achieve electrical connection.

In other possible embodiments, the active device array substrate 300 may also include an anisotropic conductive film (ACF) disposed between the wafer-die bonded package 340 and the peripheral line 130, on the wafer-die bonded package 340. The pins 342 are electrically connected to the common bonding pads 136 and the second dedicated bonding pads 134 through the anisotropic conductive film.

In summary, the present invention designs the circuit layout in the peripheral region of the active device array substrate, so that the substrate can be applied to both the wafer-glass bonding process and the wafer-film packaging process, thereby improving process flexibility and production efficiency. In addition, by the design of the overlap region, the circuit layout of the present invention does not greatly increase the edge of the board, thereby saving glass cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300‧‧‧ active component array substrate

110‧‧‧Substrate

110a‧‧‧active area

110b‧‧‧ surrounding area

112a, 112b, 112c‧‧‧ first conductive layer

114‧‧‧Insulation

116‧‧‧Protective layer

118a, 118b, 118c‧‧‧ second conductive layer

120‧‧‧ pixel array

120a‧‧ ‧ pixels

122‧‧‧ scan line

124‧‧‧Information line

130‧‧‧ peripheral lines

130a‧‧‧First drive circuit junction area

130b‧‧‧Second drive circuit junction area

130c‧‧‧Overlapping areas

132‧‧‧First special joint pad

134‧‧‧Second special joint pad

136‧‧‧Shared joint pads

240‧‧‧Drive chip

242‧‧‧Bumps

250‧‧‧ anisotropic conductive adhesive

340‧‧‧Wafer-film bonded package

342‧‧‧ pin

A1, A2, A3‧‧‧ area

FIG. 1A is a schematic diagram of an active device array substrate according to an embodiment of the invention.

FIG. 1B is a partially enlarged schematic view of a peripheral line according to an embodiment of the invention.

1C and 1D are schematic cross-sectional views of the A-A' direction and the B-B' direction of Fig. 1B, respectively.

2A is a partially enlarged schematic view showing an active device array substrate according to an embodiment of the present invention.

2B to 2C are schematic cross-sectional views of the A-A' direction and the B-B' direction of Fig. 1B, respectively.

3A is a partially enlarged schematic view showing an active device array substrate according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view taken along line B-B' of Fig. 1B.

130a‧‧‧First drive circuit junction area

130b‧‧‧Second drive circuit junction area

130c‧‧‧Overlapping areas

132‧‧‧First special joint pad

134‧‧‧Second special joint pad

136‧‧‧Shared joint pads

Claims (11)

An active device array substrate includes: a substrate having an active region and a peripheral region connected to the active region; a pixel array disposed on the active region; and a peripheral circuit disposed on the peripheral region The peripheral circuit has a first driving circuit bonding region and a second driving circuit bonding region, and the first driving circuit bonding region partially overlaps the second driving circuit bonding region, and the peripheral circuit includes: a plurality of first a dedicated bonding pad located in the first driving circuit bonding region; a plurality of second dedicated bonding pads located in the second driving circuit bonding region; and a plurality of common bonding pads located in the first driving circuit bonding region and the first The second dedicated bonding pads are electrically connected to the corresponding common bonding pads, and the first dedicated bonding pads are located in the first driving circuit bonding region and the second driving circuit. Outside the overlap area of the joint area. The active device array substrate according to claim 1, wherein a portion of the second dedicated bonding pads are located in an overlapping region of the first driving circuit bonding region and the second driving circuit bonding region. The active device array substrate of claim 1, further comprising a driving chip disposed on the first driving circuit bonding region, wherein the driving chip and the common bonding pads and the first dedicated bonding pads Electrically connected, and the driver chip is not associated with the second dedicated The bond pads are joined. The active device array substrate of claim 3, further comprising an anisotropic conductive paste disposed between the driving wafer and the peripheral line, wherein the driving wafer has a plurality of positions corresponding to the common bonding And a bump of the first dedicated bonding pad, and the bumps are electrically connected to the common bonding pads and the first dedicated bonding pads through the anisotropic conductive adhesive. The active device array substrate according to claim 3, further comprising an anisotropic conductive film disposed between the driving wafer and the peripheral line, wherein the driving wafer has a plurality of positions corresponding to the common bonding The pads and the bumps of the first dedicated bonding pads, and the bumps are electrically connected to the common bonding pads and the first dedicated bonding pads through the anisotropic conductive film. The active device array substrate according to claim 3, wherein a part of the second dedicated bonding pad is located under the driving wafer. The active device array substrate according to claim 1, further comprising a wafer-die bonding package disposed on the second driving circuit bonding region, wherein the wafer-die bonding package and the common bonding pads And the second dedicated bonding pads are electrically connected, and the wafer-die bonding package is not bonded to the first dedicated bonding pads. The active device array substrate of claim 7, further comprising an anisotropic conductive paste disposed between the die-bond bond package and the peripheral line, wherein the wafer-chip bonded package has a plurality of The positions correspond to the common bonding pads and the pins of the second dedicated bonding pads, and the pins are electrically connected to the common bonding pads and the second dedicated bonding pads through the anisotropic conductive paste. connection. The active device array substrate according to claim 7, further comprising an anisotropic conductive film disposed between the wafer-die bonded package and the peripheral line, wherein the wafer-die bonded package has a plurality of The positions correspond to the common bonding pads and the pins of the second dedicated bonding pads, and the pins pass through the anisotropic conductive film and the common bonding pads and the second dedicated bonding pads are electrically connected. connection. The active device array substrate according to claim 1, wherein an overlapping area of the first driving circuit bonding region and the second driving circuit bonding region accounts for 30% to 50% of an area of the first driving circuit bonding region. between. The active device array substrate according to claim 1, wherein an overlapping area of the first driving circuit bonding region and the second driving circuit bonding region accounts for 35% to 55% of an area of the second driving circuit bonding region. between.