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TWI389868B - Semiconductor porcelain composition and method of manufacturing the same - Google Patents

Semiconductor porcelain composition and method of manufacturing the same Download PDF

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Publication number
TWI389868B
TWI389868B TW095115537A TW95115537A TWI389868B TW I389868 B TWI389868 B TW I389868B TW 095115537 A TW095115537 A TW 095115537A TW 95115537 A TW95115537 A TW 95115537A TW I389868 B TWI389868 B TW I389868B
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Taiwan
Prior art keywords
tio
calcined powder
bina
sintering
temperature
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TW095115537A
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English (en)
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TW200706511A (en
Inventor
Takeshi Shimada
Koichi Terao
Kazuya Toji
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Hitachi Metals Ltd
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Publication of TW200706511A publication Critical patent/TW200706511A/zh
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Publication of TWI389868B publication Critical patent/TWI389868B/zh

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Description

半導體瓷器組成物和其製造方法
本發明係關於被使用於PTC熱阻體、PTC加熱器、PTC開關、溫度感測器等之具有正之電阻溫度之半導體瓷器組成物及其製造方法。
關於顯示PTCR特性(正之比電阻溫度係數:Positive Temperature Coefficient of Resistivity)之材料,在以往提案有對BaTiO3 添加各種半導體化元素而成之組成物。此等組成物之居里溫度為120℃左右。又按,依照用途之情形,有時必需使居里溫度移位。
例如有,對BaTiO3 添加SrTiO3 以使居里溫度移位之提案,但在此情況,居里溫度僅往負之方向移位,不會往正之方向移位。目前,僅知PbTiO3 為唯一可使居里溫度往正之方向移位之添加元素。然而,PbTiO3 含有引起環境污染之元素,因此在最近需求未使用PbTiO3 之材料。
關於BaTiO3 系半導體瓷器,有一種在防止Pb置換所引起之電阻溫度係數之降低之同時,抑低電壓依存性而提高生產性或可靠性之目的下,未使用PbTiO3 之製造BaTiO3 系半導體瓷器之方法,係在BaTiO3 之Ba之一部分置換成Bi-Na之Ba1 2 x (BiNa)x TiO3 之構造中,對設定x在0<x≦0.15之範圍內之組成物添加一種或一種以上之Nb或Ta或稀土類元素而在氮氣中燒結後,於氧化性環境內施行熱處理者被提案(專利文獻1)。
專利文獻1:日本專利特開昭56-169301號公報
在專利文獻1之實施例揭示,將充當起始原料之BaCO3 、TiO2 、Bi2 O3 、Na2 O3 、PbO等構成組成物之全部元素在煅燒前混合後,施行煅燒、成形、燒製、熱處理。
然而,在BaTiO3 之Ba之一部分置換成Bi-Na而成之組成物之情況有下述問題:若依專利文獻1所述將構成組成物之全部元素在煅燒前混合,則在煅燒步驟中發生Bi之揮發散失,致使Bi-Na之組成有偏移,因此促進異相之產生而引起室溫電阻率之升高,居里溫度之變動。
為了抑制Bi之揮發散失,亦可考慮低溫煅燒,但此雖然可抑制Bi之揮發散失,卻無法形成完全之固溶體,而造成無法得到所想要之特性之問題。
在另一方面,在BaTiO3 材料之情況,如還原環境中之燒結等,以室溫比電阻可變小之方式予以處理時,電阻溫度係數減低(突變特性)為其問題(非專利文獻1及2)。在電阻溫度係數減低時,則造成在標的溫度下不發生轉換作用之問題。為了解決此等問題,在非專利文獻1及2之情況,在大氣中(空氣中)施行熱處理,藉此改善電阻溫度係數。
非專利文獻1:材料學會第109回陶瓷材料部門委員會預稿集13-14(2003)非專利文獻2:J.Soc.Mat.Sci.,Japan,Vol.52,1155-1159(2003)
在依照上述專利文獻1之Ba1 2 x (BiNa)x TiO3 材料之情況,亦在還原環境內之燒結等,以室溫比電阻可變小之方式予以處理時,有電阻溫度係數減低之傾向。但對Ba1 2 x (BiNa)x TiO3 材料在大氣中施行熱處理時,室溫比電阻則有升高之傾向,即無法直接應用BaTiO3 系材料上之熱處理條件。
本發明之目的在於提供:可在未使用Pb之下,使居里溫度往正之方向移位之同時,大幅降低室溫電阻率之半導體瓷器組成物及其製造方法。
再者,本發明之目的在於提供:在BaTiO3 之Ba之一部分置換成Bi-Na而成之半導體瓷器組成物之情況,可抑制煅燒步驟中之Bi之揮發散失,以防止Bi-Na之組成偏移,抑制異相之產生而使室溫電阻率進一步降低之同時,可抑制居里溫度之變動之半導體瓷器組成物及其製造方法。
此外,本發明之目的在於提供:在BaTiO3 之Ba之一部分置換成Bi-Na而成之半導體瓷器組成物之情況,可在未施行大氣中之熱處理等之下,保持低值之室溫比電阻,且提高在高溫域(居里溫度以上)之電阻溫度係數之半導體瓷器組成物及其製造方法之提供。
為了達成上述目的,本案發明人等潛心進行研究結果,得到下述知識:在製造一由BaTiO3 之Ba之一部分置換成Bi-Na而成之半導體瓷器組成物之際,各別準備(BaQ)TiO3 組成物(Q為半導體化元素)及(BiNa)TiO3 組成物,將(BaQ)TiO3 組成物在較高溫之對其最適之溫度下予以煅燒且將(BiNa)TiO3 組成物在較低溫之對其最適之溫度下予以煅燒時,藉此可抑制(BiNa)TiO3 組成物之Bi之揮發散失,防止Bi-Na之組成偏移而抑制異相之產生,使此等煅燒粉末混合而予以成形、燒結時,藉此可得到一具有低值之室溫電阻率而抑制居里溫度之變動之半導體瓷器組成物。
再者,本案發明人等關於由上述BaTiO3 之Ba之一部分置換成Bi-Na而成之半導體瓷器組成物,為了室溫電阻之抑低,而嘗試惰性氣體環境內之燒結處理,結果得知由於燒結溫度、燒結時間、燒結環境、或試料大小等因素,電阻溫度係數(突變特性)會變動之事實。於是,進一步潛心研究結果發現下述事實:燒結時間愈長,室溫電阻及電阻溫度係數愈低;控制燒結後之冷卻速度時,電阻溫度係數則會升高,即使在燒結時間延長時亦然。據此得到下述知識:如BaTiO3 系材料之情況,在燒結後,即使未施行大氣中之熱處理等,亦可以保持低值之室溫比電阻之同時,提高高溫域(居里溫度以上)之電阻溫度係數。
亦即,本發明為製造一由BaTiO3 之Ba之一部分置換成Bi-Na而成之半導體瓷器組成物之方法,其特徵係包含:準備(BaQ)TiO3 煅燒粉(Q為半導體化元素)之步驟;準備(BiNa)TiO3 煅燒粉之步驟;使(BaQ)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟;及將煅燒粉混合物予以成形、燒結之步驟。
依照本發明,可提供一種不使用引起環境污染之Pb,使居里溫度升高之同時,大幅降低室溫電阻率之半導體瓷器組成物。
依照本發明,可提供一種抑制煅燒步驟時之Bi之揮發散失,以防止Bi-Na之組成偏移而抑制含有Na之異相之產生,使室溫電阻率進一步降低之同時,抑制居里溫度之變動之半導體瓷器組成物。
依照本發明,可提供一種在燒結後即使未施行大氣中之熱處理等,亦可以保持低值之室溫比電阻,同時提高高溫域(居里溫度以上)之電阻溫度係數之半導體瓷器組成物。
依照本發明之準備(BaQ)TiO3 煅燒粉(Q為半導體化元素)之步驟為,首先使BaCO3 、TiO2 與半導體化元素之原料粉末(例如La2 O3 或Nb2 O5 )混合以製備原料粉末混合物,而予以煅燒。煅燒溫度在900~1300℃範圍內者較佳,煅燒時間以0.5小時以上較佳。若煅燒溫度低於900℃或煅燒時間未滿0.5小時,(BaQ)TiO3 則不會完全形成,未反應之BaO會與環境中之水分及混合媒體之水分起反應而成為組成偏移之原因,因此不合適。再者,若煅燒溫度超過1300℃,煅燒粉則會產生燒結體而妨礙此煅燒粉與其後混合之(BiNa)TiO3 煅燒粉之固溶,因此不合適。
依照本發明之準備(BiNa)TiO3 煅燒粉之步驟為,首先使充當原料粉末之Na2 CO3 、Bi2 O3 、以及TiO2 混合以製備原料粉末混合物,而予以煅燒。煅燒溫度在700~950℃範圍內者較佳,煅燒時間以0.5小時~10小時較佳。若煅燒溫度未滿700℃或煅燒時間未滿0.5小時,未反應之NaO則會與環境中之水分或濕式混合時之溶媒起反應而成為組成偏移或特性變動之原因,因此不合適。再者,若煅燒溫度超過950℃或煅燒時間超過10小時,Bi之揮發散失則會持續,引起組成之偏移而促進異相之產生,因此不合適。
又按,上述之準備(BaQ)TiO3 煅燒粉之步驟中之較佳煅燒溫度(900~1300℃)及準備(BiNa)TiO3 煅燒粉之步驟中之較佳煅燒溫度(700~950℃)係最好能依照用途等之情形適當選定最適溫度。例如(BiNa)TiO3 之煅燒溫度係為了在抑制Bi之揮發散失之下充分施行反應,最好能設法調整煅燒時間等,俾可在較低溫下施行煅燒。再者,(BiNa)TiO3 之煅燒溫度最好能設定為比(BaQ)TiO3 之煅燒溫度為低之溫度。
將上述之準備(BaQ)TiO3 煅燒粉(Q為半導體化元素)之步驟及準備(BiNa)TiO3 煅燒粉之步驟予以各別分開施行係本發明之主要特徵,藉此可提供一種抑制煅燒步驟時之(BiNa)TiO3 之Bi之揮發散失,以防止Bi-Na之組成偏移而抑制異相之產生,使室溫電阻率進一步降低,同時抑制居里溫度之變動之半導體瓷器組成物。
在上述之準備各煅燒粉之步驟中,在原料粉末之混合之際,依照原料粉末之粒度之情形施行粉碎亦可。再者,混合、粉碎為使用純水或甲醇之濕式混合、粉碎,或乾式混合、粉碎均可,不過在施行乾式混合、粉碎時,更可防止組成之偏移,因此較佳。又按,在上述中,作為原料粉末,舉出BaCO3 、Na2 CO3 、TiO2 等為其例子,不過使用其他之Ba化合物、Na化合物等,亦不會損及本發明之效果。
如上所述,各別準備(BaQ)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉後,按指定量摻配各煅燒粉,然後施行混合。混合方式為屬於使用純水或甲醇之濕式混合,或乾式混合均可,在施行乾式混合時,更可防止組成之偏移,因此較佳。再者,依照煅燒粉之粒度之情形,混合後施行粉碎,或混合與粉碎同時進行亦可。混合、粉碎後之煅燒粉混合物之平均粒度係以0.6 μ m~1.5 μ m較佳。
在上述之準備(BaQ)TiO3 煅燒粉之步驟及/或準備(BiNa)TiO3 煅燒粉之步驟或混合各煅燒粉之步驟中,若添加Si氧化物3.0 mol%以下,Ca碳酸鹽或Ca氧化物4.0 mol%以下,Si氧化物則可抑制晶粒之異常生長,同時使電阻率變得容易控制,而Ca碳酸鹽或Ca氧化物則可提高低溫燒結性,因此較佳。當任一方超過上述限定量進行添加,則均會使組成物不顯示半導體化,因此不合適。添加係最好能在各步驟中之混合前施行。
使用(BaQ)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉之混合步驟所得之煅燒粉混合物成形、燒結,即可得到依照本發明之半導體瓷器組成物。以下舉出煅燒粉混合步驟以後之較佳步驟之一例,但並未受到該例之限制,而可採用習知之所有方法。
對一由(BaQ)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉之混合步驟所得之煅燒粉混合物藉所希望之成形手段施行成形。在成形前,必要時將粉碎粉藉造粒裝置予以造粒亦可。成形後之成形體密度係以2~3 g/cm3 較佳。
燒結係可在大氣中或還原環境中,或在低氧氣濃度之惰性氣體環境中,按1200℃~1400℃之燒結溫度及2小時~6小時之燒結時間施行,此外,採用以下所示之燒結步驟亦為本發明之特徵之一的較佳例。又按,在成形前施行造粒之情況,最好能在燒結前於300℃~700℃溫度下施行脫黏合劑處理。
作為燒結步驟,在1290℃~1350℃之燒結溫度下,在氧氣濃度未滿1%之環境中,(1)按未滿4小時之燒結時間施行燒結,或按滿足式(2):△T≧25t(t=煅燒時間(hr),△T=燒結後之冷卻速度(℃/hr))之燒結時間施行燒結,其次,按滿足上式之冷卻速度施行燒結後之冷卻。
無論屬於上述任一燒結步驟,即縮短燒結時間或延長燒結時間,均按適於其燒結時間之驟冷速度驟冷,藉此即使未施行如在BaTiO3 系材料所進行之大氣中之熱處理等,亦可以得到一種在保持低值之室溫比電阻之下,提高高溫域(居里溫度以上)之電阻溫度係數之半導體瓷器組成物。
在上述燒結步驟中,氧氣濃度未滿1%之環境中係指氧氣濃度未滿1%之真空中或惰性氣體環境中而言。最好能在惰性氣體環境中,例如在氮氣、氬氣環境中施行。又按,燒結後之冷卻時之環境亦以上述環境較佳,但未必如此。
在上述燒結步驟中,施行前述(1)之方法之情況,可任意選擇燒結後之冷卻條件。在另一方面,在施行前述(2)之方法之情況,冷卻速度△T(℃/hr)係取決於燒結時間t之長度。例如,在燒結時間t為1小時之情況,冷卻速度△T則成為25×1=25℃/hr以上,在燒結時間t為4小時之情況,冷卻速度△T則成為25×4=100℃/hr以上。即在延長燒結時間t之情況,依照其燒結時間,將冷卻速度△T加快。此一方法雖然在燒結時間t加長之情況有效,但在燒結時間t較短(例如未滿4小時)之情況亦有可能被應用。
在本發明中,成為對象之半導體瓷器組成物係由BaTiO3 之Ba之一部分置換成Bi-Na而成,其如上所述,各別施行準備(BaQ)TiO3 煅燒粉(Q為半導體化元素)之步驟及準備(BiNa)TiO3 煅燒粉之步驟,使此等煅燒粉混合、成形、燒結即可得。
由BaTiO3 之一部分置換成Bi-Na而成之組成物係添加半導體化元素,施行原子價控制,而成為半導體瓷器組成物。在本發明中,半導體化元素添加於BaTiO3 之一方,以使成為(BaQ)TiO3 煅燒粉(Q為半導體化元素)。
作為半導體化元素Q,以R(R為La、Dy、Eu、Gd、以及Y中之至少一元素)或M(M為Nb、Ta、以及Sb中之至少一元素)較佳。在使用R(R為La、Dy、Eu、Gd、以及Y中之至少一元素)之情況,所得之半導體瓷器組成物則用一組成式[(BiNa)x (Ba1 y Ry )1 x ]TiO3 予以表示,其中x、y為滿足0<x≦0.2,0<y≦0.02者。
在另一方面,使用M(M為Nb、Ta、以及Sb中之至少一元素)為半導體化元素Q之情況,所得之半導體瓷器組成物則用一組成式[(BiNa)x Ba1 x ][Ti1 z Mz ]03 予以表示,x、z滿足0<x≦0.2,0<z≦0.005。又,作為半導體化元素Q,無論使用R之情況或使用M之情況,該半導體瓷器組成物為由BaTiO3 之一部分被Bi-Na置換而成之組成物之事實均不變。
以下,關於上述之[(BiNa)x (Ba1 y Ry )1 x ]TiO3 及[(BiNa)x Ba1 x ][Ti1 z Mz ]O3 之兩組成物加以詳細說明。
在上述[(BiNa)x (Ba1 y Ry )1 x ]TiO3 組成物中,R為La、Dy、Eu、Gd、以及Y中之至少一元素,尤其以La較佳。在組成式中,x表示Bi+Na之成分範圍,0<x≦0.2為較佳之範圍。在x為0時,無法使居里溫度往高溫側移位,另若x超過0.2,室溫電阻率則接近104 Ω cm,難於應用於PTC加熱器等,因此均不合適。
再者,組成式中之y表示R之成分範圍,0<y≦0.02為較佳之範圍。在y為0時,組成物則不會半導體化,另若y超過0.02,室溫電阻率則變大,因此均不合適。使此y值變化,以施行原子價之控制,但在Ba之一部分置換有Bi-Na之系中,施行組成物之原子價控制之情況有下述問題:若將3價陽離子當作半導體化元素添加時,半導體化之效果則因1價Na離子之存在而降低,致使室溫電阻率變高。從而,進一步較佳之範圍為0.002≦y≦0.02。又按,上述0.002≦y≦0.02以mol%表示時,則成為0.2 mol%~2.0 mol%。又按,在前述之專利文獻1中,為充作半導體化元素,添加0.1 mol%之Nd2 O3 ,但此被認為,在PTC用途上無法實現充分之半導體化。
在[(BiNa)x Ba1 x ][Ti1 z Mz ]O3 組成物中,M為Nb、Ta、以及Sb中之至少一元素,尤其以Nb較佳。在組成式中,x表示Bi+Na之成分範圍,0<x≦0.2為較佳之範圍。在x為0時,無法使居里溫度往高溫側移位,另若x超過0.2,室溫電阻率則接近104 Ω cm,難於應用於PTC加熱器等,因此均不合適。
再者,組成式中之z表示M之成分範圍,0<z≦0.005為較佳之範圍。在z為0時,無法施行原子價之控制,組成物不會半導體化,另若z超過0.005,室溫電阻率則超過103 Ω cm,因此均不合適。又按,上述0<z≦0.005以mol%表示時,則成為0~0.5 mol%(不包括0)。
在上述[(BiNa)x Ba1 x ][Ti1 z Mz ]O3 組成物之情況,為了施行原子價之控制,將Ti置換以M元素,而在此情況M元素之添加(添加量為0<z≦0.005)係以4價元素Ti側原子價之控制為目的,與使用R為半導體化元素之[(BiNa)x (Ba1 y Ry )1 x ]TiO3 組成物中之R元素之較佳添加量(0.002≦y≦0.02)相比,可用較少之添加量來施行原子價之控制,而具有可將依照本發明之半導體瓷器組成物之內部應變予以減輕等之優點。
在上述之[(BiNa)x (Ba1 y Ry )1 x ]TiO3 及[(BiNa)x Ba1 x ][Ti1 z Mz ]O3 之兩組成物中,較佳的是,Bi:Na之比率為1:1,即在組成式成為[(Bi0 . 5 Na0 . 5 )x (Ba1 y Ry )1 x ]TiO3 、[(Bi0 . 5 Na0 . 5 )x Ba1 x ][Ti1 z Mz ]O3 者。但如前面之先前技術中所述,若將構成組成物之全部元素在煅燒前混合,則會造成下述問題:在煅燒步驟中發生Bi之揮發散失,致使Bi-Na之組成有偏移,因此促進異相之產生而引起室溫電阻率之升高,居里溫度之變動。
在本發明中,由於將(BaQ)TiO3 組成物與(BiNa)TiO3 組成物各別分開按其最適溫度煅燒,可將Bi與Na之比率設定為Bi/Na=0.78~1,可將室溫電阻率進一步降低之同時,可抑制居里溫度之變動。若Bi/Na超過1,對(BiNa)TiO3 之產生未參與之Bi則會留存於材料中,在燒結時容易產生異相,致使室溫電阻率升高,另若Bi/Na未滿0.78,則在燒結階段容易產生異相,致使室溫電阻率升高,因此均不合適。
依照上述製造方法,可得到一種以[(BiNa)x (Ba1 y Ry )1 x ]TiO3 (R為La、Dy、Eu、Gd、以及Y中之至少一元素)表示組成式,x、y滿足0<x≦0.2,0<y≦0.02,且Bi與Na之比率滿足Bi/Na=0.78~1之關係之半導體瓷器組成物,或一種以[(BiNa)x Ba1 x ][Ti1 z Mz ]O3 (M為Nb、Ta、以及Sb中之至少一元素)表示組成式,x、z滿足0<x≦0.2,0<z≦0.005,且Bi與Na之比率滿足Bi/Na=0.78~1之關係之半導體瓷器組成物,此等半導體瓷器組成物具有下述效果:可在未使用引起環境污染之Pb之下,使居里溫度升高之同時,可大幅降低室溫電阻率。
[實施例] (實施例1)
準備BaCO3 、TiO2 (充作主要原料)、以及La2 O3 (充作半導體化元素)之原料粉末,以可成為(Ba0 . 9 9 4 La0 . 0 0 6 )TiO3 之方式予以摻配,然後對此添加SiO2 0.3 mol%及CaCO3 1.2 mol%以充作燒結助劑,在乙醇中混合。將所得之原料粉末混合物在1000℃溫度下煅燒4小時,而備妥(BaLa)TiO3 煅燒粉。
準備Na2 CO3 、Bi2 O3 、以及TiO2 之原料粉末,以可成為(Bi0 . 5 Na0 . 5 )TiO3 之方式予以摻配,然後對此添加SiO2 0.08 mol%及CaO 0.27 mol%以充作燒結助劑,在大氣中(乾式)或乙醇中(濕式)混合。將所得之原料粉末混合物在大氣中且在600℃~900℃溫度下煅燒4小時,而得到(BiNa)TiO3 煅燒粉。所得之(Bi0 . 5 Na0 . 5 )TiO3 煅燒粉在600~900℃之每一煅燒溫度之X射線圖形示於圖1中。
將上述(BaLa)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式予以摻配,在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉混合物之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在大氣中且在1320℃燒結溫度下燒結4小時而得到燒結體。將所得燒結體之Na量與Bi量之成分分析結果示於表1中。又按,Bi量係以Na量當作100時換算之數值。再者,表1中之混合方法為(Bi0 . 5 Na0 . 5 )TiO3 之混合方法。
(比較例1)
準備BaCO3 、TiO2 (充作主要原料)、La2 O3 (充作半導體化元素)、Na2 CO3 、Bi2 O3 、以及TiO2 (充作居里溫度之移位劑),以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式將構成組成物之全部元素從最初起摻配,然後對此添加SiO2 0.4 mol%及CaCO3 1.4mol%以充作燒結助劑,在乙醇中(濕式)混合。將所得之原料粉末混合物在氮氣中且在200℃~1200℃溫度下煅燒4小時,而得到煅燒粉。所得之[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之煅燒粉在200~900℃之每一煅燒溫度之X射線圖形係示於圖2中。
對所得之煅燒粉添加混合PVA後,用造粒裝置以使造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在大氣中在1320℃燒結溫度下燒結4小時而得到燒結體。所得燒結體之Na量與Bi量之成分分析結果係示於表1中。又按,Bi量係以Na量當作100時換算之數值。
由圖1及圖2顯然得知,依照實施例1之(BiNa)TiO3 煅燒粉係在700℃時完全成為單一相。在另一方面,在依照比較例1之從最初起摻配其構成組成物之全部成分之情況,除非900℃以上,否則無法完全固溶,即無法得到十分符合要求之煅燒粉。
再者,由表1顯然得知,依照實施例1之(BiNa)TiO3 煅燒粉在每一煅燒溫度均示其Bi揮發散失量很少,而在形成完全固溶體之溫度(700℃)時,亦示其Bi幾乎完全未揮發散失。又得知,按乾式施行混合者較可抑制Bi之揮發散失。在另一方面,依照比較例1之從最初起摻配其構成組成物之全部元素而得到之煅燒粉,其Bi揮發散失量多於實施例1,而在形成完全固溶體之900℃溫度時,已有多量之Bi揮發散失。
(實施例2)
準備BaCO3 、TiO2 (充作主要原料)、以及La2 O3 (充作半導體化元素)之原料粉末,以可成為(Ba0 . 9 9 4 La0 . 0 0 6 )TiO3 之方式予以摻配,然後對此添加SiO2 0.3 mol%及CaCO3 1.2 mol%以充作燒結助劑,在乙醇中混合。將所得之原料粉末混合物在1000℃溫度下煅燒4小時,而備妥(BaLa)TiO3 煅燒粉。
準備Na2 CO3 、Bi2 O3 、以及TiO2 之原料粉末,以可成為(Bi0 . 5 Na0 . 5)TiO3 之方式予以摻配,然後對此添加SiO2 0.08 mol%及CaCO3 0.27 mol%以充作燒結助劑,在大氣中或乙醇中混合。將所得之原料粉末混合物在650℃~1000℃溫度下煅燒4小時,而備妥(BiNa)TiO3 煅燒粉。
將上述(BaLa)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式予以摻配,在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉混合物之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在大氣中在1290℃、1320℃、以及1350℃之燒結溫度下燒結4小時而得到燒結體。
將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果示於表2中。再者,施行Bi及Na之成分分析,以求出Bi/Na之比率。所得之結果示於表2中。又按,表1中之No.6試料係在製備(BiNa)TiO3 煅燒粉之步驟中,在大氣中施行混合者,其他試料均在乙醇中施行混合。No.5試料係被設定燒結時間為2小時之試料。No.11試料係在摻配時過剩添加Bi2 O3 之試料。再者,在試料編號旁邊附加有*記號者為比較例。
(比較例2)
準備BaCO3 、TiO2 (充作主要原料)、La2 O3 (充作半導體化元素)、Na2 CO3 、Bi2 O3 、以及TiO2 (充作居里溫度之移位劑),以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式將構成組成物之全部元素從最初起摻配,然後對此添加SiO2 0.4 mol%及CaCO3 1.4 mol%以充作燒結助劑,在乙醇中混合後,將所得之原料粉末混合物在大氣中且在1000℃溫度下煅燒4小時。
將所得之煅燒粉在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉之大小達到0.9 μ m為止,然後使之乾燥。對該項粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,所得之成形體在500℃溫度下脫除黏合劑後,在大氣中在1290℃、1320℃、以及1350℃之燒結溫度下燒結4小時而得到燒結體。
將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果示於表3中。再者,施行Bi及Na之成分分析,以求出Bi/Na之比率。所得之結果示於表3中。
由表2及表3顯然得知,根據實施例之依照本發明之半導體瓷器組成物可使居里溫度上升之同時,可大幅降低室溫電阻率。再者,由於將準備(BaQ)TiO3 煅燒粉(Q為半導體化元素)之步驟及準備(BiNa)TiO3 煅燒粉之步驟各別分開施行,已抑制Bi之揮發散失,在燒結後亦具有高度之Bi/Na比,因此抑制異相之產生,進一步降低室溫電阻率之同時,抑制居里溫度之變動。又按,雖然在本實施例中展示半導體化元素Q之R使用La之情況,但已確認在使用其他之R元素及M元素之情況亦可得到與使用La之情況約略相同之特性。
與此相對地,依照比較例之半導體瓷器組成物雖然企求居里溫度之上升,但其室溫電阻率高,電阻溫度係數低。再者,由於在煅燒步驟及燒結步驟發生多量之Bi之揮發散失,燒結後之Bi/Na比成為0.77以下。室溫電阻率之增高被認為係Bi之揮發散失所引起之異相之產生所致。
(實施例3)
準備BaCO3 、TiO2 (充作主要原料)、以及La2 O3 (充作半導體化元素)之原料粉末,以可成為(Ba0 . 9 9 4 La0 . 0 0 6 )TiO3 之方式予以摻配,在乙醇中混合。將所得之原料粉末混合物在1000℃溫度下煅燒4小時,而備妥(BaLa)TiO3 煅燒粉。
準備Na2 CO3 、Bi2 O3 、以及TiO2 之原料粉末,以可成為(Bi0 . 5 Na0 . 5 )TiO3 之方式予以摻配,在乙醇中混合。將所得之原料粉末混合物在800℃溫度下煅燒4小時,而備妥(BiNa)TiO3 煅燒粉。
將上述(BaLa)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式予以摻配,在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉混合物之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在大氣中在1290℃、1320℃、以及1350℃之燒結溫度下燒結4小時而得到燒結體。
將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果示於表4中。再者,施行Bi及Na之成分分析,以求出Bi/Na之比率。所得之結果示於表4中。
實施例3係展示在製程中未添加Si氧化物及Ca碳酸鹽或Ca氧化物之例子,但由表4顯然得知,即使未添加Si氧化物及Ca碳酸鹽或Ca氧化物,亦可得到與實施例2施行該項添加之例子約略相同之特性。
(實施例4)
準備BaCO3 、TiO2 (充作主要原料)、以及La2 O3 (充作半導體化元素)之原料粉末,以可成為(Ba0 . 9 9 4 La0 . 0 0 6 )TiO3 之方式予以摻配,在乙醇中混合。將所得之原料粉末混合物在1000℃溫度下煅燒4小時,而備妥(BaLa)TiO3 煅燒粉。
準備Na2 CO3 、Bi2 O3 、以及TiO2 之原料粉末,以可成為(Bi0 . 5 Na0 . 5 )TiO3 之方式予以摻配,在乙醇中混合。將所得之原料粉末混合物在大氣中且在800℃溫度下煅燒4小時,而備妥(BiNa)TiO3 煅燒粉。
將上述(BaLa)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式予以摻配,在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉混合物之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在氧氣濃度低於1%之氮氣環境中,按表5所示之燒結溫度及燒結時間施行燒結而得到燒結體。又按,燒結時間中之0 hr係表示燒結時間超過0且未滿1小時者。
將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果示於表5中。在試料編號之旁邊附加有*記號者為比較例。No.16之試料係將No.14之試料在1000℃溫度下在空氣中施行熱處理者。再者,關於No.6之試料,施行Bi及Na之成分分析,以求出Bi/Na之比率。得到之Bi/Na之比率為1.00。
(比較例3)
準備BaCO3 、TiO2 (充作主要原料)、La2 O3 (充作半導體化元素)、Na2 CO3 、Bi2 O3 、以及TiO2 (充作居里溫度之移位劑),以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式將構成組成物之全部成分在煅燒前(原料摻配階段)摻配,在乙醇中混合。將所得之原料粉末混合物在氮氣中且在1000℃溫度下煅燒4小時,而得到煅燒粉。
將所得之煅燒粉在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在氧氣濃度低於1%之氮氣環境中在1320℃溫度下燒結3小時而得到燒結體。將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果為如下:ρ 30(Ω cm)=602,Tc(℃)=154,電阻溫度係數(%/℃)=12。再者,施行所得燒結體之Bi及Na之成分分析,以求出Bi/Na之比率之結果,得到之Bi/Na為0.76。
由表5之結果顯然得知,將燒結步驟在氧氣濃度未滿1%之環境中在1290~1350℃燒結溫度下按未滿4小時之燒結時間施行時,可藉此保持低值之室溫比電阻之同時,提高高溫域(居里溫度以上)之電阻溫度係數。又,亦可抑制電阻溫度係數之變動。
再者,根據實施例4及比較例3之結果,由於將準備(BaLa)TiO3 煅燒粉之步驟及準備(BiNa)TiO3 煅燒粉之步驟各別分開施行,可使居里溫度上升之同時,可大幅降低室溫電阻率。此外,抑制Bi之揮發散失,在燒結後亦具有高度之Bi/Na比,因此抑制異相之產生,降低室溫電阻率之同時,抑制居里溫度之變動。依照比較例3之半導體瓷器組成物被認為由於發生多量之Bi之揮發散失而產生有異相,而結果為造成室溫電阻率之增高。
(實施例5)
將實施例4所得之(BaLa)TiO3 煅燒粉及(BiNa)TiO3 煅燒粉以可成為[(Bi0 . 5 Na0 . 5 )0 . 1 (Ba0 . 9 9 4 La0 . 0 0 6 )0 . 9 ]TiO3 之方式予以摻配,在乙醇為媒體之下藉罐磨機混合粉碎至煅燒粉混合物之大小達到0.9 μ m為止,然後使之乾燥。對該項煅燒粉混合物之粉碎粉添加混合PVA後,用造粒裝置進行造粒。將所得之造粒粉使用單軸壓縮裝置予以成形,其成形體在500℃溫度下脫除黏合劑後,在氧氣濃度未滿1%之氮氣環境中,按表2所示之燒結溫度及燒結時間施行燒結後,按表6所示之冷卻速度施行冷卻而得到燒結體。又按,表6之冷卻速度中之驟冷係依照冷卻速度超過550℃/hr之驟冷者。
將所得之燒結體按10mm×10mm×1mm之板狀予以加工而製成試片,對各試片使用電阻測量器在室溫至270℃之範圍測量電阻值之溫度變化。測量結果示於表6中。在試料編號之旁邊附加有*記號者為比較例。
由表6之結果顯然得知,將燒結步驟在氧氣濃度未滿1%之環境中,在1290~1350℃燒結溫度下,按滿足式△T≧25t(t=煅燒時間(hr),△T=燒結後之冷卻速度(℃/hr))之燒結時間施行燒結,繼之,按滿足前式之冷卻速度施行燒結後之冷卻時,可藉此保持低值之室溫比電阻之同時,提高高溫域(居里溫度以上)之電阻溫度係數。再者,亦可抑制電阻溫度係數之變動。
又按,在全部之實施例中,電阻溫度係數係依照下式求出者:TCR=(1nR1 -1nRc )×100/(T1 -Tc )Rc 為最大比電阻,Rc 為溫度Tc 時之比電阻,T1 為表示R1 之溫度,Tc 為居里溫度。
[產業上之可利用性]
由本發明得到之半導體瓷器組成物係最適於充作PTC熱阻體、PTC加熱器、PTC開關、溫度感測器等之材料。
圖1為展示依照本發明之半導體瓷器組成物之每一煅燒溫度之X射線繞射圖案之圖。
圖2為展示依照比較例之半導體瓷器組成物之每一煅燒溫度之X射線繞射圖案之圖。

Claims (13)

  1. 一種半導體瓷器組成物之製造方法,係製造組成式以[(BiNa)x (Ba1-y Ry )1-x ]TiO3 (其中,R為La、Dy、Eu、Gd、Y中之至少一種)表示,上述x、y滿足0<x≦0.2,0<y≦0.02之半導體瓷器組成物者,其特徵為包含:準備(BaR)TiO3 煅燒粉(其中,R為La、Dy、Eu、Gd、Y中之至少一種)之步驟;準備(BiNa)TiO3 煅燒粉之步驟;使(BaR)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟;以及將此混合煅燒粉予以成形、燒結之步驟,上述(BaR)TiO3 煅燒粉之煅燒溫度為900℃~1300℃,上述(BiNa)TiO3 煅燒粉之煅燒溫度為700℃~950℃,上述(BiNa)TiO3 之煅燒溫度係低於上述(BaR)TiO3 煅燒粉之煅燒溫度,上述燒結係在氧濃度未滿1%之惰性氣體環境中施行。
  2. 如申請專利範圍第1項之半導體瓷器組成物之製造方法,其中,在使(BaR)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟中,以乾式施行混合。
  3. 如申請專利範圍第1項之半導體瓷器組成物之製造方法,其中,在準備(BaR)TiO3 煅燒粉之步驟或準備(BiNa)TiO3 煅燒粉之步驟中或此等兩步驟中,在煅燒前添加Si氧化物3.0 mol%以下、Ca碳酸鹽或Ca氧化物4.0 mol%以下。
  4. 如申請專利範圍第1項之半導體瓷器組成物之製造方法,其中,在使(BaR)TiO3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟中,添加Si氧化物3.0 mol%以下、Ca碳酸鹽或Ca氧化物4.0 mol%以下。
  5. 一種半導體瓷器組成物之製造方法,係製造組成式以[(BiNa)x Ba1-x ][Ti1-z Mz ]O3 (其中,M為Nb、Ta、Sb中之至少一種)表示,上述x、z滿足0<x≦0.2,0<z≦0.005之半導體瓷器組成物者,其特徵為包含:準備Ba(TiM)O3 煅燒粉(其中,M為Nb、Ta、Sb中之至少一種)之步驟;準備(BiNa)TiO3 煅燒粉之步驟;使Ba(TiM)O3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟;以及將此混合煅燒粉予以成形、燒結之步驟,上述Ba(TiM)O3 煅燒粉之煅燒溫度為900℃~1300℃,上述(BiNa)TiO3 煅燒粉之煅燒溫度為700℃~950℃,上述(BiNa)TiO3 之煅燒溫度係低於上述Ba(TiM)O3 之煅燒溫度,上述燒結係在氧濃度未滿1%之惰性氣體環境中施行。
  6. 如申請專利範圍第5項之半導體瓷器組成物之製造方法,其中,在使Ba(TiM)O3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟中,以乾式施行混合。
  7. 如申請專利範圍第5項之半導體瓷器組成物之製造方法,其中,在準備Ba(TiM)O3 煅燒粉之步驟或準備 (BiNa)TiO3 煅燒粉之步驟中或此等兩步驟中,在煅燒前添加Si氧化物3.0 mol%以下、Ca碳酸鹽或Ca氧化物4.0 mol%以下。
  8. 如申請專利範圍第5項之半導體瓷器組成物之製造方法,其中,在使Ba(TiM)O3 煅燒粉與(BiNa)TiO3 煅燒粉混合之步驟中,添加Si氧化物3.0 mol%以下、Ca碳酸鹽或Ca氧化物4.0 mol%以下。
  9. 如申請專利範圍第1或5項之半導體瓷器組成物之製造方法,其中,燒結步驟係在1290℃~1350℃燒結溫度下以未滿4小時之燒結時間施行。
  10. 如申請專利範圍第1或5項之半導體瓷器組成物之製造方法,其中,在1290℃~1350℃之燒結溫度下,以滿足下式之燒結時間施行燒結步驟,繼之以滿足下式之冷卻速度施行燒結後之冷卻:式:△T≧25t式中,t=燒結時間(hr),△T=燒結後之冷卻速度(℃/hr)。
  11. 如申請專利範圍第1或5項之半導體瓷器組成物之製造方法,其中,Bi與Na之比滿足Bi/Na=0.78~1之關係。
  12. 一種半導體瓷器組成物,係由(BaR)TiO3 煅燒粉(R為半導體化元素,係La、Dy、Eu、Gd、Y中之至少一種)與(BiNa)TiO3 煅燒粉之混合煅燒粉經成形、燒結所得之半導體瓷器組成物,組成式以[(BiNa)x (Ba1-y Ry )1-x ]TiO3 表示,上述x、y滿足0<x≦0.2,0<y≦0.02,Bi與Na之 比滿足Bi/Na=0.78~1之關係。
  13. 一種半導體瓷器組成物,係由Ba(TiM)O3 煅燒粉(M為半導體化元素,係Nb、Ta、Sb中之至少一種)與(BiNa)TiO3 煅燒粉之混合煅燒粉經成形、燒結所得之半導體瓷器組成物,組成式以[(BiNa)x Ba1-x ][Ti1-z Mz ]O3 表示,上述x、z滿足0<x≦0.2,0<z≦0.005,Bi與Na之比滿足Bi/Na=0.78~1之關係。
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