TWI387875B - Interface circuit for ddc - Google Patents

Description

DDC interface circuit

The invention relates to a DDC (Display Data Channel) interface circuit on a motherboard.

For video display devices, DDC is used to exchange monitor attribute information (optimal resolution, etc.) between a device that outputs video signals (such as a host) and a video display device (such as a computer monitor), thereby enabling the host to monitor The properties of the device are automatically set. In the DDC, the attribute information of the monitor is exchanged in the form of formatted EDID (Extended Display ID) data. Since the EDID data is related to the resolution of the monitor, when the host cannot obtain the EDID data of the monitor, the monitor will be black. In the prior art, the level of the ACK (Automatic Color Killer) signal sent by the monitor to the motherboard is too high, and the board is determined to be inactive by exceeding the specified low level range, thereby causing the host to The board cannot read the EDID data of the monitor.

In view of the above, it is necessary to provide a DDC interface circuit to ensure that the motherboard can obtain the EDID data of the monitor.

A DDC interface circuit includes a first NMOS field effect transistor, a second NMOS field effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The gate of the first NMOS field effect transistor is connected to a 3.3V system voltage through the first resistor, and the source thereof is connected to the data of the north bridge of the motherboard to display the channel clock pin, and the gate is transparent. The second resistor is connected to a 5V system voltage, and the fourth resistor is connected to the serial clock pin of the video graphics array interface circuit on the motherboard; the gate of the second NMOS field effect transistor is transmitted through the first resistor Connected to the 3.3V system voltage, the source is connected to the data of the north panel of the motherboard to display the channel data pin, and the drain is connected to the 5V system voltage through the third resistor, and the video graphic array interface circuit is connected through the fifth resistor. The data graphic array interface circuit is further connected to an automatic color erasing circuit of a monitor to receive an automatic color erasing signal and transmit the same to the north bridge of the motherboard through the DDC interface circuit.

Compared with the prior art, the DDC interface circuit is provided to the two NMOS field effect transistors connected between the north bridge of the motherboard and the monitor by dividing the 3.3V system voltage and the 5V system voltage through the resistor to make it normal. Turns on, ensuring that the auto-eliminating signal sent by the monitor can reach the motherboard, so that the motherboard obtains the EDID data of the monitor.

Referring to FIG. 1, a preferred embodiment of the DDC interface circuit of the present invention includes two NMOS field effect transistors Q1 and Q2, and five resistors R1, R2, R3, R4 and R5.

The gate of the NMOS field effect transistor Q1 is connected to a 3.3V_SYS (3.3V System, 3.3V system) voltage through the resistor R1, and the source is connected to a DDC_CLK (Display Data Channel Clock) of the North Bridge 100. The pin is connected to the 5V_SYS (5V system, 5V system) voltage through the resistor R2, and is connected to the SCL (Serial Clock, VGA (Video Graphics Array) interface circuit 300 on the motherboard through the resistor R4. string The column clock) pin; the gate of the NMOS field effect transistor Q2 is connected to the 3.3V_SYS voltage through the resistor R1, and the source thereof is connected to the DDC_DATA (Display Data Channel Data) pin of the north bridge 100. The drain is connected to the 5V_SYS voltage through the resistor R3, and is connected to the SDA (Serial Data) pin of the VGA interface circuit 300 through the resistor R5. The VGA interface circuit 300 is also connected to an ACK of the monitor 400 (Automatic The Color Killer circuit 10 receives an ACK signal and transmits it to the DDC interface circuit 200.

In the DDC interface circuit 200 of the present invention, the 3.3V_SYS voltage is supplied to the gates of the NMOS field effect transistors Q1 and Q2 through the resistor R1 to keep the NMOS field effect transistors Q1 and Q2 turned on; the 5V_SYS voltage is transmitted through the resistor R2. R3 is divided and supplied to the drains of the NMOS field effect transistors Q1 and Q2. The resistance values of the resistors R2 and R3 are between 9.5kΩ and 10.5kΩ. The ACK signal sent by the ACK circuit 10 inside the monitor 400 is transmitted to the north bridge 100 through the VGA interface circuit 300 and the DDC interface circuit 200. After the north bridge 100 determines that the received ACK signal is in the active low level range, the north bridge 100 sends a read command to the monitor 400 through the DDC interface circuit 200 and the VGA interface circuit 300, and the monitor 400 transmits the VGA interface circuit 300. The SDA pin and the DDC interface circuit 200 transmit the EDID data to the DDC_DATA pin of the north bridge 100. After obtaining the EDID data of the monitor 400, the north bridge 100 can control the normal display of the monitor 400. The VGA interface circuit 300 is configured to convert the digital signal outputted by the north bridge 100 into an analog signal to the monitor 400 or convert the analog signal output by the monitor 400 into a digital signal to the north bridge 100.

The DDC interface circuit 200 transmits the 3.3V_SYS voltage and the 5V_SYS voltage to the NMOS field effect transistors Q1 and Q2 between the north bridge 100 and the monitor 400 through the resistors R1, R2, and R3, respectively, to be normally turned on, thereby ensuring the monitor 400. The transmitted ACK signal can reach the North Bridge 100, so that the motherboard obtains the EDID data of the monitor 400.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100‧‧‧ North Bridge

200‧‧‧DDC interface circuit

300‧‧‧VGA interface circuit

400‧‧‧ monitor

10‧‧‧ACK circuit

R1~R5‧‧‧ resistance

Q1, Q2‧‧‧ NMOS field effect transistor

1 is a circuit diagram of a preferred embodiment of a DDC interface circuit of the present invention.

100‧‧‧ North Bridge

200‧‧‧DDC interface circuit

300‧‧‧VGA interface circuit

400‧‧‧ monitor

10‧‧‧ACK circuit

R1~R5‧‧‧ resistance

Q1, Q2‧‧‧ NMOS field effect transistor

Claims (2)

A DDC interface circuit includes a first NMOS field effect transistor, a second NMOS field effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The gate of the first NMOS field effect transistor is connected to a 3.3V system voltage through the first resistor, and the source thereof is connected to the data of the north bridge of the motherboard to display the channel clock pin, and the drain of the first NMOS field is connected to the 5V system voltage through the second resistor. And connecting, by the fourth resistor, the serial clock pin of the video graphics array on the motherboard; the gate of the second NMOS field effect transistor is connected to the 3.3V system voltage through the first resistor, and the source is connected to the host The data of the board north bridge shows the channel data pin, the drain of which is connected to the 5V system voltage through the third resistor, and the serial data pin of the video graphics array interface circuit is connected through the fifth resistor, the video graphics array interface circuit It is also coupled to an automatic color erasing circuit of a monitor to receive an automatic achromatic signal and transmit it to the north bridge of the motherboard through the DDC circuit. The DDC interface circuit of claim 1, wherein the resistance values of the second resistor and the third resistor are between 9.5 kΩ and 10.5 kΩ.