TWI386981B - Nitride semiconductor structure and method for manufacturing the same - Google Patents

Description

Nitride semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a nitride semiconductor structure and a method of fabricating the same.

In recent years, light-emitting diodes (LEDs) and lasers (LDs) have been widely used in the market. For example, a combination of blue light and yellow fluorescent powder made of gallium nitride (GaN) can obtain white light, not only in brightness. Or the power consumption is brighter than the previous traditional light source and saves power, which can greatly reduce the power consumption. In addition, the life of the light-emitting diode is about tens of thousands of hours, and the life is longer than that of the conventional light bulb.

In the manufacturing process of a gallium nitride semiconductor light-emitting device, due to the difference in lattice constant and thermal expansion coefficient between the gallium nitride semiconductor layer and the hetero-substrate, the gallium nitride semiconductor is likely to cause a penetrating dislocation during the epitaxial process. The problem of thermal stress, thus affecting the luminous efficiency of the light-emitting element.

The method for separating a gallium nitride semiconductor layer and a heterogeneous substrate includes using an illumination method to cause laser light to penetrate the interface between the substrate and the gallium nitride semiconductor layer to achieve separation of the gallium nitride semiconductor layer and the heterogeneous substrate. purpose. In addition, the barrier structure between the substrate and the gallium nitride semiconductor layer can be directly removed by a wet etching method to weaken the connection structure between the gallium nitride semiconductor layer and the heterogeneous substrate, thereby separating and nitriding. A gallium semiconductor layer and a heterogeneous substrate. In addition, the interface layer between the gallium nitride semiconductor layer and the heterogeneous substrate can be directly removed by vapor phase etching at a high temperature to achieve the purpose of separating the gallium nitride semiconductor layer and the heterogeneous substrate.

PCT Patent Publication No. WO2007/107757 discloses a method of adjusting epitaxial parameters, as shown in FIG. 1, epitaxial directly on the surface of the hetero-substrate 100 to form gallium nitride nano-nitride on the nitride layer 101. GaN nanocolumn 102. Thereafter, the gallium nitride nano-column 102 is used as a seed crystal to perform lateral epitaxial growth to form a thick-film gallium nitride semiconductor layer 104, and then a cooling process is performed to cause the interface between the gallium nitride semiconductor layer 104 and the hetero-substrate 100 to be cracked. After the crack, a mechanical force is applied to separate the gallium nitride semiconductor layer 104 from the hetero-substrate 100 to form a thick film of gallium nitride.

One embodiment of the present invention provides a nitride semiconductor substrate including an epitaxial substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor film layer, and a mask layer. The nitride semiconductor pillar layer includes a plurality of patterned first cavity structures and a plurality of patterned second cavity structures formed between the first cavity structures, wherein the second cavity structure is of a nanometer size. The nitride semiconductor pillar layer is formed on the epitaxial substrate, and the nitride semiconductor film layer is formed on the nitride semiconductor pillar layer. The mask layer covers the surface of the nitride semiconductor pillar layer and the epitaxial substrate.

Another embodiment of the present invention provides a method of fabricating a nitride semiconductor substrate, comprising: forming a patterned nitride semiconductor pillar layer on a surface of an epitaxial substrate having a plurality of patterned first void structures and located A plurality of second void structures patterned in a pattern between the first void structures, wherein the second void structures are nanometer in size. Next, a mask layer is formed on the sidewall of the nitride semiconductor pillar layer and the surface of the epitaxial substrate, and an epitaxial lateral over growth (ELOG) is performed by using the nitride semiconductor pillar layer as a seed crystal to form a mask. Nitride semiconductor film layer.

In order to make the present invention more apparent, the following detailed description of the embodiments and the accompanying drawings are set forth below.

2A is a schematic cross-sectional view of a nitride semiconductor substrate in accordance with an embodiment of the present invention.

Referring to FIG. 2A, the nitride semiconductor substrate 200 includes an epitaxial substrate 202, a patterned nitride semiconductor pillar layer 204, a nitride semiconductor film layer 206, and a mask layer 208. The nitride semiconductor pillar layer 204 is composed of a plurality of patterned first void structures 210 and a plurality of patterned second void structures 212, wherein the second void structure 212 is of a nanometer size; for example, The height of the second cavity structure 212 is, for example, between 1 μm and 5 μm, and the width of the second cavity structure 212 is, for example, between 30 nm and 500 nm. The height of the first void structure 210 is, for example, between 1 μm and 10 μm. The size ratio disclosed herein is only one embodiment, and does not impose any limitation on the application of the present invention. It can be accomplished by those having ordinary knowledge in the technical field of the present invention, which can be appropriately adjusted according to actual conditions. In addition, the first cavity structure 210 is a periodically arranged structure, and the second cavity structure 212 may be a regular arrangement or a random arrangement. Moreover, the arrangement of the first hollow structures 210 may be arranged in a strip shape, a dot shape or a mesh shape as a whole.

The material of the epitaxial substrate 202 is, for example, sapphire, tantalum carbide, niobium, gallium arsenide or the like or other substrate material suitable for epitaxial processing. The material of the nitride semiconductor pillar layer 204 is a nitride semiconductor such as gallium nitride, aluminum nitride, aluminum gallium nitride, indium nitride, indium gallium nitride or aluminum gallium nitride. The nitride semiconductor pillar layer 204 is formed on the epitaxial substrate 202, the entire nitride semiconductor film layer 206 is formed on the nitride semiconductor pillar layer 204, and the mask layer 208 covers the nitride semiconductor pillar layer 204 and the pillar. The surface of the crystal substrate 202. The material of the mask layer may be a dielectric material such as hafnium oxide or tantalum nitride.

Furthermore, the nitride semiconductor film layer 206 can be formed into a thick film or a film according to actual requirements, for example, when the thickness of the nitride semiconductor film layer 206 is greater than 50 μm, a nitrogen can be formed by a separation process 214. The semiconductor substrate is a separate substrate, including a nitride semiconductor film layer 206, a nitride semiconductor pillar layer 204, and a mask layer 208 on its surface, as shown in FIG. 2B.

In the above, the pitch a1 of the first cavity structure 210 and the width a2 thereof (as shown in FIG. 2A) can be achieved by photolithography and etching to meet the size required by the separation process 214; The height h of the two-hole structure 212 and its width b may be irregular nano-sized structures. For convenience of explanation, the ratio of the distance a1 to the width a2 between the first hollow structures 210 is defined as a fill factor (FF), that is, FF=a1/a2. For example, in this embodiment (for example, 1); and the height h of the second cavity structure 212 may be 1 μm. The size ratio of the layers disclosed herein is only one embodiment, and does not impose any limitation on the application of the present invention. This is a general knowledge in the technical field to which the present invention pertains, and the existing technology can be appropriately adjusted according to actual conditions. For example, the range of a1 is between 1 μm and 10 μm, preferably between 1 μm and 5 μm; and b is, for example, between 30 nm and 500 nm, preferably between 30 nm and 300 nm.

Referring to FIG. 2B again, when the thickness of the subsequent nitride semiconductor film layer 206 is thick enough to accumulate sufficient strength, the epitaxial substrate 202 and the nitride semiconductor pillar are removed from the epitaxial temperature to the room temperature at the ambient temperature. The difference in thermal expansion coefficient of the layer 204 heterogeneous material is naturally separated into a nitride semiconductor independent substrate where the inter-interface strength is the weakest, that is, for example, the interface between the patterned nitride semiconductor pillar layer 204 and the epitaxial substrate 202 is naturally separated.

In addition, if the nitride semiconductor film layer 206 is used as a thin film (for example, having a thickness of less than 50 μm), the nitride semiconductor substrate 200 of FIG. 2A can be used as a nitride template, and is also permeable to FF. Value and h design, for example , In order to achieve a reduction in the density of the dislocations without causing the nitride semiconductor film layer 206 to crack.

3A to 3H are cross-sectional views showing the manufacturing process of the present invention.

First, referring to FIG. 3A, a layer of nitride semiconductor material 302 is formed on the surface of the epitaxial substrate 300. The material of the epitaxial substrate 300 is sapphire, tantalum carbide, niobium, gallium arsenide, etc. or other suitable for epitaxial processing. Substrate material. The thickness of the nitride semiconductor material layer 302 is, for example, between 1 μm and 10 μm. Further, a method of forming the nitride semiconductor material layer 302 on the surface of the epitaxial substrate 300 is, for example, hydride vapor phase epitaxy (HVPE), metal organic vapor phase epitaxy (MOCVD) or molecular beam epitaxy (MBE). Next, a layer of photoresist 304 is formed on the nitride semiconductor material layer 302.

Then, referring to FIG. 3B, the photoresist 304 is developed using a technique such as optical lithography to form a patterned photoresist 304a exposing a portion of the surface of the nitride semiconductor material layer 302. Thereafter, the nitride semiconductor material layer 302 is removed by etching using a patterned photoresist 304a using an etching method such as RIE or ICP to form a nitride semiconductor pattern layer 306. A portion of the epitaxial substrate 300 may also be removed during the step of removing the nitride semiconductor material layer 302.

Next, referring to FIG. 3C, the patterned photoresist 304a is removed first (as shown in FIG. 3B), and a sacrificial mask layer 308 is formed on the surface of the nitride semiconductor pattern layer 306 and the epitaxial substrate 300 to cover the nitride semiconductor pattern layer 306. surface. The sacrificial mask layer 308 can be a dielectric material such as hafnium oxide or tantalum nitride.

Subsequently, referring to FIG. 3D, a metal film 310 is formed on the surface of the sacrificial mask layer 308 (excluding the sidewall of the sacrificial mask layer 308), and the metal film 310 in this embodiment is exemplified by metallic nickel.

Next, referring to FIG. 3E, a high temperature annealing process (for example, 850 ° C) is performed to automatically integrate the metal film 310 into a spherical metal having a radius of, for example, 30 nm to 500 nm due to the difference in surface tension of the heterogeneous material, and the sacrificial cover. A patterned mask layer 312 (i.e., spherical metal) is formed on the surface of the curtain layer 308, wherein the patterned mask layer 312 has a nano-sized pattern.

Then, referring to FIG. 3F, the mask layer 312 is patterned as a mask, and the sacrificial mask layer 308 and the nitride semiconductor pattern layer 306 are etched by an anisotropic etching process such as RIE or ICP to obtain a plurality of patterns. The aligned third cavity structure 314 and the plurality of nitride semiconductor pillar layers 306a of the patterned fourth cavity structure 316. The material of the nitride semiconductor pillar layer 306a is, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, indium nitride, indium gallium nitride or aluminum gallium nitride. Thereafter, the sacrificial mask layer 308 and the patterned mask layer 312 are removed.

Next, referring to FIG. 3G, a mask layer 318 is formed on the sidewall of the nitride semiconductor pillar layer 306a and the surface of the epitaxial substrate 300 to form a fifth void structure 314' and a sixth void structure 316' of the figure. For example, the mask layer 318 may be formed by first forming a dielectric film covering the surface of the nitride semiconductor pillar layer 306a and the epitaxial substrate 300, and then removing the top surface of the nitride semiconductor pillar layer 306a. The electric film, wherein the material of the mask layer 318 can be a dielectric material such as tantalum oxide or tantalum nitride.

Then, referring to FIG. 3H, a side-by-side epitaxial process is performed using the nitride semiconductor pillar layer 306a as a seed crystal to form a nitride semiconductor film layer 320, such as gallium nitride, aluminum nitride, indium nitride, or the like. Indium gallium nitride, aluminum gallium nitride or aluminum gallium indium nitride. The above lateral epitaxial process is, for example, a hydride vapor phase epitaxy method, a metal organic vapor phase epitaxy method or a molecular beam epitaxy method.

When the thickness of the nitride semiconductor film layer 320 is 50 μm or more, it is optional to provide a cooling process to release the shear stress caused by the difference in thermal expansion coefficient between the nitride semiconductor film layers 320, so that the inter-interface strength is the weakest. The place such as the nitride semiconductor film layer 320 and the nitride semiconductor pillar layer 306a are naturally separated as shown in FIG.

In one embodiment of the present invention, a nitride semiconductor pillar layer formed by a plurality of patterned first cavity structures and a second cavity structure having a nanometer size is formed, and a nitride-transmissive nitride semiconductor film is permeable to a nitride. The semiconductor pillar layer is grown in a lateral epitaxial manner to reduce the misalignment distribution of the epitaxial layer, and the first and second void structures can also release material stress and thermal stress to avoid cracking and cause luminous efficiency of the nitride semiconductor layer. Damage; if the nitride semiconductor thick film is grown, in addition to reducing the misalignment of the epitaxial layer, the patterned nitride semiconductor pillar layer provides a natural separation process during the cooling process, causing thermal expansion between the heterogeneous materials. The shear stress caused by the difference in coefficients is released, and the interface with the weakest strength is naturally broken to separate into a nitride semiconductor freestanding substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art to which the present invention pertains may be modified and retouched without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 202, 300. . . Epitaxial substrate

101. . . Nitride layer

102. . . Gallium nitride nano column

104. . . Gallium nitride semiconductor layer

200. . . Nitride semiconductor substrate

204, 306a. . . Nitride semiconductor pillar

206, 320. . . Nitride semiconductor film layer

208, 318. . . Mask layer

210. . . First void structure

212. . . Second hollow structure

314. . . Third hollow structure

316. . . Fourth void structure

314’. . . Fifth hollow structure

316’. . . Sixth hollow structure

214. . . Separation process

302. . . Nitride semiconductor material layer

304. . . Photoresist

304a. . . Patterned photoresist

306. . . Nitride semiconductor pattern layer

308. . . Sacrificial mask layer

310. . . Metal film

312. . . Patterned mask layer

A1. . . spacing

A2, b. . . width

h. . . height

1 is a schematic cross-sectional view of a conventional nitride semiconductor substrate.

2A is a schematic cross-sectional view of a nitride semiconductor substrate in accordance with the present invention.

2B is a schematic view showing a nitride semiconductor independent substrate formed by the separation process of the nitride semiconductor substrate of FIG. 2A.

3A to 3H are cross-sectional views showing a manufacturing process of a nitride semiconductor substrate according to the present invention.

Figure 3I is a cross-sectional view showing the manufacturing process of a nitride semiconductor independent substrate according to the present invention.

200. . . Nitride semiconductor substrate

202. . . Epitaxial substrate

204. . . Nitride semiconductor pillar

206. . . Nitride semiconductor film layer

208. . . Mask layer

210. . . First void structure

212. . . Second hollow structure

A1. . . spacing

A2, b. . . width

Claims (24)

A nitride semiconductor substrate comprising: an epitaxial substrate; a patterned nitride semiconductor pillar layer formed on the epitaxial substrate; a nitride semiconductor film layer formed on the nitride semiconductor pillar layer; and a a mask layer covering the surface of the nitride semiconductor pillar layer and the epitaxial substrate, wherein the nitride semiconductor pillar layer comprises: a plurality of patterned first cavity structures; and a plurality of patterned second holes The structure is located between the first hollow structures of the patterned arrangement, wherein the second hollow structures are of a nanometer size. The nitride semiconductor substrate according to claim 1, wherein the material of the nitride semiconductor film layer comprises gallium nitride, aluminum nitride, indium nitride, gallium indium nitride, aluminum gallium nitride or aluminum nitride. Gallium indium. The nitride semiconductor substrate according to claim 1, wherein the first cavity structure has a height of between 1 μm and 10 μm. The nitride semiconductor substrate according to claim 1, wherein the second cavity structure has a width of between 30 nm and 500 nm. The nitride semiconductor substrate according to claim 1, wherein a ratio of a distance between the first cavity structures and a width is FF, and . The nitride semiconductor substrate according to claim 1, wherein the material of the nitride semiconductor pillar layer comprises gallium nitride, aluminum nitride, aluminum gallium nitride, indium nitride, indium gallium nitride or aluminum nitride. Gallium indium. The nitride semiconductor substrate according to claim 1, wherein the material of the epitaxial substrate comprises sapphire, tantalum carbide, niobium or gallium arsenide. The nitride semiconductor substrate of claim 1, wherein the first void structures are periodically arranged structures. The nitride semiconductor substrate according to claim 1, wherein the second hollow structures are regularly arranged or irregularly arranged. The nitride semiconductor substrate according to claim 1, wherein the first hollow structures are arranged in a strip shape, a dot shape or a mesh shape. The nitride semiconductor substrate of claim 1, wherein the material of the mask layer comprises a dielectric material. A method for fabricating a nitride semiconductor substrate, comprising: forming a patterned nitride semiconductor pillar layer on an epitaxial substrate surface, the nitride semiconductor pillar layer having a plurality of first void structures and located in the first void structures a plurality of second void structures between the patterned arrays, wherein the second void structures are nanometer-sized; a sidewall layer is formed on sidewalls of the nitride semiconductor pillar layer and the surface of the epitaxial substrate; The nitride semiconductor pillar layer is subjected to a side-by-side epitaxial process for the seed crystal to form a nitride semiconductor film layer. The method for fabricating a nitride semiconductor substrate according to claim 12, wherein the step of forming the nitride semiconductor pillar layer comprises: forming a nitride semiconductor material layer on the surface of the epitaxial substrate; and the nitride semiconductor material Forming a patterned photoresist on the layer and exposing a portion of the surface of the nitride semiconductor material layer; removing the nitride semiconductor material layer to form a nitride semiconductor pattern layer by using the patterned photoresist as a mask; Forming a sacrificial mask layer on the surface of the epitaxial substrate to cover a surface of the nitride semiconductor pattern layer; forming a patterned mask layer on the surface of the sacrificial mask layer, wherein the patterned mask layer a pattern having a nanometer size; etching the sacrificial mask layer and the nitride semiconductor pattern layer with the patterned mask layer as a mask; and removing the sacrificial mask layer and the patterned mask layer. The method of fabricating a nitride semiconductor substrate according to claim 13, wherein the step of removing the nitride semiconductor material layer comprises removing a portion of the epitaxial substrate. The method for fabricating a nitride semiconductor substrate according to claim 13, wherein the step of removing the nitride semiconductor material layer further comprises removing the patterned photoresist. The method for fabricating a nitride semiconductor substrate according to claim 13, wherein the method for forming the nitride semiconductor material layer on the surface of the epitaxial substrate comprises hydride vapor phase epitaxy (HVPE), metal organic gas phase Epitaxial method (MOCVD) or molecular beam epitaxy (MBE). The method for manufacturing a nitride semiconductor substrate according to claim 13, wherein the step of forming the patterned mask layer comprises: forming a metal film on the surface of the sacrificial mask layer; and performing a high temperature annealing process to enable The metal film automatically aggregates into a plurality of spherical metals due to the difference in surface tension of the heterogeneous material. The method for producing a nitride semiconductor substrate according to claim 17, wherein the spherical metal has a radius of between 30 nm and 500 nm. The method for fabricating a nitride semiconductor substrate according to claim 12, wherein the step of forming the mask layer comprises: forming a dielectric film comprehensively, covering the nitride semiconductor pillar layer and the portion of the epitaxial substrate a surface; and removing the dielectric film on the top surface of the nitride semiconductor pillar layer. The method for fabricating a nitride semiconductor substrate according to claim 12, wherein the forming of the nitride semiconductor film layer further comprises providing a temperature lowering process to separate the nitride semiconductor film layer from the surface of the epitaxial substrate. The method for fabricating a nitride semiconductor substrate according to claim 12, wherein the lateral epitaxial process comprises a hydride vapor phase epitaxy method, a metal organic vapor phase epitaxy method or a molecular beam epitaxy method. The method for fabricating a nitride semiconductor substrate according to claim 12, wherein the material of the nitride semiconductor pillar layer comprises gallium nitride, aluminum nitride, aluminum gallium nitride, indium nitride, indium gallium nitride or Aluminum gallium indium nitride. The method of manufacturing a nitride semiconductor substrate according to claim 12, wherein the material of the mask layer comprises a dielectric material. The method for producing a nitride semiconductor substrate according to claim 12, wherein the nitride semiconductor film layer and the epitaxial substrate have different thermal expansion coefficients.