1360220 九、發明說明： 本發明主張已分別於2006年〇3月31日與2006年12月08 日申請之韓國專利申請第10-2006-0029870號及第 10-2006-0124736號案件的優先權，於此隨附其全文以供參考》 【發明所屬之技術領域】 本發明係關於半導體元件，特別是關於具有增加通道 面積的半導體元件及其製造方法。 【先前技術】 —般對於半導體元件來說，由於微型化已提升了設計 標準’因此通道區域中硼的濃度亦隨之增加，這造成了電 場的增加，這種情形在動態隨機存取記憶體（DRAM)胞元以 及平面型 N-通道金屬-氧化物半導體場效應電晶體 (NMOSFETs)之中特別地明顯。因此，時常難以獲得一可接 受的更新時間。 由於半導體元件（諸如DRAMs)之積體化的大尺寸的緣 故，當參雜濃度趨於增加時，特徵尺寸便趨於減少。此一 增加會引發半導體元件之電場的增加；然而，電場的增加 亦會增加接面漏電。 此外，由於通道長度與寬度常受到限制，因此通道參 雜便日益增加地被施加以滿足所需技術特徵。其結果爲， 電子的遷移率便可能減少，此一遷移率的減少使人難以獲 得通過通道的所需電流流量。 第1A圖係爲具有傳統平面式NM0SFET之半導體元件 的上視圖，第1B圖係爲第1A圖的半導體元件中沿A-A’ 切割之平面的剖面圖。一淺溝槽隔離（STI)製程被執行於基 板11的一區域上以形成一隔離結構12(例如，場氧化物 1360220 層），一閘極氧化物層13被形成於由隔離結構12所定義之 基板11的主動式區域11A之上。平面型閘極PG係形成於 閘極氧化物層13上，其中每一個平面型閘極PG皆包括一 閘極電極1 4以及一閘極硬式遮罩1 5，二者係依照此一順 序而彼此相堆疊。在此主動式區域11A中，N-型源極與汲 極區域S與D係形成於每一個平面型閘極PG的兩側上。 如前所陳述與說明者，由於平面型閘極PG係形成於 基板11之主動式區域11A的平坦表面之上，它們常被稱爲 具有平面通道的NMOSFETs。然而，由於大尺寸積體化的 緣故，平面型電晶體結構常常難以獲得所需之通道長度與 寬度，因此，一短（或窄）通道效應可能不會被免除。 凹入通道陣列電晶體（RCATs)或FinFETs常被用來克 服上述限制。雖然這些常用的電晶體結構能夠藉由使用主 動式區域的三個表面而增加通道面積，但是這些結構仍然 會因爲高度積體化而不足以增加通道面積至某一程度。 【發明內容】 本發明的特定實施例提供一種能夠最大化通道面積的 半導體元件及其製造方法。 根據本發明的一方面，提供一種半導體元件，包括：_ 三維主動式區域，包括一頂層、兩側及一底層表面；一閘 極絕緣層，形成於該主動式區域之該頂層、兩側及底層表 面的附近；及閘極電極，形成於環繞該主動式區域的該閘 極絕緣層上方。 根據本發明的另一方面，提供一種半導體元件的製造 方法，包括：於一基板內形成溝槽’，該等溝槽定義出該基 板的主動式區域；蝕刻該等溝槽下方的該基板，以形成在 1360220 Λ 板的主動式區域；蝕刻該等溝槽下方的該基板，以形成在 一方向上連接於該等溝槽且提供支撐該主動式區域之柱狀 物的第一凹入；形成同時塡入該第一凹入及該等溝槽的一 隔離結構；鈾刻該基板及該隔離結構的部份，以形成曝露 出該主動式區域之一頂層表面、兩側表面及一底層表面的 第二凹入；形成一閘極絕緣層於所曝露之該主動式區域的 該頂層、兩側及底層表面的上方；及形成閘極電極於該閘 極絕緣層上方以環繞該主動式區域。 在一實施例中，半導體元件的製造方法包括形成主動 式區域於一基板上，該主動式區域具有定義出第一、第二、 第三及第四通道的第一、第二、第三及第四表面，一閘極 ' 絕緣層係形成於該主動式區域的附近以隔離該第一、第 二、第三及第四表面，一閘極電極係形成於該閘極絕緣層 及該主動式區域之該第一、第二、第三及第四表面的附近， 該閘極電極係用以控制在該第一、第二、第三及第四通道 中流動的電流，該主動式區域的該第一、第二、第三及第 四表面係被連接以定義出一實體多邊形結構，該多邊形的 轉角可以是圓形。 【實施方式】 第2Α圖係爲根據本發明一實施例之半導體元件的側 視圖，第2Β圖係爲根據本發明一實施例之半導體元件的剖 面圖。該半導體元件結構具有主軸與副軸，主動式區域100 具有包括一頂層表面101、兩側表面102及一底層表面 的四個表面，環形閘極電極32係如同第2Α圖般地形成於 主動式區域100的該等表面上，閘極電極32包括多晶矽。 柱狀物27Α係形成於主動式區域1〇〇的一中央區域中 1360220 —環形，因此存在四個通道，其係圍繞主動式區域100的 四個表面。該環形可以視應用場所而具有實體的具角度之 轉角或是實體的圓形轉角。 第2B圖顯示沿副及主軸方向之切割平面的剖面圖。元 件符號21、26、28及3 1係分別代表一基板、一間隙壁、 一隔離結構（例如，場氧化層）以及一閘極絕緣層（例如，氧 化層），該等通道的方向將藉由參考第4C圖而於之後詳細 說明。根據本發明，由於主動式·區域100的四個表面被用 來當作通道，因此該半導體元件的通道面積便可被增加至 相較傳統的RCATs與FinFETs更大的程度。 第3A至3G圖係爲本發明另一實施例之半導體元件的 製造方法的剖面圖。第3A至3F圖中左側的剖面圖所顯示 者爲沿主動式區域300之副軸方向的切割平面，而右側的 剖面圖所顯示者爲沿主動式區域300之主軸方向的切割平 面。 請參閱第3A圖，墊氧化層232及墊氮化層23 3係形成 於一基板231上方，基板231包括具有某一量之雜的一矽 基板。墊氧化層232係形成成爲約50A至150A的厚度，且 墊氮化層233係形成成爲約1000A至2000A的厚度。 光阻層係被塗佈於墊氮化層233上並經由微影製程而 被圖案化以形成 STI遮罩 234，該光阻層包括具有 cycloolefin-maleic anhydride(COMA)或是丙烯的聚合物材 質’ STI遮罩234係形成成爲從頂層看過去爲條形或是，τ’ 形。雖然未經說明，但在形成STI遮罩234之前，抗反射 性塗佈層還會被形成，藉以防止該微影製程期間的散射效 1360220 應。該抗反射性塗佈層可包括氮化氧矽（SiON)材質。 墊氮化層233及墊氧化層232係使用STI遮罩234作 爲蝕刻遮罩而被蝕刻，且基板231會被蝕刻至某一深度。 其結果爲，溝槽23 5會被隔離地形成。考慮到後續的濕鋪 刻及氧化作用，每一溝槽的深度皆處於約1000 A至2000 A 的範圍內。溝槽23 5係爲用以被當作一隔離結構的區域， 且係用以定義主動式區域300。 請參閱第3B圖，STI遮罩234係使用氧氣電漿而被移 除，間隙壁23 6係同時形成於溝槽235的側壁以及包括墊 氮化層23 3及墊氧化層23 2的堆疊圖案結構之上。間隙壁 23 6係藉由沉積氮化層（未顯示）於第3A圖中的所成結構 上、並且於其上執行一回蝕刻製程而被形成。 請參閱第3C圖，等向性蝕刻係使用間隙壁236作爲蝕 刻遮罩而被執行，氯化氫（HC1)蒸氣被用來執行該蝕刻。此 等向性蝕刻的結果爲，第一凹入237(或是水平隧道）的形成 係橫向地延伸至溝槽235的下方。當從主軸方向看過去時， 第一凹入237便會從個別溝槽235的底層部份而被由下方 切割。 主動式區域300在副軸方向上係短於在主軸方向上， 此一事實極爲重要的原因在於，在副軸方向上的兩個溝槽 235係爲足夠地接近以允許該等向性蝕刻將兩者連接，在主 軸方向上的溝槽235係爲足夠地遠離以允許基板231的柱 狀物237A殘留於中央。因此，主動式區域300便不會崩塌。 該等向性蝕刻係執行於保持氣壓於約2Torr至200T〇rr 的範圍內，且HC1蒸氣之流動率爲約lOOsccm至l〇〇〇sccm， 1360220 « 的範圍內，且HC1蒸氣之流動率爲約lOOsccm至lOOOsccm， 藉以調整蝕刻率及曲線。當HC1蒸氣被使用時，該等向性 蝕刻係執行於約700°C至1 000°C的溫度且持續約30秒至60 秒。 在使用HC1蒸氣的該等向性蝕刻之前，會執行預退火 處理於溫度範圍在約8 00 °C至1 000 °C的氫氣環境下，該預 退火處理的執行係用以移除外部材質。 請參閱第3D圖，將缺口塡入絕緣層塡入第一凹入23 7 及溝槽235，且執行化學機械硏磨以形成隔離結構23 8(例 如，場氧化層），該缺口塡入絕緣層包括氧化物材質。該STI CMP製程係如同習用之技術，且該硏磨停止在墊氮化層233 處，該缺口塡入絕緣層係藉由同時沉積而塡入第一凹入237 及溝槽23 5。替代方案爲，執行熱氧化處理於該缺口塡入絕 緣層上以塡入第一凹入2 37,並且接著執行高強度電漿（HDP) 處理以塡入溝槽2 35 » 請參閱第3E圖，使用磷酸（H3PO 〇溶液以選擇性地移除 墊氮化層233，將光阻層塗佈於殘留的墊氧化層232上方、 並且經由微影製程而被圖案化以形成光阻圖案2 39。光阻圖 案239包括諸如COMA或丙烯的一聚合物材質，光阻圖案 239並不會在副軸方向上被形成於殘留的墊氧化層232上 方。 由光阻圖案239所開放的那些開放區域239A係形成成 爲線形圖案，這些區域是後續待形成之閘極的所在地。因 此’由於開放區域239A的緣故，主動式區域300的一部份 以及墊氧化層2 32的一部份便會被曝露在主軸方向上的該 -10- 1360220 域3 00的該整個部份便會被曝露在副軸方向上。此處，主 動式區域300的該整個部份係爲僅位於副軸方向上的主動 式區域300 » 墊氧化層232係使用光阻圖案239作爲蝕刻遮罩而被 蝕刻，在墊氧化層23 2的蝕刻之後所曝露的隔離結構238 係被蝕刻藉以形成用於通道形成的第二凹入240。在副軸方 向上，墊氧化層232及隔離結構238會被蝕刻完畢。對於 向下蝕刻來說，一乾蝕刻會被執行直到到達第一凹入237 的地層（請參閱第3C圖），並且一濕蝕刻會被額外地執行於 橫向蝕刻。因此，使用光阻圖案239以蝕刻墊氧化層232 及隔離結構23 8會造成第二凹入240的形成，第二凹入240 係圍繞（或包圍）主動式區域300而成環形。 請參閱第3F圖，在第二凹入240中的間隙壁2 36被移 除，由於間隙壁236包括氮化物材質，因此可以使用H3P〇4 溶液於該移除。光阻圖案23 9被移除，並且接下來，殘留 於副軸方向上之主動式區域300上的墊氧化層232便會被 移除。 在墊氧化層232的移除之後，通道的四側301 ' 302、 303及3 04便會被曝露於完整的圓環3 04。 請參閱第3G圖，閘極絕緣層241係形成於在墊氧化層 23 2的移除之後所曝露的主動式區域300上方，閘極絕緣層 24 1包括氧化物材質、且其係藉由執行熱氧化處理或是沉積 方法而形成。更明確地說，熱處理之執行會使得閘極絕緣 層241在主動式區域300之曝露的表面上成長出統一厚 度。 -11- 1360220 度。 用來當作電晶體之閘極電極的多晶矽層係形成於閘極 絕緣層24 1上方直到塡入第二凹入24 0爲止。雖然未說明， 但具有低電阻及硬式遮罩層的金屬層係形成於多晶矽層 242上且被圖案化以形成閘極圖案，該金屬層及該硬式遮罩 層亦可以分別包括鎢以及氮化物材質。由於多晶砂層242 係圍繞於類似環狀的主動式區域300之四個曝露的表面， 四個通道便因此而形成。 第4A圖係爲根據本發明另一實施例所獲得之半導體 元件的側視圖，特別是，第4A圖顯示在主動式區域300與 閘極電極之間的結構配置（諸如多晶矽層242)。主動式區域 300包括四個曝露的表面亦即頂層表面301、兩側表面302 以及底層表面303。閘極電極242係形成於環狀形狀並圍繞 於主動式區域300的四個表面。第4A圖顯示兩個閘極電 極，其中每一個係位於柱狀物237A的各一側，一單一閘極 電極係環繞於主動式區域300的四側。 在主動式區域300的中心區域中，柱狀物237A存在， 並且閘極電極242圍繞於在柱狀物237A兩側之主動式區域 3 00的所曝露表面。由於閘極電極242係圍繞於類似環狀的 主動式區域300之四個曝露的表面，四個通道便因此而形 成。 第4B圖係爲根據本發明另一實施例中位於主動式區 域3 00及閘極電極242之間的接觸表面的示意圖，第4C圖 係爲根據本發明另一實施例之形成在主動式區域中的四個 通道之不同方向的示意圖。請參閱第4B圖，由於閘極電極 -12- 1360220 L * 242圍繞於環形的主動式區域300之頂層表面301、兩側表 面3 02以及底層表面303，因此四個通道便可以如第4A圖 般而形成。更詳細地說，如第4C圖所說明般，一第一通道 CH1係形成於主動式區域3 00之頂層表面301上，第二及 第三通道CH2及CH3則係形成於主動式區域300之兩側表 面3 02的各側上，第四通道CH4係形成於主動式區域300 之底層表面303上。 根據本發明的不同實施例，由於使用的是主動式區域 的已知表面（諸如四個表面），因此通道長度與面積便可以 被最大化至相較於傳統的RCATs與FinFETs具有一較大程 度。其結果爲，當半導體元件被積體化至一較大尺寸時， 便能夠減少一短通道效應。因此而能夠改善電晶體特性。' 本案得由熟悉本技藝之人士任施匠思而爲諸般修飾， 然皆不脫如附申請專利範圍所欲保護者。 【圖式簡單說明】 第1A圖係爲一傳統平面型NMOSFET的上視圖》 第1B圖係爲第1A圖的半導體元件中沿A-A’線的剖面 圖。 第2A圖係爲根據本發明一實施例之半導體元件的側 視圖。 第2B圖係爲根據本發明一實施例之半導體元件的剖 面圖。 第3A至3G圖係爲本發明另一實施例之半導體元件的 製造方法的剖面圖。 第4A圖係爲根據本發明另一實施例之半導體元件的 -13- 1360220 側視圖。 第4B圖係爲根據本發明另一實施例中位於主動式區 域及一閘極電極（例如，多晶矽閘極電極）之間的一接觸區 域的示意圖。 第4C圖係爲根據本發明另一實施例之形成在主動式 區域中的四個通道之不同方向的示意圖。 【主要元件符號說明】 1 1 基 板 11 A 主 動 式 區 域 12 隔 離 結 構 13 閘 極 氧 化 物 層 14 閘 極 電 極 15 閘 極 硬 式 遮 罩 21 基 板 26 間 隙 壁 27A 柱 狀 物 28 隔 離 結 構 3 1 閘 極 絕 緣 層 32 環 形 閘 極 電 極 100 主 動 式 域 101 頂 層 表 面 102 兩 側 表 面 103 底 層 表 面 23 1 基 板 232 墊 氧 化 層 -14- 1360220 233 墊氮化層 234 淺溝槽隔離遮罩 235 溝槽 236 間隙壁 237 第一凹入 237A 柱狀物 238 隔離結構 239 光阻圖案 239A 開放區域 240 第二凹入 241 閘極絕緣層 242 多晶砂層 242 閘極電極 300 主動式區域 301 頂層表面 302 兩側表面 303 底層表面 304 圓環 PG 平面型閘極 S 源極區域 D 汲極區域 CHI 第一通道 CH2 第二通道 CH3 第三通道 CH4 第.四通道 -15-1360220 IX. INSTRUCTIONS: The present invention claims priority to Korean Patent Application Nos. 10-2006-0029870 and 10-2006-0124736, which were filed on March 31, 2006 and December 08, 2006, respectively. The present invention relates to a semiconductor element, and more particularly to a semiconductor element having an increased channel area and a method of fabricating the same. [Prior Art] As for the semiconductor device, since the miniaturization has improved the design standard', the concentration of boron in the channel region also increases, which causes an increase in the electric field, which is in the dynamic random access memory. Among the (DRAM) cells and the planar N-channel metal-oxide semiconductor field effect transistors (NMOSFETs), they are particularly noticeable. Therefore, it is often difficult to obtain an acceptable update time. Due to the large size of the semiconductor elements (such as DRAMs), as the doping concentration tends to increase, the feature size tends to decrease. This increase causes an increase in the electric field of the semiconductor element; however, an increase in the electric field also increases the junction leakage. In addition, since the length and width of the channel are often limited, channel variations are increasingly applied to meet the desired technical characteristics. As a result, the mobility of electrons may be reduced, and this reduction in mobility makes it difficult to obtain the required current flow through the channel. Fig. 1A is a top view of a semiconductor element having a conventional planar NMOS transistor, and Fig. 1B is a cross-sectional view taken along line A-A' of the semiconductor device of Fig. 1A. A shallow trench isolation (STI) process is performed on a region of the substrate 11 to form an isolation structure 12 (eg, a field oxide 1360220 layer), a gate oxide layer 13 being formed by the isolation structure 12 Above the active region 11A of the substrate 11. The planar gate PG is formed on the gate oxide layer 13, wherein each of the planar gates PG includes a gate electrode 14 and a gate hard mask 15 in accordance with the sequence. Stacked on each other. In this active region 11A, N-type source and drain regions S and D are formed on both sides of each of the planar gates PG. As previously stated and explained, since the planar gate PG is formed over the flat surface of the active region 11A of the substrate 11, they are often referred to as NMOSFETs having planar vias. However, due to the large size of the integrated body, it is often difficult to obtain the desired channel length and width for the planar transistor structure, and therefore, a short (or narrow) channel effect may not be eliminated. Recessed channel array transistors (RCATs) or FinFETs are often used to overcome the above limitations. While these commonly used transistor structures are capable of increasing the channel area by using the three surfaces of the active region, these structures are still insufficient to increase the channel area to some extent due to the high degree of integration. SUMMARY OF THE INVENTION A specific embodiment of the present invention provides a semiconductor device capable of maximizing a channel area and a method of fabricating the same. According to an aspect of the present invention, a semiconductor device includes: a three-dimensional active region including a top layer, two sides, and a bottom surface; a gate insulating layer formed on the top, both sides of the active region and a vicinity of the bottom surface; and a gate electrode formed over the gate insulating layer surrounding the active region. According to another aspect of the present invention, a method of fabricating a semiconductor device includes: forming trenches in a substrate, the trenches defining active regions of the substrate; etching the substrate under the trenches, Forming an active region of the 1360220 ; plate; etching the substrate under the trenches to form a first recess connected to the trenches in a direction and providing a pillar supporting the active region; forming Simultaneously inserting the first recess and an isolation structure of the trenches; the uranium engraves the substrate and the portion of the isolation structure to form a top surface, both side surfaces and a bottom surface of the active region a second recess; forming a gate insulating layer over the exposed top, sides and bottom surface of the active region; and forming a gate electrode over the gate insulating layer to surround the active region . In one embodiment, a method of fabricating a semiconductor device includes forming an active region on a substrate having first, second, and third sides defining first, second, third, and fourth channels a fourth surface, a gate electrode layer is formed in the vicinity of the active region to isolate the first, second, third, and fourth surfaces, a gate electrode is formed on the gate insulating layer and the active In the vicinity of the first, second, third, and fourth surfaces of the region, the gate electrode is configured to control current flowing in the first, second, third, and fourth channels, the active region The first, second, third, and fourth surface systems are joined to define a solid polygonal structure, and the corners of the polygon may be circular. [Embodiment] FIG. 2 is a side view of a semiconductor element according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a semiconductor element according to an embodiment of the present invention. The semiconductor device structure has a main axis and a sub-axis. The active region 100 has four surfaces including a top surface 101, two side surfaces 102 and a bottom surface. The ring gate electrode 32 is formed in an active manner as in the second figure. On the surfaces of region 100, gate electrode 32 includes polysilicon. The pillars 27 are formed in a central region of the active region 1 1 1360220 - a ring shape, so there are four channels which surround the four surfaces of the active region 100. The ring can have a solid angular angle or a solid rounded corner depending on the application. Figure 2B shows a cross-sectional view of the cutting plane along the direction of the secondary and major axes. The component symbols 21, 26, 28 and 31 represent a substrate, a spacer, an isolation structure (for example, a field oxide layer), and a gate insulating layer (for example, an oxide layer), and the directions of the channels will be borrowed. This will be described in detail later with reference to FIG. 4C. According to the present invention, since the four surfaces of the active type region 100 are used as channels, the channel area of the semiconductor element can be increased to a greater extent than conventional RCATs and FinFETs. 3A to 3G are cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. The cross-sectional view on the left side in Figs. 3A to 3F shows the cutting plane in the direction of the minor axis of the active region 300, and the cross-sectional view on the right side shows the cutting plane in the direction of the major axis of the active region 300. Referring to FIG. 3A, a pad oxide layer 232 and a pad nitride layer 23 3 are formed over a substrate 231. The substrate 231 includes a germanium substrate having a certain amount of impurities. The pad oxide layer 232 is formed to a thickness of about 50 A to 150 A, and the pad nitride layer 233 is formed to have a thickness of about 1000 A to 2000 A. The photoresist layer is coated on the pad nitride layer 233 and patterned via a lithography process to form an STI mask 234 comprising a polymer material having a cycloolefin-maleic anhydride (COMA) or propylene. The STI mask 234 is formed to have a strip shape or a τ' shape as viewed from the top layer. Although not illustrated, an anti-reflective coating layer is formed prior to formation of the STI mask 234 to prevent scattering effects during the lithography process. The anti-reflective coating layer may include a material of silicon nitride (SiON). The pad nitride layer 233 and the pad oxide layer 232 are etched using the STI mask 234 as an etch mask, and the substrate 231 is etched to a certain depth. As a result, the grooves 23 5 are formed in isolation. The depth of each groove is in the range of about 1000 A to 2000 A in consideration of subsequent wet etching and oxidation. The trench 23 5 is a region to be used as an isolation structure and is used to define the active region 300. Referring to FIG. 3B, the STI mask 234 is removed using oxygen plasma, and the spacers are simultaneously formed on the sidewalls of the trench 235 and the stacked pattern including the pad nitride layer 23 3 and the pad oxide layer 23 2 . Above the structure. The spacers 23 6 are formed by depositing a nitride layer (not shown) on the resultant structure in Fig. 3A and performing an etch back process thereon. Referring to Figure 3C, an isotropic etch is performed using spacers 236 as an etch mask, and hydrogen chloride (HC1) vapor is used to perform the etch. As a result of this isotropic etch, the formation of the first recess 237 (or horizontal tunnel) extends laterally below the trench 235. When viewed from the direction of the main axis, the first recess 237 is cut from below by the bottom portion of the individual groove 235. The fact that the active region 300 is shorter in the direction of the minor axis than in the direction of the major axis is extremely important because the two trenches 235 in the direction of the minor axis are sufficiently close to allow the isotropic etching to The two are connected such that the grooves 235 in the direction of the main axis are sufficiently far apart to allow the pillars 237A of the substrate 231 to remain in the center. Therefore, the active area 300 does not collapse. The isotropic etching is performed while maintaining the gas pressure in a range of about 2 Torr to 200 T rr, and the flow rate of the HC1 vapor is in the range of about 100 sccm to l 〇〇〇 sccm, 1360 220 «, and the flow rate of the HC 1 vapor is From about 100sccm to lOOOsccm, the etching rate and curve are adjusted. When HC1 vapor is used, the isotropic etching is performed at a temperature of about 700 ° C to 1 000 ° C for about 30 seconds to 60 seconds. Prior to the isotropic etch using the HC1 vapor, a pre-annealing treatment is performed in a hydrogen atmosphere having a temperature ranging from about 8000 °C to 1 000 °C, and the pre-annealing is performed to remove the external material. Referring to FIG. 3D, the notch is immersed in the insulating layer into the first recess 23 7 and the trench 235, and chemical mechanical honing is performed to form the isolation structure 23 8 (eg, field oxide layer), which is immersed in insulation. The layer includes an oxide material. The STI CMP process is a conventional technique, and the honing stops at the pad nitride layer 233, which breaks into the insulating layer and simultaneously breaks into the first recess 237 and the trench 23 5 by simultaneous deposition. Alternatively, thermal oxidation treatment is performed on the gap into the insulating layer to break into the first recess 2 37, and then high-intensity plasma (HDP) processing is performed to break into the trench 2 35 » see Figure 3E Phosphoric acid (H3PO ruthenium solution is used to selectively remove the pad nitride layer 233, the photoresist layer is coated over the remaining pad oxide layer 232, and patterned via a lithography process to form a photoresist pattern 2 39 The photoresist pattern 239 includes a polymer material such as COMA or propylene, and the photoresist pattern 239 is not formed over the remaining pad oxide layer 232 in the minor axis direction. Those open regions opened by the photoresist pattern 239 239A is formed into a linear pattern, which is the location of the gate to be formed later. Therefore, due to the open region 239A, a portion of the active region 300 and a portion of the pad oxide layer 32 are exposed. The entire portion of the -10- 1360220 domain 300 in the direction of the main axis is exposed in the direction of the minor axis. Here, the entire portion of the active region 300 is active only in the direction of the minor axis. Area 300 » Oxygen The layer 232 is etched using the photoresist pattern 239 as an etch mask, and the isolation structure 238 exposed after the etch of the pad oxide layer 23 2 is etched to form a second recess 240 for channel formation. In the axial direction, the pad oxide layer 232 and the isolation structure 238 are etched. For the down etch, a dry etch is performed until the formation of the first recess 237 is reached (see Figure 3C), and a wet etch It will be additionally performed in the lateral etch. Therefore, the use of the photoresist pattern 239 to etch the pad oxide layer 232 and the isolation structure 238 will result in the formation of the second recess 240, which surrounds (or surrounds) the active The region 300 is annular. Referring to Figure 3F, the spacers 2 36 in the second recess 240 are removed. Since the spacers 236 comprise a nitride material, the H3P〇4 solution can be used for the removal. The resist pattern 23 9 is removed, and then, the pad oxide layer 232 remaining on the active region 300 in the minor axis direction is removed. After the pad oxide layer 232 is removed, the four sides 301 of the channel ' 302, 303 and 3 04 will be Exposed to the complete ring 3 04. Referring to FIG. 3G, the gate insulating layer 241 is formed over the active region 300 exposed after the removal of the pad oxide layer 23 2 , and the gate insulating layer 24 1 includes oxidation. The material is formed by performing a thermal oxidation treatment or a deposition method. More specifically, the execution of the heat treatment causes the gate insulating layer 241 to grow to a uniform thickness on the exposed surface of the active region 300. 11 - 1360 220 degrees. A polysilicon layer used as a gate electrode of the transistor is formed over the gate insulating layer 24 1 until the second recess 24 0 is broken. Although not illustrated, a metal layer having a low resistance and a hard mask layer is formed on the polysilicon layer 242 and patterned to form a gate pattern, and the metal layer and the hard mask layer may also include tungsten and nitride, respectively. Material. Since the polycrystalline sand layer 242 surrounds the four exposed surfaces of the ring-like active region 300, four channels are formed. Fig. 4A is a side view of a semiconductor element obtained in accordance with another embodiment of the present invention, and in particular, Fig. 4A shows a structural configuration (such as polysilicon layer 242) between active region 300 and a gate electrode. The active region 300 includes four exposed surfaces, namely a top surface 301, two side surfaces 302, and a bottom surface 303. The gate electrode 242 is formed in an annular shape and surrounds the four surfaces of the active region 300. Fig. 4A shows two gate electrodes, each of which is located on each side of the pillars 237A, and a single gate electrode surrounds the four sides of the active region 300. In the central region of the active region 300, the pillars 237A are present, and the gate electrodes 242 surround the exposed surfaces of the active regions 300 on both sides of the pillars 237A. Since the gate electrode 242 surrounds the four exposed surfaces of the ring-like active region 300, four channels are thus formed. 4B is a schematic view of a contact surface between the active region 300 and the gate electrode 242 according to another embodiment of the present invention, and FIG. 4C is formed in the active region according to another embodiment of the present invention. Schematic representation of the different directions of the four channels. Referring to FIG. 4B, since the gate electrode-12-1360220 L* 242 surrounds the top surface 301 of the annular active region 300, the side surfaces 032, and the bottom surface 303, the four channels can be as shown in FIG. 4A. Formed as usual. In more detail, as illustrated in FIG. 4C, a first channel CH1 is formed on the top surface 301 of the active region 300, and second and third channels CH2 and CH3 are formed in the active region 300. On each side of the side surfaces 312, a fourth channel CH4 is formed on the bottom surface 303 of the active region 300. According to various embodiments of the present invention, since the known surface of the active region (such as four surfaces) is used, the channel length and area can be maximized to a greater extent than conventional RCATs and FinFETs. . As a result, when the semiconductor element is integrated into a large size, a short channel effect can be reduced. Therefore, the transistor characteristics can be improved. 'This case has been modified by people who are familiar with the art, and it is not intended to be protected by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a top view of a conventional planar NMOSFET. Fig. 1B is a cross-sectional view taken along line A-A' of the semiconductor device of Fig. 1A. Fig. 2A is a side view of a semiconductor element in accordance with an embodiment of the present invention. Fig. 2B is a cross-sectional view showing a semiconductor element in accordance with an embodiment of the present invention. 3A to 3G are cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. Fig. 4A is a side view of the -13-1360220 of the semiconductor element in accordance with another embodiment of the present invention. Figure 4B is a schematic illustration of a contact region between an active region and a gate electrode (e.g., a polysilicon gate electrode) in accordance with another embodiment of the present invention. Figure 4C is a schematic illustration of different orientations of four channels formed in an active region in accordance with another embodiment of the present invention. [Main component symbol description] 1 1 substrate 11 A active region 12 isolation structure 13 gate oxide layer 14 gate electrode 15 gate hard mask 21 substrate 26 spacer 27A pillar 28 isolation structure 3 1 gate insulation Layer 32 Ring Gate Electrode 100 Active Domain 101 Top Surface 102 Both Side Surfaces 103 Subsurface Surface 23 1 Substrate 232 Pad Oxide-14-1360220 233 Pad Nitride Layer 234 Shallow Trench Isolation Mask 235 Trench 236 Gap Wall 237 First recess 237A pillar 238 isolation structure 239 photoresist pattern 239A open region 240 second recess 241 gate insulating layer 242 polycrystalline sand layer 242 gate electrode 300 active region 301 top surface 302 side surface 303 bottom surface 304 ring PG planar gate S source region D drain region CHI first channel CH2 second channel CH3 third channel CH4 fourth channel-15-