TWI359487B - Col (chip-on-lead) multi-chip package - Google Patents

Description

丄359487 ' 九 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利Sealed 0 [Prior Art] In the traditional semiconductor package structure, the lead frame can be used as the carrier of the ^0 carrier and the electrical transfer medium. The sealed state can be divided into "wafer on the pin" ( Chip_〇n_Lead, COL) (Lead-On-Chip, LOC) and the wafer pad carried by the wafer on the shelf. The back side of the wafer (on the surface of the chip) (i.e., the surface on which the integrated circuit is not formed) is adhered to an inner section of the leg, and the wafer and the pin are sealed by the encapsulant. In the process of molding the glue injection, the upper and lower mold flow balance is achieved, and usually the tie bar of the foot or the wafer holder is made into a plurality of sinking and bending, which causes the pins to easily shake. When it is affected by the pressure of the mold flow, resulting in displacement or deformation, the space inside the sealant should be reserved for deformation. The inner package components such as the anti-soil wafer or the lead are improperly exposed. Therefore, the number of wafers in which an inner package is constructed is limited. Especially when the pin on the pin is applied to the pin itself, which has insufficient structural strength and needs to stack a plurality of wafers, the problem of tilting the displacement of the wafer is more severe, and the change of the position of the wafer cannot control the flow of the upper and lower molds. balance. Referring to FIG. 1 , the conventional "chip on the lead" package structure 1 includes a plurality of first bows 110, a plurality of mounting wafers, and the "guide line is going to be in In order to introduce the marks, the leads, the package, the "grain stack, the polycrystalline 5th chip 130, the second wafer," and the first pin U 〇 and the caps respectively The second pin 120 is connected to the opposite side of the body 15 。. The first pins 1 1 〇#. 2 112; the 'also has a plurality of first inner legs 111 and the first outer The second flute-V" second pin 120 also has a plurality of second inner leg portions 121. The second inner legs 22 are longer than the length of the first inner leg portions U1.

Chu 1 s u inner section 122 length, in order to carry the younger one's 'day film> and the second / second chip M〇. The outer leg portions 112 of the first outer leg portion 112 extend out of the outer leg portion 122 and pass through the side of the sealant 150 to the outer side. Referring to FIG. 1 again, each of the first lower portion U1 is formed with a first sinking crease 114 Μ : crease 115 so that the first inner leg portion (1) is . The first 曰μ "1 11 horse / child set sunday film 130 is set in the first plurality of first spit inner leg adjacent lil and u brother a solder pad i 3 3, the first crystal is set in the first - free of the back of the film 130

Two-pin U〇 > sealant 15〇. The inner leg portion 111. The plurality of first buckles are connected to the first leg portions 121 of the first inner leg #.兮M _ a w , π 111 and the second first wafers 140 are positively masked #—# 13 〇 and I ancient # # π stacked on the first wafer 八 has a plurality of second pads 143. The plural number is electrically connected to the first one... " the first - welding line 170 / one button pad 143 to the 坌 The second inner leg 邱 ~ the first inner leg m and the inner leg. P 1 2 1. The seal body i 5 〇 - the inner leg portion 11 L L 糸 is used to seal the second inner leg portion 121, the second ΡΚυΛ the first day piece 130, the third piece 140, the first A first wire leg U2 and 122 are exposed by a weld line u 1 7〇, and a second wire bond.谙,, the first outer leg of the two, please refer to the first figure, because the first inner leg i! i 6 is bent over two bends ( Φί· # 第 - sinking and bending The mark 114 and the scar 115) form a sinking π, which is set, so that the structural strength of the iu is lowered and it is not necessary to control the first inner leg surface. Therefore, A, m ^ , sealing glue During the process, the first inner leg is insufficiently supported, and the inner leg 111 generates & - the soil is not moved or displaced, so it is highly probable that the inner leg 111 or the crystals > ί 130 and 140 are exposed. The shape of the clear shape, in addition, the mold flow impact caused the wire to be pulled and broken 'to make the package defect rate more improved. This u first day of the film i4 misses the first one below the first usually in the first The wafer 130 and the second wafer 140 are spaced apart from each other by a sheet 90', but thus shortening the stacking of the wafers by stacking more wafers. Since the spacers 190 of the second wafer 14 are bonded to each other (including the formation of the spacers 190) The first part) cannot obtain the support from the spacer 1 90 into a floating portion, in order to make the second bonding wires 170 have a branch The second wafer 140 must have a certain thickness to make the number of stackable wafers. SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a multi-chip package structure on a lead. In the bearing, the foot does not need to be placed and bent, so that the upper and lower modes can reduce the mold flow interference and prevent the pin displacement, so "the wafer can be stacked on the pin of the mounted state; S; The shadow of the water flow pressure of the first inner leg portion 111 of the second sinking curve causes the first occurrence of the first sealing bodies 160 and 170, and a height is set between the welding wires 160 without the periphery. Good bonding with the two pads 143 while wire bonding, but thus limiting the pin flow balance of a wafer chip, and the pin is not displaced by the displacement 7 1359487 oblique 0

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-chip package structure of a wafer on a lead mainly includes a plurality of first pins, a first wafer, one or more second wafers, and a gel. Each of the first pins has a first inner leg. The first wafer is disposed on the first pins. The second wafers are stacked on the first wafer. The encapsulation system seals the first wafer, the second wafers, and the first inner leg portions of the first pins. The first inner leg portions are coplanar full-sinking configurations such that the first inner leg portions are all parallel to one of the first surface and the second surface of the encapsulant. Moreover, the height distance between the first inner leg portion and the first surface is three times or more than the height distance between the first inner leg portion and the second surface, and the second wafers have appropriate The amount is such that the thickness of the sealant from the first surface to the nearest second wafer is substantially the same as the height distance of the first inner leg to the second surface. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-chip package construction, the number of the second wafers may be three. In the above multi-chip package structure, the first wafer system may have a first active surface, a first back surface, and a plurality of first pads formed on the first active surface, the first back surface is attached to The first inner legs of the first pins. 8 1359487 In the foregoing multi-chip package structure, a plurality of first bonding wires may be further included, which electrically connect the first pads to the first inner legs of the first pins. In the multi-wafer package construction described above, each second wafer may have a thickness no greater than the thickness of the first wafer. In the multi-chip package construction described above, each of the first pin systems may further have a first outer leg portion extending from the side edges of the encapsulant and bent and formed.

In the multi-chip package construction described above, the first outer leg portions of the first pins are bendable toward the first surface. In the foregoing multi-chip package structure, a plurality of second pins may be further included, each second pin has a second inner leg portion, wherein the second inner leg portions are shorter than the first ones. The inner leg portion is such that the second inner leg portion is not used to carry the first wafer. In the multi-chip package construction described above, each of the second lead pins may further have a second outer leg portion extending from the side edges of the encapsulant and bent and formed. In the multi-chip package construction described above, the second outer leg portions of the second pins are bendable toward the first surface. In the multi-wafer package construction described above, each of the second wafers has a plurality of second pads, and the second wafers may be staggered in a stepped stack to not cover the second pads. In the foregoing multi-chip package structure, a plurality of second bonding wires may be further included, which electrically connect the second pads to the second inner legs of the second pins. In the foregoing multi-chip package construction, a plurality of interconnect bonding wires may be further included, which are electrically connected to the second pads of adjacent second wafers. In the multi-chip package construction described above, the thickness of the first pins may be not less than the thickness of the first wafer. In the above multi-chip package structure, a pin pitch sustaining sheet may be further disposed on the plurality of surfaces of the first inner leg portions of the first pins facing the two surfaces.

In the foregoing multi-chip package structure, the thickness of each of the first wafer and the second wafers may be thinned to a height not greater than the height of the first inner leg to the second surface. . In the multi-wafer package construction described above, an electrically insulating wafer attaching layer is fully attached to the back side of each of the first wafer and the second wafers. It can be seen from the above technical solution that the multi-chip package structure of the wafer of the present invention has the following advantages and effects: 1. Solving the problem that a wafer cannot be stacked on a "on-pin" package type for a long time. problem. Second, the pins inside the pins of the carrying chip do not have any sinking and bending marks, so that the upper and lower mold flow balance can be achieved, and the mold flow interference to the pins can be reduced, so that when stacking a plurality of wafers on the pins, No displacement or tilting will occur. Third, it can reduce the influence of other components of non-wafer (such as spacer) on the upper and lower mold flow, can stack more wafers and facilitate the calculation of the table by the sealant.

1359487 Surface to the thickness of the nearest wafer. Fourth, the problem of the wrong line of the bonding wire can be avoided to reduce the traffic of the wire. [Embodiment] According to the first embodiment of the present invention, the multi-chip package structure 200 of the wafer on the pin is shown in FIG. Mainly includes a first pin 210, a first wafer 230, one or more two wafers 240, and a colloid 250. As shown in FIG. 2, each of the first pins 210 has an inner leg portion 211 and a first outer leg portion 212, wherein "the inner leg portion is a portion where the pin is sealed in the sealant body; The outer leg portion refers to a portion that extends beyond the sealant. The first pins 2 1 0 can be on the same lead frame, and the material thereof can be iron, copper or other metal materials and has a suitable thickness (about 125.125 mm or more), which is enough to support the wafers 230 and 240. Structural strength. Preferably, the thickness of the first 210 is not less than the thickness of the first wafer 230. The first inner leg portions 211 are in a coplanar full-sink configuration, and the first inner leg portions 211 are formed in a fully-deposited configuration on the sinking plane 201 so as not to damage the carrier chip. Support strength. In the case of "full-sinking type", it means that the inner leg is formed in the same plane and does not form a sinking crease. The so-called "sinking and bending" means that the inner leg is bent into a vertical or other angle to form different flat curves. Specifically, the first inner leg portions 211 extend from the side of one of the sealing tapes through the back surface of the first wafer 230, and the back surface of the first wafer 230 is carried in the first portions. The first first "pin" of the foot 211 is taken from the material, and the pin is loaded, and in other words, the first bend 250 of the sinking type makes the one of the 11

1359487 A particular section, but the first inner leg 211 still has a finger covered by the wafer 230. In this embodiment, the length of the 211 may exceed the multi-chip package i-line for carrying the first wafer 230 and the negative of each of the first pins 210 in the driver embodiments. The side of the encapsulant 250 extends to J to be bonded to an external printed circuit board (the unillustrated portion 212 can be bent into a gull lead, other shapes such as an I-shape or a J-shape, etc.) Referring to Figure 2, the first wafers are on the first pins 210. The first wafer 230 is 0.125 mm. The first wafer 230 can have a first back surface 232 and a plurality of first a first pad 233 is attached to the first inner leg portion 211 of the first chip 203. The first column is on a single side of the first wafer 230. On the first back side of the wafer 230 The 232 series can fully paste the wafer attaching layer 234 as a die bond and increase the degree, so that the first wafer 30 0 can be further thinned. The first back surface 232 is bonded to the electrically insulating wafer attaching layer 234 to The first inner leg portion 211 has a package shape on the foot. The thickness of the electrically insulating phase may be about 0.025 mm. As shown in Fig. 2, the second wafers are not formed by one of the first first inner leg portions I: 200. The second wafer 240 is bent at the outer leg portion 2 1 2, L. ,For). The first outer legs may be bent into 230 series, and the thickness may be about the first active surface 23, and the active surface 231 may be arranged on the first lead pads 233. In particular, the resistance to breakage of the electrically insulating wafer is particularly advantageous, and the wafer 230 can be "the wafer is attached to the wafer attachment layer 234 240 in the 12 1359487.

Above the first wafer 230. Specifically, the second wafers 240 may be stacked on the first wafer 230 in a staggered manner, and the first pads 233 are exposed for subsequent wire bonding steps. Each of the second wafers 240 can have a second active surface 241, a second back surface 242, and a plurality of second pads 243 formed on the second active surface 241. Preferably, the second wafers 240 are stacked in a staggered manner so as not to cover the second pads 243, thereby reducing the influence of other components of the non-wafer (such as spacers) on the upper and lower modes, and More second wafers 240 can be stacked. In this embodiment, the second back surface 242 of each of the second wafers 240 can be fully attached with an electrically insulating wafer attaching layer 244 to serve as a die bond and increase the chip's breaking strength, so the second wafer 240 The electrically insulating wafer attaching layer 244 can be bonded to the active surface of the first wafer 230 or the second wafers 240 below it. In particular, the second wafers 240 can be substantially identical to the first wafer 230. For example, the first wafer 230 and the second wafer 240 may be the same size and the second pads 243 are also arranged in the same wafer. In this embodiment, the number of the second wafers 240 may be three. The multi-chip package construction 200 is more suitable for stacking four or eight wafers. In the present embodiment, the multi-chip package structure 200 has four wafers stacked. Each second wafer 240 may have a thickness no greater than the thickness of the first wafer 230. Specifically, the thickness of each of the second wafers 240 may be approximately equal to the thickness of the first wafer 230, and the thickness of each of the second wafers 240 may be approximately 〇 125 125 mm. Generally, the encapsulant 250 is formed by compression molding, which is used to avoid the first wafer 230, the second wafers 240, and the first inner legs 211 from being contaminated by external pollutants. Referring to FIG. 2 , the encapsulant 250 seals the first wafer 230 , the second wafers 240 , and the first inner leg portions 211 of the first pins 210 . In this embodiment, the first outer leg portion 2 1 2 of the first pin 210 is extended outward from one side of the sealant 250 and can be bent toward the first surface 251.

Please refer to FIG. 2 , because the first inner leg portions 211 are in a coplanar full-sink configuration, so that the first inner leg portions 21 1 are all parallel to the first one of the seal bodies 250 . Surface 251 and a second surface 252. In other words, the fully-sinking plane 201 is parallel to the first surface 251 and the second surface 252. The first inner leg portion 211 to the first surface 251 have a height distance H1 of an equal width, and the first inner leg portion 211 to the second surface 252 also have a height distance H2 of an equal width. . And the first inner leg portion 211 of the first full leg portion 211 to the first surface portion 251 is the first inner leg portion 211 to the first portion The height of the two surfaces 252 is three times or more than the height H2, and the second wafers 240 have an appropriate number to cause the sealant 250 to have a thickness from the first surface 25 1 to the nearest second wafer 240A. T1 is substantially the same as the height distance H2 of the first inner leg portion 211 to the second surface 252 to achieve upper and lower mold flow balance. The thickness T1 is the shortest vertical height distance between the first surface 251 of the encapsulant 250 and the second active surface 241 of the second wafer 240A, and the first inner leg portions 14 211 to the second The height distance H2 of the surface 252 refers to the shortest vertical height distance between the surface of the first inner leg portion 2H (the surface on which the first wafer 230 is not disposed) and the second surface 252. Specifically, the thickness τι and the degree of distance H2 of the first inner leg portion 211 to the second surface 252 may be about 338 mm, which is the same value. Preferably, the thickness of each of the first wafer 230 and the second wafers 24 is thinned to a height not greater than the height of the first inner leg 2 ι to the second surface 252. H2, for stacking more crystals. In this embodiment, the thickness of the multi-chip package structure 2 is: L000-. The first inner leg portion 2ΐι: the height distance H1 of the first surface 251 refers to the surface of the first inner leg portion 211 (the surface of the first ay day plate 23 0 is disposed) The distance from the first surface 25l, the thickness of the first wafer 230 (about 0 · 1 25 mm), each first 曰 y. The thickness of the first day of the film 240 (about 0.125 mm), the thickness of each of the layers of electrically insulating wafers, the thickness of the adhesion layer 234 (about 0.025 mm), and the thickness T1 (about, 138 mm) The total distance H1 of the first inner leg portion 211 to the first surface is substantially 0.738 mm. The height distance H2 of the first inner leg portion 211 to the first surface 252 is about 138138mm. It can be seen from the above that in the embodiment, the height distance m of the first inner leg portion 2U to the first surface 251 is about five of the height distance H2 of the first inner leg portion 211 to the second surface 252. Times. In different embodiments, the first inner leg portion 2 ι to the first surface 251 has a twist distance Hi and the first inner leg portions 211 15

The ratio of the height distance H2 of the second surface 252 to the second surface 252 may be 3:1. Therefore, the first inner leg portions 2 of the first pins 210 need to be additionally formed with a folding bend by 'to reach the upper and lower modes. The leveling edge can reduce the mold flow interference, so as to prevent the wafer from being tilted, the lead wire is broken, and the like, so that more wafers can be stacked on the 'pins 210' without displacement. Since the first bows 21 are fully configured and are not easily dry by the mold flow, the inner legs 211 of the first pins 210 may be adjacent to the second 252 of the seal body 250 in parallel, as opposed to More stacks are placed above the first wafer 230 for stacking a larger number of first wafers 240, so that more wafers can be stacked without expanding the overall thickness of the structure to expand the bulk capacity. Preferably, the second wafers 240 can be stacked in a wrong order, so that the influence of the other 70 pieces (such as spacers) of the non-wafer I on the upflow can be reduced, so that more first dies 240 are stacked and the calculation is facilitated. Body 250 is from the first surface 251 to the nearest second wafer 240A T1. Further, the formation of the sinking step can be omitted in the manufacturing process to shorten the manufacturing time of the multi-chip package structure 200. Referring to FIG. 2, in the embodiment, the multi-wafer structure 200 may further include a plurality of second pins 22, each of which has a second inner leg portion 221' The second encapsulation is sealed by the encapsulant 250. The second pin 220 and the first pin 210 are taken from the 扒π^, the same-lead frame, and the second 220 and the first pins 21 are respectively located on the multi-chip. Package or 4: 1 1 No, and solder-soldered first surface stacking and sealing memory ladder-shaped lower mold-filled package of thick packaged package pin 丨220 These pin structures 16 1359487

200 of the two corresponding sides. In this embodiment, the thickness of the second pins 220 may not be less than the thickness of the first wafer 230. Specifically, the thickness of the second pins 220 can be substantially equal to the thickness of the first pins 210 (about 0.125 mm or more). The multi-chip package structure 200 can be applied to a Thin Small Outline Package (TSOP), and the number of pins can be 48 pins, so the number of the first pins 210 and the second pin 220 The number can be 24 respectively. In this embodiment, the second inner leg portions 22 1 of the second pins 220 are shorter than the first inner leg portions 211 , and the second inner leg portions 221 are arranged in the sealing body 250 . The second inner leg portion 22 1 of the second pins 220 is not required to carry the first wafer 230 . The second inner leg portion 22 1 of the second pins 220 is not required to extend the first inner surface of the first wafer 230 . Referring to FIG. 2 again, preferably, the second inner leg portions 221 are coplanar full-sinking configurations and are formed on the fully-sinking plane 201. In this embodiment, the second outer leg portions 222 of the second pins 220 extend from the sides of the sealant 250 and are bent and formed. The second outer leg portion 222 of the second pin 220 can also be bent toward the first surface 251. As shown in FIG. 2 , the multi-chip package structure 200 may further include a plurality of first bonding wires 260 electrically connecting the first pads 233 to the first pins 210 . The first inner leg portion 211 and the second inner leg portions 221 of the second pins 220. More specifically, a plurality of second bonding wires 270 can be used to electrically connect the second pads 243 to the second inner legs 17 of the second pins 220 to reach a ratio of 9487 L·. The second wafer 240 is electrically connected to the second pins 220. Preferably, the multi-chip package structure 200 can further include a plurality of interconnected if-lines 280' electrically connected to the second pads 243 of the adjacent second wafers 240. One of the interconnecting wires 280 is electrically connected to the adjacent second pads 243 and the first pads 233, so that the second wafers 240 can be The bonding wire 260 transmits an electrical signal to the first inner leg portions 2U. Therefore, the problem that the first bonding wires 260 and the second bonding wires 27 are misaligned can be avoided by the interconnection bonding wires 28〇 to reduce the risk of the wire. In addition, due to the first wafer 23 〇

The misaligned stepped stack between the first crystals and the second wafers 24 can provide a second wafer 24 位于 preferably supported thereon, so that even if the second wafers 240 are specialized by the lotus, there is no Caused by lack of support

The second wafers 24 honed the problem of jfSiixA υ fracture. Further, the integrity of the structure of the second wafers 240 during the wire bonding operation can be further maintained, so as to avoid the wafer receiving. In the specific embodiment of the present invention, please refer to FIG. The multi-chip package structure of the other θ μ 在 on the pin is substantially the same as the first embodiment of the present invention, so that the first embodiment is used from Μ ^ 苻No. and no longer repeat them. The multi-chip package structure mainly comprises a plurality of first pins 210, a first 230u 230, one or more first ruthenium sheets 240, and a colloid 25 〇. In this embodiment, the first inner leg portion 211 of the first two-legged foot 210, the gentleman of the sealant 250, the height distance Η1 of the surface 251 is about the first inner portion. The leg portion 2li=_1 to the second surface 252 of the sealant 250 has a height of 18 1359487* degrees three times the distance H2' and the same two wafers 240 have an appropriate number to cause the first inner portions The height distance H2 of the n-foot portion 211 to the second surface 2 52 of the encapsulant 250 is substantially the same as that of the encapsulant 250 from the first surface 251 to the last wafer. The thickness of 240A Τ Γ 'to achieve upper and lower mold flow balance. Read J% and then as shown in FIG. 3, the multi-chip package structure may further include a & 3 foot spacing maintaining sheet 290 attached to the first pin 210. The inner leg portion 211 faces the sealant

The number of the second surface 252 of the body 250 is the main sleeve < the last few surfaces. Therefore, the pin pitch maintaining piece 290 can maintain the distance between the gates of the first inner leg portion 211 of the pin-to-pin-pin 210 to avoid the process of molding the glue. - The displacement of pin 21G$ is affected by the mode flow. The thickness of the lead (4) from the sustaining sheet 290 may be about 〇 7 〇 mm. (4) The foot spacing maintaining sheet may be an electrically insulating tape such as a polypethylene (p〇iyimide, H) tape. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is subject to the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the embodiments are not deviated from the technical solutions of the present invention, and the above embodiments are in accordance with the technical essence of the present invention. Any simple modifications and modifications made by the invention are still within the scope of the technical solutions of the present invention. [Simple diagram of the diagram] Figure 1. Schematic diagram of the multi-chip package structure of the conventional wafer on the lead 19 1359487 磉 ψ Figure 0

2 is a cross-sectional view showing a multi-chip package structure on a pin according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a multi-chip package structure on a pin according to a second embodiment of the present invention. Component Symbol Description 100 Multi-chip package construction 110 First pin 111 First - - Inner leg 112 114 First sinking crease 115 Second sinking crease 120 Second pin 121 Second inner leg 122 130 first wafer 133 first - pad 140 second wafer 143 second two fresh pad 150 encapsulant 160 first - bonding wire 170 190 spacer 200 multi-chip package structure 201 210 first - pin 211 first - inner Foot 212 220 second pin 221 second inner leg 222 230 first wafer 231 first - active surface 232 233 first pad 234 electrically insulating wafer attach layer 240 second wafer 240A second E plate 241 242 Second Back Side 243 Second Pad 244 Electrically Insulating Wafer Mounting Layer 250 Sealant 251 Surface 252 - Wafer is in the drawing. A wafer is intended to be in k. First outer leg second outer leg second wire fully sunken plane first outer leg second outer leg first back second active surface second surface 20 1359487 \ 260 first bonding wire 270 second welding Line 280 interconnect wire bond 290 pin spacing maintaining piece H1 height distance from first inner leg to first surface ΗΓ height distance from first inner leg to first surface H2 height of first inner leg to second surface The height distance T1 from the first inner leg to the second surface of the distance H2' is from the thickness of the first surface to the second wafer closest to the second wafer ΤΓ from the first surface to the thickness of the nearest second wafer

twenty one

Claims (1)

Patent application::, the wafer on the pin θ through the cylinder 7-day chip package construction 'contains: a plurality of first pins, each - flute ^ 匕 3 a flute a 曰 ^ first bow I The foot line has - the first inner first wafer, the Ministry of the Ministry of War - hK JL_1. Shao is placed on the first - bow foot; one or more of the first - and "slices" a colloid on the first wafer, which seals the first 曰^ 日 日. The first and second legs of the second pin of the second wafer are parallel to each other [main Θ Ρ 其中 其中The encapsulation system has one of the first surface and the second surface; wherein the first inner leg portion is a full-sink configuration of a total of thousands of faces to face and parallel to the sealant ^ the first surface, and the height distance of the first inner leg to the first surface is three or more times the height distance of the first inner leg to the second surface, The second wafer has an appropriate number ' such that the sealant has substantially the same thickness from one of the first surface to the nearest second wafer a height distance from the first inner leg to the second surface; wherein each second chip has a plurality of second pads, and the second chips are in a staggered stepped stack to not cover the The second solder pad is as follows: 2. The multi-chip package structure of the wafer on the pin as described in claim i wherein the number of the second wafers is three. 3. As claimed in the patent scope The multi-chip package structure of the wafer on the lead, wherein the first wafer has a first active surface, a first back surface, and a plurality of first solder pads formed on the first active surface, the first The back side is attached to the first inner leg portions of the first pin. 1359487 • κ 4, the polycrystalline moon package structure of the wafer on the lead according to claim 3, and the plural a bonding wire electrically connecting the first bonding pads to the first inner legs of the first pins. 5. The wafer according to the patent application scope is on a pin. a multi-chip package structure in which the thickness of each of the second wafers is not greater than the first The thickness of the wafer.% 6. The multi-chip package structure of the wafer on the pin as described in the patent application 帛i' wherein each of the -pin-pins further has a - outer leg portion extending from the side of the encapsulant And out and bend to form. 7. The multi-chip package structure of the wafer of claim 6, wherein the first-outer leg of the first-pin is bent toward the first surface. 8. The multi-chip package structure of the wafer according to claim 4, wherein the wafer further comprises a plurality of second pins, each of the second pins having a second inner leg, wherein the The second inner leg portions are shorter than the first inner leg portions, and the inner leg portion is not used to carry the first inner chip. 9. The multi-chip package structure of the wafer on the pin as described in claim 8 wherein the second inner leg of the second bow is shorter than the first pin of the first pin of the circuit The foot is not used to carry the first wafer. 10. The multi-chip package structure of the wafer on the pin as described in claim 9 wherein the number of the second legs is equal to the number of the first pins. U. The multi-chip package structure of the wafer on the pin as described in claim 8 wherein each of the first leg systems further has an H leg portion, 23 1359487 λ.** which is the side of the encapsulant Extend and bend out. 12. The multi-wafer package structure of the wafer according to the scope of the patent application, wherein the second outer leg portion of the (4) two (10) is bent toward the surface of the crucible. ...such as the scope of patent application! The multi-wafer sealing structure of the wafer on the pin, further comprising a plurality of second bonding wires electrically connected: the second bonding pads to the second inner legs of the second pins unit. 14. The multi-wafer package construction of the wafer on the lead of claim i, further comprising a plurality of interconnect bonding wires 'the second pads of the second wafer. 15. The multi-wafer package structure of the wafer on the lead according to claim i, wherein the thickness of the (four) 1 leg is not less than the thickness of the first wafer. 16. The multi-chip package structure of the wafer on the pin according to claim 1, further comprising a pin pitch maintaining sheet attached to the first-inner leg of the first pin a plurality of surfaces of the second surface. 7. The multi-chip package structure of a wafer on a lead according to claim 1, wherein a thickness of each of the first wafer and the second wafer is thinned to not more than the above The height distance between the first and inner two surfaces. The multi-chip package structure of the wafer on the lead according to claim 17, wherein the back surface of each of the first wafer and the second wafer is fully attached. Sister & ^ Electrically Insulating Wafer Attachment Layer. twenty four