TWI359478B - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- TWI359478B TWI359478B TW097103711A TW97103711A TWI359478B TW I359478 B TWI359478 B TW I359478B TW 097103711 A TW097103711 A TW 097103711A TW 97103711 A TW97103711 A TW 97103711A TW I359478 B TWI359478 B TW I359478B
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- Prior art keywords
- layer
- forming
- metal
- semiconductor device
- heat treatment
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- 238000000034 method Methods 0.000 title claims description 45
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 67
- 238000010438 heat treatment Methods 0.000 claims description 53
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 39
- 229910052732 germanium Inorganic materials 0.000 claims description 38
- 238000004519 manufacturing process Methods 0.000 claims description 34
- 239000007789 gas Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 11
- 229910052707 ruthenium Inorganic materials 0.000 claims description 11
- 239000011261 inert gas Substances 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052744 lithium Inorganic materials 0.000 claims description 3
- 229910001507 metal halide Inorganic materials 0.000 claims description 3
- 150000005309 metal halides Chemical class 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 2
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000004575 stone Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 111
- 238000002425 crystallisation Methods 0.000 description 16
- 230000008025 crystallization Effects 0.000 description 16
- 239000003054 catalyst Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000009825 accumulation Methods 0.000 description 6
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
成'其程序單純，雖有易高聚積化的優點，但也有待機電 流南、軟性誤差耐性脆弱等缺點。TFT細胞為在MOSFET 上積層有多TFT之構造，雖有待機電流不高、易高聚積化等 優點’但有不易低電力化的缺點。 第1圖係顯示習知具有TFT細胞構造之SRAM製造方法 之截面圖。第1圖所示之領域相當於SRAM細胞陣列的一部 分0 第Ua)圖，係顯示形成MOSFET，且用以在其上方積層 多TFT之前步驟。相當於半導體基板之矽晶圓1〇上形成有由 閘極11、源極/汲極12所構成之MOSFET。在此，省略形成 MOSFET相關詳細内容的說明。 第1(b)圖’係顯示形成適用於多晶矽TFT之多晶矽製造 的種子層步驟。一般而言，如此之多晶矽是以單結晶矽為 種子，再使非晶矽結晶化來製造。首先，M〇SFET上形成 層間絕緣層13，並形成使源極/汲極12領域露出之接觸孔 14。接著，在接觸孔14上利用SE(}法(選擇性磊晶生長)形成 作為種子層之單結晶矽層15 ^ SEG法為一種化學蒸鍍法， 且是在在900°C以上的溫度、使用SiH4、％氣體，僅在矽露 出領域使單結晶矽成長以控制之方法。即，單結晶矽僅在 以接觸孔14露出之源極/汲極12上（即，矽）成長，且不會在 層間絕緣層13上成長之方法。 第1(c)圖係顯示在層間絕緣層13與單結晶矽層15上形 成非晶矽層16之步驟。非晶矽層主要是利用低壓化學蒸鍍 法(LPCVD)或電漿化學蒸鍍法(pECVD)形成。 第1(d)圖係顯示將非晶矽層16進行熱處理並形成多經 石夕層17之步驟。此時’單結晶⑪層15係擔任非結晶石夕的結 晶化種子的任務。在藉由如此所形成之矽層上製造多TFT 完成SRAM。在此，省略相關的詳細說明。 然而’前述習知方法中，有以下的問題點。 第-、使用種子，使非晶石夕層結晶化是有限制的。如 前所述’由於為了獲得所需的結晶性，必須將非晶碎層進 行長時間熱處理，因而SRAM的生產性會大大降低。當然， 提南熱處理溫度可縮短熱處理時間，但在SRAM整體程序 上，亦有無法提高熱處理溫度的狀況。 第二、擔任種子任務之單結晶矽層形成時所使用之 SEG法是在高溫進行的程序，為高單價的程序。如前所述， 由於SEG法程序溫度在900C以上’因而會有sram熱積存 增加的缺點。藉此，由於SEG法基本上為高單價程序，因 而會有SRAM製造成本增加的問題點。 L發明内容3 本發明欲解決之課題 因此，本發明係用以解決前述習知技術問題點而製成 者，其目的在於提供一種生產性高、程序成本低iSRAM 製造方法。 為達成前·述目的，本發明之半導體元件之製造方法， 包含以下步驟.於半導體基板上形成製造半導體元件之電 晶體；於前述電晶體上形成絕緣層；選擇性去除前述絕緣 層’形成使刚述電晶體預定領域露出之接觸孔：於前述接 1359478 =切層；於前述絕緣層及前㈣層上 曰’將則切層及前述金屬層進行熱處理 战金屬 物層；去除前述金屬層；於前述絕緣層及前述.屬石夕化 =形成非晶㈣；及將前述非㈣層進行熱處^ 夕晶砂層。 形成 又’為達成前述目的，本發明之半導體元生Into its program is simple, although it has the advantages of easy accumulation, but also has shortcomings such as standby current south and soft error tolerance. The TFT cell has a structure in which a plurality of TFTs are stacked on the MOSFET, and has the advantages of low standby current and high accumulation, but has a disadvantage that it is difficult to reduce the power. Fig. 1 is a cross-sectional view showing a conventional SRAM manufacturing method having a TFT cell structure. The field shown in Figure 1 corresponds to a portion of the SRAM cell array, 0 Ua), showing the steps before the MOSFET is formed and used to build multiple TFTs over it. A MOSFET composed of a gate electrode 11 and a source/drain 12 is formed on the germanium wafer 1 corresponding to the semiconductor substrate. Here, the description of the details of forming the MOSFET is omitted. Fig. 1(b) shows the step of forming a seed layer for polycrystalline germanium fabrication suitable for polycrystalline germanium TFTs. In general, such a polycrystalline silicon is produced by seeding a single crystal ruthenium and crystallizing the amorphous ruthenium. First, an interlayer insulating layer 13 is formed on the M?SFET, and a contact hole 14 exposing the source/drain 12 region is formed. Next, a single crystal germanium layer as a seed layer is formed on the contact hole 14 by the SE (} method (selective epitaxial growth). The SEG method is a chemical vapor deposition method, and is at a temperature of 900 ° C or higher. The use of SiH4, % gas to grow a single crystal yt only in the field of yttrium exposure is controlled. That is, the single crystal yt grows only on the source/drain 12 (ie, 矽) exposed by the contact hole 14, and does not A method of growing on the interlayer insulating layer 13. Fig. 1(c) shows a step of forming an amorphous germanium layer 16 on the interlayer insulating layer 13 and the single crystal germanium layer 15. The amorphous germanium layer mainly utilizes low pressure chemical vaporization. Plating (LPCVD) or plasma chemical vapor deposition (pECVD) is formed. Figure 1(d) shows the step of heat-treating the amorphous germanium layer 16 to form a multi-layered layer 17. At this time, 'single crystal 11 The layer 15 serves as a task of crystallizing seeds of australis. The SRAM is completed by fabricating a plurality of TFTs on the layer formed thereon. Here, the detailed description is omitted. However, the above conventional methods include the following. The problem point. - The use of seeds to crystallize the amorphous layer is limited. As mentioned above, in order to obtain the required crystallinity, the amorphous fracture layer must be heat-treated for a long time, so the productivity of the SRAM is greatly reduced. Of course, the heat treatment temperature of the heath can shorten the heat treatment time, but in the overall process of the SRAM. There is also a situation in which the heat treatment temperature cannot be increased. Second, the SEG method used in the formation of a single crystal layer for seeding tasks is a procedure performed at a high temperature, which is a high unit price procedure. As described above, due to the SEG method procedure The temperature is above 900 C. Therefore, there is a disadvantage that the sram heat accumulation increases. Thereby, since the SEG method is basically a high unit price program, there is a problem that the manufacturing cost of the SRAM increases. L SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for manufacturing a high-performance and low-cost iSRAM. The method for manufacturing a semiconductor device of the present invention is achieved for the purpose of the foregoing description. The method comprises the steps of: forming a transistor for manufacturing a semiconductor element on a semiconductor substrate; forming an insulating layer on the transistor; The first insulating layer is formed to form a contact hole exposing a predetermined area of the transistor: in the foregoing, 1359478 = a slice; on the insulating layer and the front (four) layer, the slice and the metal layer are heat-treated to the metal. a layer of material; removing the metal layer; forming an amorphous (four) layer on the insulating layer and the foregoing genus; and performing a hot layer on the non-(four) layer; forming the same as the object of the present invention Semiconductor student
=’於則述電晶體形成絕緣層;選擇性去除前述電 形成使前述電晶财㈣出之接觸孔；於前述層緣層」 上开，成金屬層，將藉由月,』逑接觸孔的形成 則述電晶體石夕層及前述金屬層進行熱處理，形</ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The formation of the transistor and the metal layer are heat treated.
化物層；去除前述金屬層；於前述絕緣層及前述接觸孔I 形成非晶石夕層；及將前述非晶石夕層進行熱處理形成多晶 石夕層。And removing the metal layer; forming an amorphous layer on the insulating layer and the contact hole I; and thermally treating the amorphous layer to form a polycrystalline layer.
Ag、Au、Co、Sb、pd、Ag, Au, Co, Sb, pd,
前述金屬層，包含Ni、Al、Ti Cu中任一或兩種以上之金屬。 前述金屬層以利用化學蒸鍍法形成者為佳。 前述金屬層以利用原子層單位蒸鍍法（Μ。—— unit deposition)形成者為佳。 20 冑述金屬石夕化物層厚度’最好是可以依前述非晶石夕層 厚度決定。 形成前述金屬矽化物層步驟之熱處理溫度，以25〇它至 500°C為佳；滅理時間以3〇分至叫為佳；且熱處理環境 氣體以非活性氣體為佳。 8 1359478 前述金屬層係以可利用SPM(硫酸過氧化氫混合物 (Sulfuric Peroxide Mixture))溶液去除者為佳。 形成前述多晶矽層步驟之熱處理溫度以4〇〇乞至7〇〇°C 為佳；熱處理時間以1小時至10小時；且熱處理環境氣體以 5 非活性氣體為佳。The metal layer contains a metal of any one or two or more of Ni, Al, and Ti Cu. The metal layer is preferably formed by a chemical vapor deposition method. The metal layer is preferably formed by atomic layer deposition (unit deposition). 20 The thickness of the metal lithium layer is preferably determined according to the thickness of the amorphous layer. The heat treatment temperature for forming the metal halide layer step is preferably from 25 Torr to 500 ° C; the annihilation time is preferably from 3 Torr; and the heat treatment ambient gas is preferably an inert gas. 8 1359478 The aforementioned metal layer is preferably removed by a SPM (Sulfuric Peroxide Mixture) solution. The heat treatment temperature for forming the polycrystalline germanium layer step is preferably 4 Torr to 7 Torr °C; the heat treatment time is 1 hour to 10 hours; and the heat treatment ambient gas is preferably 5 inert gases.
本發明之半導體製造方法，由於可大大縮短非晶矽結 晶化所需的熱處理溫度及熱處理時間，故可減少 DRAM製造程序上的熱積存，且有提高SRAM4DRAM生產 性的效果。又，本發明之SRAM製造方法，不需利用用以形 1〇成種子的高價程序，且具有降低SRAM製造成本的效果。 t實施方式；J 較佳實施例之詳細說明 以下，參考附加圖示’詳細說明本發明之構造。 本發明之SRAM製造方法，係利用金屬觸媒降低結晶 15化溫度的方式形成多晶矽層。利用金屬觸媒，使非晶矽結 晶化之方法’適用於相當於LCd等平板顯示器的驅動元件 之多晶石夕薄膜電晶體（Poly Silicon Thin Film Transistor; Poly Si TFT)。多晶矽TFT製造時最重要的程序，是在低溫 下進行非晶妙結晶化之程序，且尤其以可降低結晶化溫度 20為佳。因此’提案有各種可在低溫下、短時間内，形成多 晶矽之程序’而其中又以可對非晶矽塗佈Ni、Cu、A1等金 屬觸媒’以低溫誘導結晶化之方法受到注目。 在此’本發明人著眼於在LCD多TFT製造時，利用金屬 觸媒使多晶矽結晶化之方式亦可適用於SRAM多tft製造 9 時、，到本發明。換言之，由於只要在形成的多 TFT之多晶⑦層結晶化時_金屬觸媒，即可低溫結晶化， 由；可在同樣的熱處理溫度條件下縮短熱處理時間故 可提门SRAM的生產性。又，自於可進行種子乃至於多晶石夕 層的結晶化亦可錢用程序成本高之舰法。藉此， 可降低SRAM的製造成本。 第2圖係顯示本發明第j實施型態之SRAM製造方法之 截面圖。與第1圖同樣地’帛2圖,亦以相當於訊鳩陣列一部 份之領域為例加以說明。 由於第2(a)圖與第1(a)及(b)圖的步驟相同，故省略詳細 说明。然而，由於本實施型態中不使用種子，因而不須在 接觸孔24上形成單結晶⑪層。即，本實施型射，係在接 觸孔24上形成如非晶矽層或多晶矽層之矽層 25。此時，由 於在程序原理上，無法僅在接觸孔24上選擇性形成矽層 25,因而可利用在層間絕緣層23上所形成之回蝕程序、CMP 程序(化學機械研磨法）等去除。萬一，為了省略追加去除層 間絕緣層23上所形成之矽層之步驟，亦可與第1(幻圖同樣 地，在接觸孔上利用SEG程序形成單結晶矽層，但因SEG 程序有製造成本提高的問題點。 第2 (b)圖係顯示以觸媒在層間絕緣層2 3及矽層2 5上形 成金屬層26之步驟。金屬層26可包含Ni、a卜Ti、Ag、Au、In the semiconductor manufacturing method of the present invention, since the heat treatment temperature and the heat treatment time required for the crystallization of the amorphous germanium can be greatly shortened, the heat accumulation in the DRAM manufacturing process can be reduced, and the effect of improving the productivity of the SRAM 4 DRAM can be obtained. Further, the SRAM manufacturing method of the present invention does not require the use of a high-priced program for forming seeds, and has an effect of reducing the manufacturing cost of the SRAM. t. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the configuration of the present invention will be described in detail with reference to the accompanying drawings. In the SRAM manufacturing method of the present invention, a polycrystalline germanium layer is formed by a metal catalyst to reduce the crystallization temperature. A method of crystallizing an amorphous germanium by a metal catalyst is applied to a polysilicon thin film transistor (Poly Silicon Thin Film Transistor; Poly Si TFT) corresponding to a driving element of a flat panel display such as LCd. The most important procedure in the fabrication of a polycrystalline germanium TFT is a procedure for performing amorphous crystallization at a low temperature, and particularly preferably a crystallization temperature of 20 is lowered. Therefore, there are various proposals for forming a polycrystalline germanium at a low temperature and in a short period of time, and in particular, a method of coating a non-crystalline germanium with a metal catalyst such as Ni, Cu, or A1 to induce crystallization at a low temperature has been attracting attention. Here, the inventors of the present invention have focused on the crystallization of polycrystalline silicon by a metal catalyst during the manufacture of an LCD multi-TFT, and are also applicable to the SRAM multi-tft manufacturing, to the present invention. In other words, since the metal catalyst can be crystallized at a low temperature as long as the polycrystalline 7 layer of the formed polycrystal is crystallized, the productivity of the SRAM can be improved by shortening the heat treatment time under the same heat treatment temperature. Moreover, since the crystallization of seeds and even the polycrystalline layer can be carried out, it is also possible to use a ship method with a high cost. Thereby, the manufacturing cost of the SRAM can be reduced. Fig. 2 is a cross-sectional view showing a method of manufacturing the SRAM of the jth embodiment of the present invention. Similarly to Fig. 1, the '帛2 diagram is also taken as an example of a field equivalent to a portion of the signal array. Since the second (a) diagram is the same as the steps of the first (a) and (b) diagrams, detailed descriptions are omitted. However, since the seed is not used in the present embodiment, it is not necessary to form a single crystal 11 layer on the contact hole 24. That is, in the present embodiment, the germanium layer 25 such as an amorphous germanium layer or a poly germanium layer is formed on the contact hole 24. At this time, since the germanium layer 25 cannot be selectively formed only on the contact hole 24 in the principle of the program, it can be removed by an etch back process, a CMP program (chemical mechanical polishing method) or the like formed on the interlayer insulating layer 23. In order to omit the step of additionally removing the ruthenium layer formed on the interlayer insulating layer 23, a single crystal ruthenium layer may be formed on the contact hole by the SEG process as in the first (magic picture), but it may be manufactured by the SEG program. The problem of cost increase. Fig. 2(b) shows the step of forming a metal layer 26 on the interlayer insulating layer 23 and the germanium layer 25 by a catalyst. The metal layer 26 may contain Ni, ab, Ti, Ag, Au. ,
Co、Sb、Pd、Cu中任一或兩種以上之金屬，但考量SRAM 整體製造程序，以使用见為佳。金屬層26的形成方法並無 特別限定’但通常以使用半導體元件製造時所使用的方法 1359478 為佳。例如，可藉由如熱蒸鍍或濺鍍等物理蒸鍍法及如 LPCVD或PECVD法等化學蒸鍍法來形成。 金屬層26的厚度，可藉由在第2(d)圖步驟所形成之非晶 矽層28的厚度來決定。隨著非晶矽層的厚度增加的程度， 5 必要的金屬層厚度也會增加。在必須精密地調節金屬層26 的厚度的情形下，以利用化學蒸鍍法形成金屬層26為佳。Any one or two or more of Co, Sb, Pd, and Cu, but considering the overall manufacturing procedure of SRAM, it is better to use it. The method of forming the metal layer 26 is not particularly limited, but it is generally preferred to use the method 1359478 used in the manufacture of a semiconductor device. For example, it can be formed by a physical vapor deposition method such as thermal evaporation or sputtering, and a chemical vapor deposition method such as LPCVD or PECVD. The thickness of the metal layer 26 can be determined by the thickness of the amorphous germanium layer 28 formed in the step (d). As the thickness of the amorphous germanium layer increases, the thickness of the necessary metal layer also increases. In the case where the thickness of the metal layer 26 must be precisely adjusted, it is preferable to form the metal layer 26 by chemical vapor deposition.
另一方面，如本發明利用金屬觸媒之方式中，雖有可 進行非晶矽的低溫結晶化之優點，但由於TFT的作用區含有 相當量的金屬，故有漏茂電流增加的缺點。因此，為防止 10 如此的金屬污染，必須盡可能減少塗佈之金屬觸媒量。因 此，亦有必須將金屬層26的厚度調節至原子層單位以下的 情形。在如此的情形下，最好是利用原子層單位蒸鍍法 (atomic layer unit deposition)形成金屬層 26。在此，將金屬 層厚度調節至原子層單位以下的意義，不僅在將一層金屬 15 原子均一塗佈於全面積的情形，亦包含稀疏塗佈金屬原子 的情形。當然，除了原子層單位蒸鍍法外，亦可使用可盡 量將金屬層厚度調節至原子層單位以下之其他塗佈方法。 第2(c)圖係顯示將矽層25及金屬層26進行熱處理，且僅 在矽層25上形成金屬矽化物層27之步驟。此時，熱處理溫 20 度以250°C至500°C為佳；熱處理時間以30分至60分為佳； 且熱處理環境氪體以非活性氣體為佳。然後，去除不進行 金屬矽化物反應之層間絕緣層23上的金屬層26。去除方式 係使用濕式蝕刻，以SPM(硫酸過氧化氫混合物）溶液選擇性 僅去除金屬層。 11 1359478 第2 (d)圖係顯不形成非晶矽層2 8之步驟。非晶矽層的厚 度以100Α至200 Α範圍内為佳。如前所述，—般是使Ζ LPCVD法及PECVD法形成非晶石夕層。On the other hand, in the method using the metal catalyst of the present invention, although there is an advantage that the low temperature crystallization of the amorphous germanium can be performed, since the active region of the TFT contains a considerable amount of metal, there is a disadvantage that the leakage current increases. Therefore, in order to prevent such metal contamination, it is necessary to minimize the amount of metal catalyst applied. Therefore, it is also necessary to adjust the thickness of the metal layer 26 to a level below the atomic layer unit. In such a case, it is preferable to form the metal layer 26 by atomic layer unit deposition. Here, the meaning of adjusting the thickness of the metal layer to the atomic layer unit or less is not only a case where a single layer of metal 15 atoms is uniformly applied to the entire area, but also a case where the metal atoms are sparsely coated. Of course, in addition to the atomic layer unit evaporation method, other coating methods which can adjust the thickness of the metal layer to the atomic layer unit or less can be used. The second (c) diagram shows the step of heat-treating the ruthenium layer 25 and the metal layer 26, and forming the metal ruthenide layer 27 only on the ruthenium layer 25. At this time, the heat treatment temperature is preferably 20 ° C to 500 ° C; the heat treatment time is preferably 30 minutes to 60 minutes; and the heat treatment environment is preferably an inert gas. Then, the metal layer 26 on the interlayer insulating layer 23 which is not subjected to the metal telluride reaction is removed. The removal method uses wet etching to selectively remove only the metal layer with a SPM (sulfuric acid hydrogen peroxide mixture) solution. 11 1359478 The second (d) diagram shows the step of not forming the amorphous germanium layer 28. The thickness of the amorphous germanium layer is preferably in the range of 100 Å to 200 Å. As described above, it is generally the case that the ΖLPCVD method and the PECVD method form an amorphous layer.
第2 (e)圖係顯示將非晶矽層2 8進行結晶化熱處理，以形 成多晶石夕層29之步驟。X，萬一在接觸孔24上形成非晶石夕 層，在該過程中可在多晶矽層結晶化。此時，在第2(c)圖步 驟所形成金屬矽化物27擔任結晶化觸媒的任務。即，在熱 處理過程中，金屬矽化物在非晶矽層28内擴散，同時非晶 矽結晶化而成為多晶矽。 本發明中的熱處理溫度，以4〇〇ec至700°C範圍為佳。 在此，由於熱處理溫度過低，則結晶化所需的時間會增加， 因而必須考量到生產性(處理量）降低的問題點；熱處理溫度 過高，則必須考量到SRAM熱積存增加的問題點。熱處理時 間係由熱處理溫度決定。 15 本發明中，熱處理時間以1小時至10小時的範圍為佳。The second (e) diagram shows the step of subjecting the amorphous germanium layer 28 to crystallization heat treatment to form the polycrystalline layer 29. X, in the case where an amorphous layer is formed on the contact hole 24, in the process, the polycrystalline layer can be crystallized. At this time, the metal telluride 27 formed in the step (c) of Fig. 2 serves as a crystallization catalyst. That is, during the heat treatment, the metal telluride diffuses in the amorphous germanium layer 28, and the amorphous germanium crystallizes to become polycrystalline germanium. The heat treatment temperature in the present invention is preferably in the range of 4 〇〇 ec to 700 °C. Here, since the heat treatment temperature is too low, the time required for crystallization increases, so it is necessary to consider the problem that the productivity (treatment amount) is lowered; if the heat treatment temperature is too high, it is necessary to consider the problem that the SRAM heat accumulation is increased. . The heat treatment time is determined by the heat treatment temperature. In the present invention, the heat treatment time is preferably in the range of from 1 hour to 10 hours.
在此，必須考量到熱處理時間過短，則會導致多晶矽的結 晶性變差的問題點；且需考量到熱處理時間過長，則生產 性降低的問題點。考量到前述全部問題點，最好是在550°c 約3小時以上、600°C約1小時以上的條件下進行熱處理，將 20 非晶矽進行結晶化。當然，前述的熱處理時間可依接觸孔 間的距離稍微改變。 本發明中，熱處理時的環境氣體以非活性氣體為佳。 此時’所使用之非活性氣體包含Ar、Ne、He、N2。 第3圖係顯示本發明第2實施型態之SRAM製造方法之 12 第3 (a)圖係顯示在製造SRAM的MOSFET後，形成層間 絕緣層33及接觸孔34的步驟。相較於第2(a)圖，本實施型態 不形成擔任種子任務之單結晶矽層。 第3 (b)圖係顯示在層間絕緣層3 3及接觸孔3 4上形成金 屬層35之步驟。由於該步驟之相關全部内容與第丨實施型態 相同’故參考第2(b)圖的說明内容。 第3(c)圖係顯示將相當於源極/汲極32之接觸孔34的下 方矽層及金屬層35進行熱處理，並僅在源極/汲極32上形成 金屬矽化物層36的步驟。由於該步驟之相關全部内容與第i 實施型態相同，故參考第2(c)圖的說明内容。 第3(d)圖係顯示形成非晶矽層37的步驟。由於該步驟之 相關全部内容與第1實施型態相同，故參考第2(d)圖的說明 内容。 第3(e)圖係顯示將非晶石夕層37進行結晶化熱處理，以形 成多晶石夕層38的步驟。由於該步驟之相關全部内容與第1實 施型態相同’故參考第2(e)圖的說明内容。然而，由於本實 施型態中不使用種子’因而相較於第1實施型態，在相同的 熱處理溫度條件下，熱處理時間會稍微增加。 以上’本發明之方法係以具有TFT細胞之SRAM為例加 以說明，但亦適用於SRAM以外的半導體元件包含以多TFT 作為構造元件之情形。 又，本發明之方法，可適用於前述方法外之各種半導 體元件的製造程序。尤其適用於在半導體元件使用多晶矽 1359478 多晶矽配線層48之步驟。本發明中，熱處理溫度以4〇〇。匸至 700 C範圍為佳。在此，由於熱處理溫度過低，則結晶化所 需的時間會増加，因而必須考量到生產性(處理量）降低的問 題點；熱處理溫度過高，則必須考量到SRAM熱積存增加的 5 問題點。 熱處理時間係由熱處理溫度及非晶矽層46的摻雜濃度 來決定。本發明中，熱處理時間以1小時至10小時的範圍為 佳。在此，必須考量到熱處理時間過短，則會導致多晶矽 的結晶性變差的問題點；且需考量到熱處理時間過長，則 10生產性降低的問題點。 考量到前述全部問題點，最好是在^^(^約丨小時以上 的條件下進行熱處理，將非晶矽進行結晶化。因此，相較 於將非日日石夕固相結晶化（S〇Hd phaSe Crystallizatj〇n)，以形成 多晶石夕配線層之習知方法，本發明中，可大大降低多晶石夕 15配線層形成時結晶化的熱處理溫度與熱處理時間。 本發明中’熱處理時的環境氣體以非活性氣體為佳。 此時’所使用之非活性氣體包含Ar、Ne、He、。亦可視 障况’在含有〇2、N2〇、H2〇、臭氧氣體等氧化性氣體及含 有Η2、NH3氣體等還原性氣體下進行埶處理。 2〇 口 ’、 另-方面，利用本發明，以非晶石夕的結晶化觸媒所使 用之金屬’在多晶石夕配線層47與源極42及汲極43的邊界領 域办成金屬石夕化物層49。例如，在金屬觸媒使用见的情形 下，形成如懸、腦2等錦石夕化物。一般而言，金屬石夕化 物的比電阻明顯較多晶石夕小。藉此，本發明中，可大大降 15 1359478 低多晶矽配線層與其下方矽層間的接觸阻抗。 產業上可利用性 以上，本發明之方法係以DRAM為例加以說明，但除 了 DRAM以外，亦可適用於快閃記憶體元件、非記憶體元 5 件等所有半導體元件的多晶矽配線程序。因此，本發明的 產業利用性可謂非常高。Here, it is necessary to consider that the heat treatment time is too short, which may cause a problem that the crystallinity of the polycrystalline silicon is deteriorated; and it is necessary to consider the problem that the productivity is lowered if the heat treatment time is too long. In view of all the above problems, it is preferable to carry out heat treatment at 550 ° C for about 3 hours or more at 600 ° C for about 1 hour or more, and to crystallize 20 amorphous ruthenium. Of course, the aforementioned heat treatment time may vary slightly depending on the distance between the contact holes. In the present invention, the ambient gas during the heat treatment is preferably an inert gas. At this time, the inert gas used includes Ar, Ne, He, and N2. Fig. 3 is a view showing a method of manufacturing an SRAM according to a second embodiment of the present invention. Fig. 3(a) shows a step of forming an interlayer insulating layer 33 and a contact hole 34 after fabricating a MOSFET of an SRAM. Compared to Fig. 2(a), this embodiment does not form a single crystal ruthenium layer serving as a seed task. The third step (b) shows the step of forming the metal layer 35 on the interlayer insulating layer 33 and the contact hole 34. Since all the relevant contents of this step are the same as those of the third embodiment, the description of Fig. 2(b) is referred to. The third (c) diagram shows the step of heat-treating the lower germanium layer and the metal layer 35 corresponding to the contact hole 34 of the source/drain 32, and forming the metal germanide layer 36 only on the source/drain 32. . Since all the relevant contents of this step are the same as those of the i-th embodiment, the description of FIG. 2(c) is referred to. The third (d) diagram shows the step of forming the amorphous germanium layer 37. Since all the contents of this step are the same as those of the first embodiment, the description of Fig. 2(d) will be referred to. Fig. 3(e) shows a step of subjecting the amorphous layer 37 to a crystallization heat treatment to form a polycrystalline layer 38. Since all the relevant contents of this step are the same as those of the first embodiment, the description of Fig. 2(e) is referred to. However, since the seed is not used in the present embodiment, the heat treatment time is slightly increased under the same heat treatment temperature conditions as compared with the first embodiment. The above method of the present invention is described by taking an SRAM having TFT cells as an example, but is also applicable to a case where a semiconductor element other than the SRAM includes a plurality of TFTs as structural elements. Further, the method of the present invention can be applied to the manufacturing procedures of various semiconductor elements other than the above methods. It is particularly suitable for the step of using a polysilicon 1359478 polysilicon wiring layer 48 in a semiconductor device. In the present invention, the heat treatment temperature is 4 Torr. It is better to reach the 700 C range. Here, since the heat treatment temperature is too low, the time required for crystallization increases, so it is necessary to consider the problem that the productivity (handling amount) is lowered; if the heat treatment temperature is too high, it is necessary to consider the problem of the increase in the SRAM heat accumulation. point. The heat treatment time is determined by the heat treatment temperature and the doping concentration of the amorphous germanium layer 46. In the present invention, the heat treatment time is preferably in the range of from 1 hour to 10 hours. Here, it is necessary to consider that the heat treatment time is too short, which may cause a problem that the crystallinity of the polycrystalline silicon is deteriorated; and it is necessary to consider the problem that the productivity is lowered when the heat treatment time is too long. In consideration of all the above problems, it is preferable to heat-treat the amorphous germanium under the conditions of about 2 hours or more. Therefore, compared with the non-Japanese-day solid phase crystallization (S 〇Hd phaSe Crystallizatj〇n), a conventional method for forming a polycrystalline shi wire layer, in the present invention, the heat treatment temperature and heat treatment time for crystallization of the formation of the polycrystalline slab 15 wiring layer can be greatly reduced. The ambient gas during the heat treatment is preferably an inert gas. In this case, the inert gas used includes Ar, Ne, and He. It may also contain oxidizing properties such as 〇2, N2〇, H2〇, and ozone gas. The gas and the reducing gas such as ruthenium 2 and NH 3 gas are subjected to hydrazine treatment. 2 〇 ' ', and the other aspect, according to the present invention, the metal used in the crystallization catalyst of the amorphous ceramsite is wired in the polycrystalline stone. The metal 47 is formed in the boundary region between the layer 47 and the source 42 and the drain 43. For example, in the case where the metal catalyst is used, a ceramsite such as a suspension or a brain is formed. The specific resistance of the metal lithology is significantly more Therefore, in the present invention, the contact resistance between the low polysilicon wiring layer and the underlying germanium layer can be greatly reduced. Industrial Applicability The method of the present invention is described by taking a DRAM as an example, except for DRAM. In addition, it is also applicable to a polysilicon wiring program of all semiconductor elements such as a flash memory device and a non-memory device. Therefore, the industrial applicability of the present invention is extremely high.
另一方面，本說明書内藉由數個較佳實施型態記述本 發明，但其所屬技術領域中具有通常知識者應可在不脫離 附加之申請專利範圍所揭示之本發明範疇及思想，獲得多 10 數變形及修正。 L圖式簡單說明3 第1 (a)〜(d)圖係顯示習知SRAM製造方法之截面圖。 第2(a)〜(e)圖係顯示本發明第1實施型態SRAM製造方 法之截面圖。 15 第3(a)~(e)圖係顯示本發明第2實施型態SRAM製造方On the other hand, the present invention has been described in terms of several preferred embodiments, and those of ordinary skill in the art should be able to obtain the scope and spirit of the invention disclosed in the appended claims. More than 10 deformations and corrections. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1(a) to (d) are cross-sectional views showing a conventional SRAM manufacturing method. 2(a) to 2(e) are cross-sectional views showing a method of manufacturing the SRAM of the first embodiment of the present invention. 15 (a) to (e) show the manufacturer of the second embodiment of the present invention SRAM
法之截面圖。 第4(a)〜(d)圖係顯示本發明DRAM製造方法之截面圖。 【主要元件符號說明】 20、 30...石夕基板 21、 31…閘極 22、 32…源極/汲極 23、 33...層間絕緣層 24、 34...接觸孔 25...矽層 26、 35...金屬層 27、 36...金屬石夕化物層 28、 37...非晶矽層 29、 38...多晶矽層 16Sectional view of the law. 4(a) to (d) are cross-sectional views showing a method of manufacturing a DRAM of the present invention. [Main component symbol description] 20, 30... Shixi substrate 21, 31... Gate 22, 32... Source/drain 23, 33... Interlayer insulating layer 24, 34... Contact hole 25..矽 layer 26, 35... metal layer 27, 36... metal lithium layer 28, 37... amorphous germanium layer 29, 38... polycrystalline germanium layer 16
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| KR0160545B1 (en) * | 1994-12-05 | 1999-02-01 | 양승택 | Fabrication method of contact and via plug silicide |
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