TWI355683B - A dielectric barrier film - Google Patents

Description

(6) Protection of (6) 1355683 structure. These and other specific examples of the invention will be further discussed and explained below with reference to the following figures. [Embodiment] Application by Demar ay et al. in 2001, July 1st, the application name "Planar optical device and its manufacturing method" is 09/903,050 ('050 application). RF sputtering of oxide films is discussed in the same assignee of the present application, the entire disclosure of which is hereby incorporated by reference. Furthermore, in 2002, March 16th, the application 'Application No. 1〇/1〇1341, Assigned to the Same Assignee of the Invention', discussed in the reactor applicable to the present invention The subject matter is hereby incorporated by reference in its entirety for reference. A method for depositing oxides in a pulsed, biased manner is discussed further in U.S. Patent Application Serial No. 10/1 0 1 8 63, filed on March 16, the disclosure of which is incorporated herein by reference. The present application is hereby incorporated by reference in its entirety in its entirety in its entirety in the the the the the the the the the the the the the In a specific example, the device 10 can be modified, for example, by the Applied Komatsu, California, Santa Cruz, 600-D (600 X 5 00 mm substrate size) system, or by AKT-4300 from Applied Komatsu. The PVD (600 X 720 mm substrate size) system was retrofitted. The AKT-1600 reactor, for example, contains three or four deposition chambers connected by a vacuum transport chamber. These AKT PVD reactors (7) (7 1355683 can be modified so that when the raw material film is deposited, it is supplied to the target by a pulsed DC power source and supplied to the substrate by RF power. The device 10 includes a transmission filter 15 electrically coupled to the pulsed DC power supply 14 Target 12. In some specific cases, target 12 is a wide area splash A plating source target that provides a deposition material for deposition on the substrate 16. The substrate 16 is placed in parallel and placed relative to the target 12. When power is applied to the target 12, the target 12 is used as the cathode and the same Referring to the cathode, power is applied to the target 12, and a plasma 53 is generated under the target 12. The top of the target 12 is scanned by the magnet 20. The substrate 16 is capacitively coupled to the electrode 17 through the insulator 54. Coupling to RF Power Supply When performing on device 1 ,, for pulsed reactive DC magnetron sputtering, the polarity of the power supply supplied by the power supply 14 to the target 12 will be at a negative potential and positive The potential varies between potentials. During the positive potential, the insulating layer on the surface of the target 2 will discharge and prevent arcing. To obtain arc-free deposition, the pulse frequency will exceed the critical frequency, which is the target material of the critical frequency. Depending on the cathode current and the reversal time, a high quality oxide film can be completed using reactive pulsed DC magnetron sputtering in device 10. Pulsed DC power supply 14 can be any pulsed DC power supply. , for example by Advanced Energy AE Pinnacle plus 10K manufactured by the company. This embodiment supply can supply a pulsed DC power supply up to I 〇 kW at a frequency between 350 KHz. The reverse voltage is the negative voltage of 负%. The power supply can also achieve different power characteristics, frequency characteristics, and percentage of reversal voltage. The reversal time of the specific example of the electric 'source supply 14 can be adjusted between 0 and 5 μ5. -10- (9) (9) 1355683 Figure 2A shows a specific example of a dielectric stack 120 that can serve as a barrier layer. Dielectric stack 120 includes multiple layers 10, 1, 2, 1 , 3, 104, and 105, each of which utilizes the deposition method described in U.S. Patent Application Serial No. 10/100,86, 3, et al. Deposited in a manner generally illustrated in device 10. In general, the dielectric stack 120 can include any number of layers. A particular embodiment of the barrier stack 120 described herein has five layers, layers 1, 1, 1, 2, 103, 104, and 105. The dielectric stack 120 shown in Fig. 2A is formed of a high refractive index material such as titanium oxide (Ti02). Layers 102 and 104 may be formed of a low refractive index material such as cerium oxide (SiO 2 ) which may be doped with aluminum oxide (e.g., 92% ceria and 8% alumina in terms of percentage of cations). The barrier stack 120 can be deposited directly onto the substrate, as shown in Figure 2A, or deposited on layer 107, as shown in Figure 2D. Layer 107 is a layer that is intended to prevent atmospheric pollution or physical damage and may include optical or electrical devices or another layer. Substrate 100 is a substrate on which layer 107 or dielectric stack 120 is formed. In some embodiments, the substrate may also provide a barrier to the atmosphere of the layer 107. Table 1 illustrates the deposition parameters of certain embodiments of the dielectric stack 20 according to the present invention as described above, biased pulsed DC reactivity as further described in U.S. Patent Application Serial No. 1 0/1 0 1,863. Scanning the magnetron PVD method, each stack I 2 0 illustrated in Table 1 is formed with an AKT 4 3 00 PVD system, which is hereby incorporated by reference. Furthermore, the apparatus 10 as described above with respect to Figures 1A and 1 B can be mounted in the AKT 4300 PVD system together with a load lock chamber, a gas escape chamber, and can be equipped with a plasma shield or Shade the heater. As shown in the figure (10) (10) 1355683 2A, the dielectric stack 120 used in these embodiments comprises a staggered layer of 5 layers - 3 layers of titanium dioxide and 2 layers of cerium oxide / aluminum oxide (with cations) Concentration meter 92% / 8%). A dielectric stack 120 for each of the stacks shown in Table 1 was deposited directly on the substrate 100. First, the substrate 1 for each of the formed stacks is placed in the wafer transfer chamber of the apparatus 10. The wafer transfer chamber of device 10 is pumped to a substrate pressure of about 2 x 1 〇 6 Torr. The substrate 100 is then sheeted, which may be glass or plastic, transported to the heating chamber of the apparatus 10 and maintained at a temperature of about 3 ° C for about 20 minutes to allow the accumulated moisture of the substrate 1 to escape. . For polymer-based substrates, for example, the preheat step can be eliminated and the substrate heater and shield heater of device 10 can be eliminated. The substrate column of Table 1 shows the composition of the substrate 100 used in the deposition method. In each of the stacks 1 to 6 illustrated in Table 1, the composition of the dielectric stack 120 is Ti02/92-8/Ti02/92-8/Ti02, indicating that the layers 101, 103, and 105 shown in FIG. 2A are The Ti02 layer, while the layers 102 and 104 shown in Fig. 2A are Si〇2/Al203 (92°/./8% in terms of cation concentration). The Ti 02 layer was deposited using the parameters shown in the Ti02 deposition method. The details of the method are illustrated with the nominal power/bias power/pulse frequency/air flow/oxygen flow/deposition time. The nominal power represents the power applied to the target 12 of the device 10. The bias power represents the power supplied from the bias generator 18 to the electrode 17, and the substrate 16 shown in Fig. 1A is mounted on the electrode 17 and capacitively coupled to the electrode 17 by a substrate. The flow of air through the substrate and the flow of oxygen are then illustrated in units of standard cubic centimeters per minute (seem). Finally, the deposition time is obtained. For example, using a nominal RF power of about 7 k\V, with a bias power of about 200 W '-13-(11) (11) 1355683 pulse frequency of about 200 KHz, about 60 seem oxygen flow rate, about 90 seem The oxygen flow rate, and a deposition time of about 950 seconds, was deposited for the 1 丨 02 layer of the stack number 1 described in the table. The measured thickness of the typical Ti02 layer deposited according to the method described in the Ti02 deposition method column is shown in the 1彳02 measurement thickness column of Table 1. Similarly, the deposition parameters for depositing the cerium oxide/alumina layer of each of the dielectric stacks 1 2 shown in Table 1 are shown in the cerium oxide/alumina (92/8) deposition method column. As shown, each of the layers used in the cerium oxide/alumina layer of the stack numbers 1 to 6 shown in Table 1 was about 92% cerium oxide and about 8% alumina in terms of cation concentration. For example, in the stack number 1 illustrated in Table 1, a power of about 3 kW is applied to the target I 2 to deposit a cerium oxide/alumina layer, and a bias power applied to the electrode 17 is about 200 W, pulse. The DC power supply 14 has a frequency of about 200 kHz, an argon flow rate of about 85 seem, an oxygen flow rate of about 90 sccm, and a deposition time of about 1, 〇〇 5 seconds. Among the layers of the stack described in Table 1, the reversal time of the pulsed DC power supply 14 was fixed at about 2.3 microseconds. The spacing between the target I 2 and the substrate 100 is about 60 mm, and the spacing between the magnet 20 and the target 2 is about 4 to 5 mm. The temperature of the substrate 100 was about 200 ° C, and the shielding heater of the apparatus 10 was set to about 2 50 °C. The origin offset of the magnet 20 was set to about 20 mm and the scanning length was about 980 mm. When the Ti02 layer is deposited, the total pressure in the plasma 53 inside the chamber 10 of the apparatus 10 is about 5 to 6 mT. When depositing the ruthenium dioxide/alumina layer, the total pressure in the plasma 5 3 inside the deposition chamber of the apparatus 10 is about 8 to 9 m T . (12)1355683

1 CN has m ? fi 画 ^ ^ m to _ II S' : 980 ί i 1 1_ Ο Os 1000 1000 1000 1000 m , with tan m ^ , m ^ 5 ^ S «A II ^ 3KW/200W/200K Hz/ 85 Argon / 90 Oxygen / 1005 0 C! minus 1 ϊ , Ό VO 彡 = ο Ν ° m, 2 o ci嘁| | ^ 2? S ^ N ° Π 〔 [ 3KW/200W/200K Hz/85 Argon / 90 Oxygen/1025 3KW/200W/200K Hz/85 Argon/90 Oxygen/1025 3KW/200W/200K Hz/85 Argon/90 Oxygen/1025 Ti〇2 Measurement Thickness (A) 580 Ο 550 550 550 550 1'1 〇2 deposition method 7KW/200W/200 KHz/60 argon/90 oxygen/9 5 0 seconds 7KW/200W/200 KHz/60 argon/90 oxygen/83 5 seconds 7KW/200W/200 KHz/60 argon/90 oxygen/ 901 seconds 7KW/200W/200 KHz/60 argon Z90 oxygen/901 seconds 7KW/200W/200 KHz/60 argon/90 oxygen/901 seconds 7KW/200W/200 KHz/60 argon/90 oxygen/901 seconds stacked layer composition 1 Ti02/92-8/Ti02/92-8/Ti〇2 Ti02/92-8/Ti02/92-8/Ti02 Ti02/92-8/Ti02/92-8/Ti02 Ti02/92-8/Ti02/92 - 8/Ti02 Ti02/92-8/Ti02/92-8 丨1 Ti02/92-8/Ti02/92-; 8/Ti02 Substrate^ dr 蕤t = κ® + β Ε <;^ + m 7 7_ i: nig ^ m ^ 1 v ^ s + ^ fr ^ ^ ^ mm ,vm ΓNorth-North fr mm ^ mm 4 microscope slides W Sis followed by + . Τ m m ^ ^ m stack # - (N-inch VO

-15 - (13) 1355683 In the barrier stack according to the present invention, the method is described as "one or more reactive splashes" by a pulsed, biased deposition method previously described in U.S. Application Serial No. 10/10],863. The plated film layer is deposited as a barrier layer pulsed, biased deposition method combined with a unique state of the art optical quality vacuum film with a tubeless columnar defect, the optical quality vacuum film is generally uniform in parts per million The level and control of the refractive index of the light and the bi-fold unbiased vacuum film. The extremely high resolution ellipsometer also confirms that the product has zero extinction coefficient across the visible and near-infrared regions, and the uniformity is in the order of several parts per million to provide a perfect transparency of the refractive index of the surrounding film. As a result of high densification and low defect concentrations, these extremely transparent films were also able to provide internal moisture with excellent diffusion barrier protection as measured by vapor permeation. Finally, it can be confirmed from the same film that under the action of high voltage stress, there will be a much higher dielectric, and a lower defect result can be obtained. Figure 8 shows the product after prolonged exposure to high humidity and high temperature environments. In the sample shown in Figure 8, about 200 nm of TiO 2 was deposited on the 4" 矽 wafer reactive aluminum layer. The sample was held at ° C for about 500 hours in a deposition with a relative humidity of about 100%. As seen from the eighth, there is no defect on the wafer, which means that the underlying reaction layer is highly protected. Figure 9 shows the cerium oxide according to the present invention after prolonged exposure to high humidity 'high temperature environment. Sample of the /alumina layer. In the sample of Figure 9, aluminum of about 〇nm was deposited on a 4" wafer. A 00 nm cerium oxide/alumina was deposited on aluminum. The sample is then placed in an approximately [25] patent. The dense shape is uniform and can be broad and wide, and the product of about 85 graphs of the thin aluminum loss is about -16-(14) (14)1355683 Approximately 3.5 pm in a pressure cooker of approximately 3.5 atm saturated steam. Again, no defects were seen on the wafer' which indicates that the underlying reactive aluminum layer is highly protected. Deposition of selected metal oxide thin films from previously described methods, from tens of nanometers to more than 15 microns, not only acts as a film but is not affected by moisture and chemical permeation, but as an optical, electrical and/or abrasive layer or In the case of the device, it is also possible to provide protection to the lower layer or the protection device from the influence of gas or moisture entering the interior' to provide substantial manufacturing and environmental limits for the individual layers and devices. The method of the present invention has been demonstrated with wide area glass and metal substrates, as well as low temperature materials such as plastics. Returning to Figure 2A, a dielectric stack is deposited on the substrate 1 〇 2〇. Substrate 100 can optionally be a glass 'plastic, metal or semiconductor substrate. The layer thickness of the dielectric stack 120 can be varied to form an anti-reflective coating or a reflective coating. Figure 2B shows a transparent 'conductive layer 106 deposited on the dielectric stack. The transparent conductive layer 1〇6 may be, for example, a thin oxide layer of indium. Figure 2C illustrates substrate 100 deposited as a top surface and a bottom surface of substrate 1 with dielectric stack 120. The specific embodiment shown in FIG. 2C includes a dielectric stack 120 and a dielectric stack 2 deposited on the top surface of the substrate 1以 with layers 1, 102, 103, 104, and 105. In another embodiment, the dielectric stack 20 is deposited as a layer 108, 109, 110, 111, and 112 on the bottom surface of the substrate 100 as shown in FIG. 2C. Further, the layers 〇8, 11 0 and 1 ] 2 may be a high refractive index layer (for example, a TiO 2 layer) according to the present invention, and the layers 109 and Π 1 may be a lower refractive index layer such as a ceria/alumina layer. . An example of the deposition parameters of the dielectric stack 120 is seen in Table 1. -17 - (16) (16) 1355683 A transparent conductive layer 3] 4, such as indium tin oxide, is deposited over the dielectric stack 3 1 5 . Layer 31 may be an electroluminescent layer, for example, a phosphorus doped oxide or fluoride material or an organic light emitting polymer, an OLED (optical light emitting diode) or a polymer stack. A metal layer 3 1 2 is deposited on the side adjacent to the layer 3 1 3 , which may be doped with calcium or boron. A second dielectric stack 317 can be formed on the bottom of the substrate 316. The structure 321 illustrated in Figure 3 is an embodiment of a microcavity-enhanced LED protected by dielectric stacks 3 15 and 31 17 to protect it from water and reactive gases that can diffuse into the substrate 3 i 6 . . If layer 31 is a metal layer, a microcavity is formed between layer 312 and dielectric stack 315. The dielectric stack 315 blocks light emitted by the electroluminescent layer 313. Layer 3 1 3 illuminates when a voltage is applied between the transparent conductive layer 314 acting as the anode and the conductive layer 312 acting as the anode causing the layer 313 to be electrically deflected. The dielectric stack 3] 5 and the layer of the dielectric stack 317 may be arranged to include the light emitted by the layer 3] 3 between the layer 317 and the metal layer 3] 2 to form an etalon arrangement along the substrate 3 i 6 Guide the light. In addition, the dielectric stack 3 17 can be disposed to transmit light generated by the layer 31 to thereby form a monitor configuration in which the light is substantially perpendicular to the substrate 3 . Figure 4 shows an embodiment of a bottom gate transistor structure 2 2 in accordance with the present invention. A crystal structure 422 is formed on the substrate 41 6 , and the substrate 4 6 can be a plastic glass material. As in the specific example illustrated in FIG. 4, the dielectric stack 415 according to the present invention is deposited on the top surface of the substrate]6, and the second layer according to the present invention is deposited on the bottom surface of the substrate]16. Electrical stack 4]7. For example, the dielectric stacks 4] 7 and 4] 5 may each comprise a layer of high refractive index and low refractive index pen material. The high refractive index and low refractive index dielectric materials, Examples 19-(17)(17)1355683, such as the Ti 02 and cerium oxide/alumina layers described above, each containing a low voltage flat strip and a low surface defect, Therefore, it is suitable for a thin film transistor structure. A semiconductor layer 423 is deposited on the barrier stack 41 5 and patterned. The semiconductor layer 42 3 may be a semiconductor such as germanium or germanium, or may be a zinc oxide or a polymer material. Layers 424 and 425 form a source layer and a germanium layer in contact with semiconductor layer 423. Layer 426 can be formed of a high dielectric constant material, such as any dielectric layer that forms dielectric stacks 4 1 5 and 41 17 and is discussed herein, such as a high dielectric strength Ti02 material deposited by the methods described herein. Layer 42 7 is the intermediate layer and layer 428 is the smear metal. Figure 5 shows an embodiment of a top gate transistor device 529. A crystal structure 529 is formed on the substrate 516 to protect the substrate 516 from atmospheric contamination (e.g., water or gas) and physical wear, as well as wear of the dielectric stacks 5 15 and 5 17 . The dielectric stacks 5] 5 and 5 17 are formed from one or more layers of optical material when the dielectric stack is discussed above. A gate layer 530 is deposited over the dielectric stack 51. Layer 530 can be a metal layer such as aluminum or chromium. A gate oxide layer 531 is deposited over layer 530. Semiconductor layer 532 can be similar to layer 423 of FIG. The layers 53 3 and 534 are a source layer and a germanium layer, respectively, similar to the layers 424 and 428 of Fig. 4, and may be composed of, for example, a conductive metal, a conductive oxide or a conductive polymer. Figure 6 shows another structure 6 3 3 embodiment having a microcavity-enhanced LED structure 3 2 as illustrated in Figure 3, which has a structure such as that shown in Figures 2A through 2F 622 is covered and protected. As shown in Fig. 6, layers 3] 4, 3 1 4 and 3 1 2 in structure 3 2 ] have been patterned. The structure 622 deposited on the opposite side of the substrate 61 9 with the dielectric stacks 6] 8 and 62 0 can be independently formed -20-(18) 1355683. The dielectric stacks 6 1 8 and 6 ] 9 are formed as described in the description of the dielectric stack i2 of FIGS. 2A to 2F. Structure 262 is then epoxidized on structure 321 to seal and protect structure 321 . The epoxy layer can be, for example, an EVA epoxy resin. Figure 7 shows another structure 700 having the embodiment of the microcavity enhanced LED structure 321 illustrated in Figure 3, which is shown in Figures 2A through 2F. Structure 6 2 3 is covered and protected. The cover structure 6 2 3 includes a substrate 619' that is epoxidized to adhere to the device 321 and a substrate 619 has a dielectric stack 620 deposited. Fig. 1 illustrates transmission data collected by the dielectric stack according to the present invention. The metric measurement device used to retrieve the data obtained in the figure is the 'Perkin E】mer λ_6 spectrometer. The 4 samples were measured and each sample was as discussed above - a 5-layer stack of Ti02/92-8. 2 The samples have the same thickness layer (Ti 2 at 55 nm and 92-8 at 100 nm). It can be seen that almost the same transmission spectrum of the two different experiments confirms the repeatability of the deposition method. The third embodiment has different thickness settings for biasing the transmission spectrum to blue. The fourth embodiment was produced after the third embodiment and maintained under the test conditions of 8 5 / 8 5 (85 ° C 8 5 % humidity) for 1 20 hours. It can be seen that humidity and heat have no significant impact on the transmission characteristics of the mirror stack, and the function of the dielectric stack as a protective layer is again confirmed. FIG. 10 shows a cross-sectional SE diagram of an exemplary dielectric stack according to the present invention. formula. Again showing five layers of Ti02 / sulphur dioxide - oxidized ingot stack with 550 nm thick ΊΊ〇 2 layer and 970 nm sulphur dioxide - oxidized (92-8) 〇 shows that ion-biased film provides protection in the orientation Electron and Optical Thin-21- (19) (19)1355683 Membranes, such as Photovoltaic Films, 'Semiconductor Films and Electroluminescent Films, Especially Electrodes Doped with Calcium or Other Reactive Metals and Other Hygroscopic or Significant advances have been made in the goal of appropriate barriers for organic light-emitting diodes of reactive materials. However, to date, most of the biasing methods used to produce films, filtered cathode vacuum arc coating techniques or FCVAC methods, have contained particle densities greater than about one defect per square centimeter. This method uses a high sputter rate at high voltages that can cause surface roughening. Undoubtedly, the presence of particles indicates that water vapor or oxygen can diffuse through the defect. In addition, the surface roughness formed by the FCVAC method impacts stress and morphology, and also impacts transparency and uniformity of refractive index. The sputtered film may be peeled off from the processing chamber shield or drawn to the surface of the film by a large electrostatic field present in the ion beam method. In any case, because many of the films do not cover particles larger than the film thickness, leaving particles that are several times larger than the film thickness, the particle defect density of particles larger than the film thickness also determines the pinhole density or other. Defects caused by discontinuous deposition of the film. The dielectric stack according to the present invention has a very fine smooth film surface&apos; independent of film thickness and non-zero but unmeasurable film transparency also represents a new capability for bias barrier film defect levels and barrier protection. There are few products that require dielectric barrier protection for moisture and oxygen, such as the '0 LED display, which can tolerate defects per square centimeter. In the method of the present invention, a thin film as thin as 2.5 nm and thick to 5 μm has been deposited, and the film has an average surface roughness of about 2 nm, which means no damage and can be expressed. An optical quality surface that satisfies the uniformity of the amorphous film and satisfies all film thicknesses of -22-(20) 1355683. The ultrathin reactive metal film capable of protecting aluminum according to the dielectric layer of the present invention is shown to have a thermal oxidation of water vapor of from 125 to 250 ° C for hundreds of hours at a pure water vapor pressure of 3.5 atm. 〇mm矽 There are defects on the wafer. Thus, it is apparent that both the titanium oxide and the aluminum niobate film as described in the present disclosure can provide a reactive film for long-term protection, with up to or two wafer areas without pinholes. There is a pinhole in the protective dielectric barrier layer on the 1 〇〇 mm wafer. The area of the wafer is approximately 75 cm 2 and is converted to a pinhole density of approximately 1 0 1 3 3 per square centimeter. Because there are two wafers, one contains aluminum silicate and the other contains titanium oxide barrier dielectric coating, there is no difference, the total area is 150 square centimeters. If there are 1 defect on the two wafers, the defect density is 0.00666 per square centimeter. However, since the wafer is free of defects, the actual defect density cannot be measured by the results of the two wafers alone. The actual defect density is less than 0.0133 per square centimeter. The various embodiments of the present invention can be provided by the above disclosure. However, it will be apparent to those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Accordingly, the invention is limited only by the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A and 1B illustrate a deposition apparatus for depositing a barrier layer film according to the present invention. 2A, 2B, 2C, 2D, 2D and 2F illustrate an embodiment of a device comprising a dielectric stack according to the invention. -23 - (21) (21) 1355683 Figure 3 shows a microcavity. Enhanced LED structure using a dielectric stack according to the present invention. Figure 4 shows a bottom gate transistor device incorporating a dielectric stack in accordance with the present invention. Figure 5 shows a top gate transistor device containing a dielectric stack in accordance with the present invention. Table 6 shows an embodiment of a similar microcavity-enhanced LED structure that is no longer protected by a dielectric stack structure. Figure 7 shows another embodiment of a similar microcavity-enhanced LED structure that is no longer protected by a dielectric stack structure. Figure 8 shows an example of a titanium dioxide film deposited on a reactive aluminum layer without prolonged exposure to a high humidity, high temperature environment. Fig. 9 shows an example of a ceria/alumina film which is deposited on a reactive aluminum layer without being exposed to a high humidity, high temperature environment for a long period of time. The figure shows an SEM photograph of a cross section of a dielectric stack in accordance with the present invention. The figure shows a plot of transmittance versus wavelength for various embodiments of a dielectric stack in accordance with the present invention. Elements having the same reference numerals have the same or similar functions in this figure. [Description No.] 1 0 Reactor device 12 Target-24- (22) Pulse DC power supply filter substrate electrode RF power supply magnet plasma plasma insulator substrate layer layer transparent conductive layer Layered Layer Substrate Dielectric Stack-25- (23) Metal Layer Electroluminescent Layer Transparent Conductive Layer Dielectric Stack Substrate Second Dielectric Stack Microcavity Enhanced LED Structure Dielectric Stack Second dielectric stack bottom gate transistor structure layer layer layer dielectric stack substrate dielectric stack top gate transistor device interlayer gate oxide layer semiconductor layer -26 - (24) Layer dielectric stack substrate dielectric stack epoxy layer structure covering structure structure -27 -

Claims (1)

1355683_ Amendment Addendum 5Α: Amendment No. 093105204 Scope of Patent Application Amendment of the Republic of China, May 24, 2014 Revision, Patent Application 1. A method of forming a barrier layer, comprising: providing a target: placing a surface area smaller than the base of the target Applying a pulsed direct current to the target to vary the voltage of the target between negative voltages; applying an RF (radio frequency) bias to the substrate; applying a narrow band rejection filter to the target Pulsed direct rejection of the RF (radio frequency) biased frequency current applied to the substrate: forming a portion of the barrier layer in the highly densified, amorphous dielectric deposited on the substrate, the highly densified material The barrier is less than one permeable defect concentration per square centimeter. 2 _ The method of claim 1, wherein the composition is formed by a target comprising 92% aluminum and 8% bismuth. 3. The method of claim 1, wherein the composition is formed by a target comprising titanium. 4. The method of claim 1, further comprising forming a stack of densified material layers, wherein the stack is not affected by environmental pollution. 5. The method of claim 1, further comprising a stack of shaped densified material layers wherein the stack is resistant to the target; positive voltage and galvanic discharge and material, the wall layer having an electrical material system The electrical material is formed into a stack containing the high-permeability and containing the high physical wear 1356683 3_, as in the first aspect of the patent application, and further comprising forming a stack comprising the highly densified material layer, wherein the stack is anti-reflective coating. 7. The method of claim 1, further comprising forming a stack comprising the highly densified layer, wherein the stack is a reflective coating. 8. The method of claim 1, wherein the barrier The layer includes a Ti 2 0 2 layer. 9. The method of claim 1, wherein the barrier layer comprises an alumina/ceria layer. 10. The method of claim 1, wherein the barrier layer is also an optical layer. 1 1 · The method of claim 1, wherein the barrier layer is also an electrical layer. 1 2. The method of claim 11, wherein the barrier layer comprises a capacitive layer. The method of claim 1, wherein the barrier layer comprises a resistive layer. 1 4. The method of claim 13 wherein the resistive layer is an indium-tin metal or an oxide. 15. The method of claim 14, wherein the barrier layer comprises a tribological layer. 16. The method of claim 1, wherein the water vapor transmission rate is less than about lxlO - 2 gm/m2/day. 17. The method of claim 1, wherein the optical attenuation in the continuous film is less than about 〇1 dB/cm. The method of claim 1, wherein the barrier layer has a thickness of less than about 500 nm. 19. The method of claim 1, wherein the barrier layer is used as a gate oxide of a thin film transistor. 20. The method of claim 1, further comprising depositing a second highly densified 'unshaped dielectric material, wherein the barrier layer comprises the highly densified, amorphous dielectric material being highly densified, Unshaped dielectric material. 〃 2 1. As in the method of claim 20, the highly densified, amorphous dielectric material layer in the product # is an aluminum oxide layer, and the two highly densified, amorphous dielectric material layers It is a layer of titanium oxide. -3-