TWI237902B - Method of forming a metal-insulator-metal capacitor - Google Patents

Abstract

The present invention discloses a method of forming a capacitor includes: to sequentially form a barrier layer, a second dielectric layer, and a conductive layer on a surface of a first dielectric layer and conductors in the first dielectric layer, to perform an etching process to remove portions of the barrier layer, the second dielectric layer, and the conductive layer to form the capacitor, and to perform a contacting process to connect the conductive layer of the capacitor to a first terminal through a first contact plug.

Description

1237902 Case No .: 93114577 Amended on May 13, 1994 玖 Description of the invention: [Technical field to which the invention belongs], especially a type of capacitor The invention provides a method for manufacturing a capacitor for a copper process (Metal-Insulators ~ Metal Electrical MIMC). (metal-insulator-metal capacitor, [previous technology] In recent years, the integrated circuit industry has continued to flourish, from the early days # 红 # $ qing, the body chip and the central processing unit chip (CPU chip) 'and even the current response The communication chips generated in the era of communication have all evolved towards high power & low price and small size. In other words, the industry has invested huge manpower and material resources in order to integrate the chips. Research on design and materials and processes # Breakthroughs in the exhibition to achieve the above goals. Early in the production of various wafers: The metal interconnects used were aluminum interconnects. However, the requirements of product specifications continue to increase Copper process technology has gradually become mainstream. This is because copper has a low resistance. Compared with Minglian, it can carry a larger current in a smaller area, so it is easier to reduce RC delay and improve the reliability of metal wiring. , Reduce the wiring area, reduce power consumption, etc. Especially after the copper-related process and equipment gradually mature, this trend is even more obvious. Among the key components used in integrated circuit products, capacitors have always been a very important component. When making capacitors, the choice of material and the quality of the process will ultimately affect the capacitance of the capacitor element ( capacitance value), reliability, dispersion behavior, and high-frequency characteristics, etc., then affect the overall performance of the chip. Especially when capacitors are used in communication chips, high-frequency characteristics are more important, because communication chips In fact, it can be regarded as a radio frequency integrated chip (RF integrated chip) '1237902 Case No .: 93114577 The amendment on May 13, 1994 is usually applied in the high frequency range. When the quality factor of the capacitor element (Quality f actor) is not stable enough, it will certainly produce unexpected energy loss (energy) and noise (noise), which will greatly reduce the performance of the chip. Please refer to Figure 1 to Figure 5, Figure 1 to Figure 5 Knowing the method of making an electric valley 38 on a chip 10, as shown in Figure 1, it is known to make a capacitor on a chip 10. The law system first provides wafer 10, and as mentioned earlier, the metal interconnects in wafer 10 are made using copper process technology. Due to the structure on wafer 10, it depends on the type of wafer after completion. Different, therefore, no special explanation is given here. In addition, due to the strong permeability of copper atoms, the copper process is a highly polluting process, so the capacitor is usually made on the top copper wire. The copper wire 12 is fabricated in a first dielectric layer 14. In fact, the copper wire 12 and the first dielectric layer 14 are manufactured simultaneously through a chemical mechanical polishing (CMP) process. Next, a first deposition process is performed to form an isolation layer 16 on the surface of the wafer 10. The isolation layer 16 is a silicon nitride layer and covers the copper wire 12 to block the copper atoms in the copper wire 12 from upward. diffusion. Then, a first conductive layer 18 is formed on the surface of the isolation layer 16. The first conductive layer 18 is a TaN layer or a TiN layer. SpUttering) process. Subsequently, after coating a photoresist layer (not shown) on the surface of the first conductive layer 18, a first mask and a first photolithography process are used to define a patterned photoresist The layer 'is used as a bottom electrode plate pattern 24. As shown in FIG. 2, a first etching process is performed, and the lower conductive plate pattern 24 is used as a mask to etch the first conductive layer 18 down to the surface of the isolation layer 16 to form a lower electrode plate of a capacitor (not shown). 26. As shown in FIG. 3, after removing the lower plate pattern 24, a second deposition process is performed to form a second dielectric layer 28 on the surface of the wafer 10. The second dielectric layer 28 includes a silicon oxide layer or It is a silicon nitride layer and covers the lower electrode plate 26. Next, a second conductive layer 32 is formed on the surface of the second dielectric layer 28. 1237902 Case No. 93114577 May 13, 1994 Revised the second conductive layer 3 2 to be a nitride group layer or a nitride layer , And formed by another cheap bond process. Then, after coating another photoresist layer (not shown) on the surface of the second conductive layer 32, a second photomask and a second lithography process are used to define a patterned photoresist layer for use as A top electrode plate pattern 34 is made. As shown in FIG. 4, a second etching process is subsequently performed, using the upper electrode plate pattern 34 as a mask, and the second conductive layer 32 and the second dielectric layer 28 are etched down to the surface of the first conductive layer 18 to form a surface. The capacitor plate 36 and the capacitor dielectric layer 42 are on the capacitor 36, and the capacitor 36 is completed. As shown in FIG. 5, after the upper electrode plate pattern 34 is removed, a third deposition process is performed to form a third dielectric layer 44 on the surface of the wafer 10, and the third dielectric layer 44 covers the capacitor 36. Next, a contact process is performed to form a first contact plug 46 and a second contact plug 48 in the third dielectric layer 44 to use the first contact plug 46 and the second contact plug 48 to separate The upper electrode plate 38 and the lower electrode plate 26 of the capacitor 36 are connected to a first terminal 52 and a second terminal 54. In fact, the first terminal 52 and the second terminal 54 are different Al bonding pads for electrically connecting different voltages. However, the conventional method of making capacitors requires two photomasks to define the upper and lower plate patterns. In other words, two yellow light and etching processes are required, making the process very tedious, and therefore increasing the cost, sometimes even Yield decline due to complicated steps, which will affect the performance of the completed wafer. In addition, in terms of the characteristics of the capacitor itself, when the resistance of the upper and lower plates is low, it actually helps the characteristics of the capacitor. Therefore, in the conventional technology, only tantalum nitride or titanium nitride is used as the capacitor. The material of the upper and lower plates is not a good choice. As far as the copper metal interconnects are concerned, although their own resistance is low enough, it is not possible to use part of their structure as an electrode because of the diffusion of copper atoms. Therefore, how can we develop a new method for making metal-insulator-metal capacitors, which not only does not need to perform two yellow light and post-cut processes, but can also use a copper metal layer as part of the electrode plate to make To produce capacitors with excellent characteristics, or to retain the original two yellow light and etching 1237902. Case No .: 93114577 May 13, 1994 Revised process, but you can make capacitors with other advantages, such as high capacitance value, become Very important subject. [Summary of the Invention] The main purpose of the present invention is to provide a method for manufacturing a capacitor, in particular, a method for manufacturing a metal-insulator-metal capacitor in a copper manufacturing process to solve the above problems. In a preferred embodiment of the present invention, a method for fabricating at least one capacitor on a semiconductor substrate is provided. The surface of the semiconductor substrate includes at least a first dielectric layer and at least one conductive object disposed on the first substrate. Among the electrical layers, the method includes: sequentially forming a barrier layer, a second dielectric layer, and a conductive layer on the surface of the semiconductor substrate, and the barrier layer is in direct contact with the conductive object, and then An etching process is performed to remove a portion of the barrier layer, the second dielectric layer, and the conductive layer, and the patterned barrier layer, the second dielectric layer, and the conductive layer constitute the capacitor, and a A contact process is used to connect the conductive layer of the capacitor to a first terminal using a first contact plug. Due to the method for manufacturing a capacitor of the present invention, a copper wire and a barrier layer are used as the lower electrode plate of the capacitor. On the premise that the exposed copper wire is satisfied, the copper wire can be smoothly connected to the terminal. Only one yellow light and etching process is needed to complete the capacitor production. Therefore, not only the manufacturing process is shortened, but also a copper wire can be used as a part of the lower electrode plate to produce a capacitor with better characteristics. At the same time, costs are reduced and yields are improved. In addition, with the original two yellow light and etching processes, capacitors with high capacitance values can be made, and the design of the capacitors is more flexible. When the method of the present invention is used to make a capacitor on a specific wafer, the performance of the wafer can be improved. 1237902 Case No .: 93114577 Amended on May 13, 1994 [Embodiment] Please refer to FIG. 6 to FIG. 9. FIG. 6 to FIG. 9 are schematic diagrams of a method for fabricating a capacitor 118 on a wafer 100 in the first embodiment of the present invention. As shown in FIG. 6, the method for fabricating a capacitor on a wafer 100 according to the present invention is to first provide the wafer 100, and the metal interconnects existing on the wafer 100 are fabricated using copper process technology. Due to the structure on the wafer 100, It varies according to the type of the chip, so it is not specifically described here. At least one copper wire 102 in the uppermost layer is shown in FIGS. 6 to 9, and the copper wire 102 is made in a first Within the dielectric layer 104. In fact, the copper conductive line 102 and the first dielectric layer 104 are simultaneously manufactured through a chemical mechanical polishing process. Next, a barrier layer 106, a second dielectric layer 108, and a conductive layer 112 are sequentially formed on the surface of the wafer 100, and the barrier layer 106 is in direct contact with the copper wire 102. The barrier layer 106 is a nitride group layer, a Ta layer, or a titanium nitride layer, and is formed through a sputtering process. The second dielectric layer 108 includes a silicon oxide layer, A silicon nitride layer is a high-k material layer, and the conductive layer 112 is a nitride button layer or a titanium nitride layer, and is formed by another sputtering process. After coating a photoresist layer (not shown) on the surface of the conductive layer 112, a photomask (not shown) and a lithography process are used to define a patterned photoresist layer for use as a capacitor. Pattern 116. As shown in FIG. 7, an etching process is subsequently performed to remove part of the barrier layer 106, the second dielectric layer 108, and the conductive layer 112, so that the copper wire 102, the patterned barrier layer 106, and the second dielectric layer are removed. 108 and the conductive layer 112 constitute a capacitor 118. The patterned barrier layer 106 and the copper wire 102 form an electrode plate under the capacitor 118. The patterned second dielectric layer 108 is a capacitor dielectric layer of the capacitor 118, and the patterned conductive layer 112 is above the capacitor 118. Plate, and the capacitor 118 is a metal-insulator-metal capacitor. It is worth noting that the patterned barrier layer 106, the second dielectric layer 108, and the conductive layer 1237902 Case No .: 93114577 May 3rd, 1994 Rev. 112 exposed part of the copper wire 102 to facilitate subsequent contact During the manufacturing process, the copper wire 102 can be smoothly connected to the terminal (not shown). At the same time, the barrier layer 106 formed on the copper wire 102 in the present invention is not only used to prevent the diffusion of copper atoms in the copper wire 102, but also used as a part of the lower electrode plate. It is worth mentioning that, in this embodiment, the patterned barrier layer 106 almost completely covers the copper wire 100, which can make the copper wire 102 and the barrier layer 106 have a good contact, and make the capacitance The electrode plate has a larger area, which is a preferred embodiment. As shown in FIG. 8, after removing the capacitor pattern n6, a deposition process is subsequently performed to sequentially form an isolation layer 122 and a third dielectric layer 124 on the surface of the wafer 100, and the isolation layer 122 and the third dielectric layer. The layer 124 covers the capacitor 118 and the copper wire 102. The isolation layer 122 is usually a silicon nitride layer to prevent the copper atoms in the copper wire 102 from diffusing upward. As shown in FIG. 9, a contact process is then performed to form a first contact plug 26 and a second contact plug I28 in the third dielectric layer 124 and the isolation layer 122 to use the first contact plug, respectively. The plug 126 connects the conductive layer 112 of the capacitor 118 to an aluminum pad 132, and uses the second contact plug 128 to connect the copper wire 102 to another aluminum pad 134. In fact, the aluminum pads 132 and 134 are used as terminals in order to transfer the voltages applied to them to the upper and lower plates of the capacitor 118 during the normal operation. At the same time, since the copper wire 102 is a part of the lower plate of the capacitor 118, it can also be directly electrically connected to the corresponding voltage by its own wiring to omit the second contact plug 128 and the aluminum pad 134. Making. In addition, the contact spear king in this embodiment can be regarded as a single damascene process. Since its implementation is a conventional technique, it will not be described again here. In the first embodiment of the present invention, only one photomask is used to define the capacitance pattern. In other words, only one yellow light and etching process is required, which significantly shortens the entire manufacturing process. In the second embodiment of the present invention, the original two case numbers are 1237902. The case number is 93114577, which was amended on May 13, 1994.

Sub-yellow light and etching processes to produce capacitors with high capacitance values. Please refer to FIGS. 10 to 15. FIGS. 10 to 15 are schematic diagrams of a method for fabricating a capacitor 234 on a chip 200 in the second embodiment of the present invention. As shown in FIG. 10, the method for making a capacitor on a wafer according to the present invention is to first provide the wafer 200, and the metal interconnects existing on the wafer 200 are made using copper process technology. Because of the structure on the wafer 200, The types of the chips are different, so no special explanation is given here. In FIG. 10 to FIG. 15, only the uppermost layer of at least one copper wire 202 is shown, and the copper wire 202 is made in a first Within the dielectric layer 204. In fact, the copper wire 202 and the first dielectric layer 204 are simultaneously manufactured through a chemical mechanical polishing process. Then, a barrier layer 206, a second dielectric layer 208, a first conductive layer 212, a third dielectric layer 214, and a second conductive layer 216 are sequentially formed on the surface of the wafer 200, and the barrier layer is formed. 206 is in direct contact with the copper wire 202.

The barrier layer 206 is a tantalum nitride layer, a tantalum layer, or a titanium nitride layer and is formed through a sputtering process. The second dielectric layer 208 and the third dielectric layer 214 include an oxide. Shi Xi layer, a nitride nitride layer or a high dielectric constant material layer, and the first conductive layer 212 and the second conductive layer 216 are a tantalum nitride layer or a titanium nitride layer and pass through another Formed by a sputtering process. After coating a photoresist layer (not shown) on the surface of the second conductive layer 216, a first photomask (not shown) and a first lithography process are used to define a patterned photoresist layer. Used as a first pattern 222. As shown in FIG. 11, a first etching process is then performed, using the first pattern 222 as a mask, and the second conductive layer 216 and the third dielectric layer 214 are etched down to the surface of the first conductive layer 212. As shown in FIG. 12, after removing the first pattern 222, a photoresist layer (not shown) is coated on the surface of the wafer 200, and then a second photomask (not shown) and a second lithography are used. In the manufacturing process, a patterned photoresist layer is defined and used as a second pattern 226. As shown in FIG. 13, a second etching process is then performed, using the second pattern 226 as a mask, and the first conductive layer 212 and the second 12 1237902 are etched downward. Case No .: 93114577 May 13, 1994 Revised dielectric The layer 208 and the barrier layer 206 reach the surfaces of the copper wires 202 and the first dielectric layer 204. The patterned first conductive layer 212, the third dielectric layer 214, and the second conductive layer 216 constitute a first capacitor 228, and the patterned first conductive layer 212, the second dielectric layer 208, and the barrier layer 206 constitute A second capacitor 232, a first capacitor 228, and a second capacitor 232 are connected in a parallel lei structure, and an equivalent capacitor 234 is generated.

It is worth noting that, by pre-designing the first photomask (not shown) and the second photomask (not shown), after the secondary etching process is completed, the patterned second conductive layer 216 and the patterned first conductive layer 216 are patterned. The three dielectric layers 214 expose a portion of the patterned first conductive layer 212, and the patterned second conductive layer 216, the patterned third dielectric layer 214, the patterned first conductive layer 212, and the patterned The second dielectric layer 208 and the patterned barrier layer 206 expose a part of the copper wire 202, so that the copper wire 202 and the first conductive layer 212 can be connected to the terminal (not shown) during subsequent contact processes. . In addition, the barrier layer 206 formed on the copper wire 202 in the present invention is not only used to prevent the diffusion of copper atoms in the copper wire 202, but also used as a part of the lower electrode plate of the second capacitor 232. It is worth mentioning that in this embodiment, the patterned barrier layer 206 almost completely covers the copper wire 202, which can make the copper wire 202 and the patterned barrier layer 206 have good contact, and make the capacitor's electrode The large plate area is a preferred embodiment. As shown in FIG. 14, after removing the second pattern 226, a deposition process is subsequently performed to sequentially form an isolation layer 236 and a fourth dielectric layer 238 on the surface of the wafer 200, and the isolation layer 236 and the fourth The dielectric layer 238 covers the first capacitor 228, the second capacitor 232, and the copper wire 202. The isolation layer 236 is usually a silicon nitride layer to prevent the copper atoms in the copper wire 202 from diffusing upward. As shown in FIG. 15, a contact process is further performed to form a first contact plug 242 and a second contact plug 244 in the fourth dielectric layer 238 and the isolation layer 236 to use the first contact plug, respectively. The plug 242 connects the first conductive layer 212 of the first capacitor 228 to an aluminum pad 246, and corrects and uses the second contact plug 244 to connect the first capacitor 228 to the first capacitor 228 with the case number 13 1237902. The two conductive layers 216 and the copper wire 202 are connected to another aluminum pad 248. In fact, the aluminum pads 246 and 248 are used as terminals so as to transmit the voltages applied to the first capacitor 228 and the second capacitor 232 above and below the plate during the normal operation. In addition, the contact process in this embodiment can be regarded as a single damascene process. Please refer to FIG. 16, which is a schematic diagram of an equivalent circuit of the capacitor 234 of FIG. As shown in Figures 13, 15, and 16, the capacitor 234 of Figure 13 is the equivalent capacitor of the first capacitor 228 and the second capacitor 232 in parallel in Figure 13. The patterned first conductive layer 212 is an upper plate of the first capacitor 228 and the second capacitor 232, and the patterned third dielectric layer 214 is a capacitor dielectric layer of the first capacitor 228, and the patterned second The dielectric layer 208 is a capacitor dielectric layer of the second capacitor 232, the patterned second conductive layer 216 is a plate under the first capacitor 228, and the patterned barrier layer 206 and the copper wire 202 constitute a second capacitor 232, and the first capacitor 228 and the second capacitor 232 are metal-insulator-metal capacitors. The upper electrode plate (first conductive layer 212) of the first capacitor 228 and the second capacitor 232 is electrically connected to the aluminum pad 246 through the first contact plug 242, and the lower electrode plate (the second conductive layer) of the first capacitor 228 216) is electrically connected to the second electrode plate (consisting of the patterned barrier layer 206 and the copper wire 202) through the second contact plug 244, so the capacitance value (C) of the capacitor 234 is equal to the The capacitance value of a capacitor 228 (the sum of the capacitance value (C2) of CO and the second capacitor 232). When the first capacitor 228 and the second capacitor 232 both use the same material in this embodiment, the capacitance of the capacitor 234 The value can be up to twice the capacitance of a single capacitor, but in fact, by adjusting the materials used for the first capacitor 228 and the second capacitor 232, the capacitance of the capacitor 234 can be further increased. In addition, as described above Due to the strong penetration of copper atoms, the copper process is a highly polluting process, so conventional capacitors are usually made on top copper wires. However, since the present invention uses copper wires and The barrier layer is used as the capacitor plate, and Immediately after making a complete cut isolation layer to cover the capacitance 14123790294 amended on May 13

And copper wires to prevent the copper atoms in the copper wires from diffusing outwards. Therefore, this capacitor can also be made between the copper interconnects in each layer. Please refer to FIG. 17 and FIG. 8. FIG. 17 is a schematic diagram of a method for fabricating a capacitor on a chip 300 in the third embodiment of the present invention. FIG. 18 is a schematic diagram of a method for making a capacitor 424 on a chip 4 ′ in the fourth embodiment of the present invention. As shown in FIG. 17, a crystal 300 is first provided. Crystal # 3GG includes at least one copper wire 3G2. The copper wire is: within the -dielectric layer 304 'and the copper wire is not the uppermost layer. A capacitor 314 composed of a barrier layer 306, a second dielectric layer 308, and a conductive layer 312 is formed on the surface of the wafer 300, and the barrier layer 306 is in direct contact with the copper 9 wire 3 . After the capacitor 314 is manufactured, a spacer _ 315 will be manufactured first, and then the upper-layer copper interconnects will be manufactured. The steps are the same as the conventional techniques. First, a silicon oxide layer 316 is deposited, and then a chemical mechanical polishing process is used to smooth it. Then, a silicon nitride layer or a silicon oxynitride layer, which is used as the stop layer 318, is sequentially deposited. 322, and a silicon nitride or silicon oxide layer used as another stop layer 324. Subsequently, the upper trench 326 and the lower contact hole 328 are produced by two stages of the etching process, and the upper trench 326 and the lower contact hole 8 are filled with copper. Finally, another chemical mechanical polishing process is performed to remove the trench 326 and Contact hole = Steel other than 8 to complete the production of the dual mosaic structure 332. In this embodiment, the conductive layer 312 of the valley 314 is connected to a copper wire 334, and the copper wire 302 is connected to another copper wire 336. As shown in FIG. 18, a wafer 400 is first provided. The wafer 400 includes at least one steel wire 402. The copper wire 402 is fabricated in a first dielectric layer 404. The copper wire 402 is not the uppermost layer. Copper wires. A first capacitor 418 composed of a first conductive layer 412, a third dielectric layer 414, and a second conductive layer 416 is formed on the surface of the wafer 400, and a first conductive layer 412, a second capacitor A second capacitor 422 is formed by the dielectric layer 408 and a barrier layer 406, and the barrier layer 406 is in direct contact with the copper wire 402. The first capacitor 418 and the second capacitor 422 are connected in parallel, and an equivalent capacitor 424 is generated. After the completion of the production of capacitor 424, 15 will be the first case number 93114577 as May 13, 1994 to modify the isolation layer 325, and then to control you μ ^ Zhuang Yi to make a layer of copper interconnects, the steps A S of 4t i is then re-used by segmented ecliptic sandpiper. First deposit-silicon oxide, and then use a chemical deposition to know the stop layer 434 fossil layer 'another oxide layer 432, and one to be used as an alternative roll & silicon nitride layer or oxynitride Silicon layer. Suihua sand layer or ground, and then sequentially deposited as the stop layer 428, ---- // Day Hou 1 们 π force, the right surname ditch booth 4 buckle, the upper trench building and The lower layer contacts and holes 438 are filled with copper to fill the upper layer 9 and the lower layer contact holes 438. Finally, another chemical mechanical polishing process is performed to remove copper other than the trenches 436 and the contact holes 438 to complete the fabrication of the dual damascene structure 442. In this embodiment, the first conductive layer 412 of the first capacitor 418 is connected to a copper wire 444, the second conductive layer 416 of the first capacitor 418 and the copper wire 402 are connected to another copper wire material 6.

In addition, the size, shape, and position of the electrode plates of the capacitor in the present invention can be adjusted according to actual conditions, as long as the premise of exposing a part of the copper conductors to successfully connect the copper conductors to the terminals is certain. Feasibility is included in the scope of the present invention. However, in actual implementation, issues such as the contact resistance of the barrier layer and the steel wire, the misalignment in the manufacturing process, and the performance of the overall capacitor must be considered. At the same time, the method of the present invention is applicable to any copper structure. Not only the copper wire and the barrier layer can form the lower electrode plate of the capacitor, but the copper transfer pad can also form the lower electrode plate of the capacitor with the barrier layer. Because the method for making a capacitor of the present invention uses a copper wire and a barrier layer as the lower electrode plate of the capacitor, 'On the condition that the exposed copper wire is satisfied to connect the copper wire to the terminal smoothly, only the A capacitor mask can be used to define the capacitor pattern, that is, the capacitor can be manufactured by only one yellow light and etching process. Shortened the entire production process. At the same time, in the second embodiment of the present invention, the original two yellow light and etching processes are retained to produce a capacitor having a high capacitance value. When the method of the present invention is applied to an actual production line, a capacitor with low cost, high yield, and excellent characteristics can be manufactured. 16 1237902 Case No. 93114577 May 13, 1994 amendment

Compared with the conventional method for making a capacitor, the method for making a capacitor of the present invention uses copper wires and a barrier layer as the lower electrode of the capacitor. The copper wires can be smoothly provided that the exposed copper wires are satisfied. It is connected to the terminal, so only one yellow light and etching process is needed to complete the capacitor production. In this way, not only the manufacturing process is shortened, but also copper wires can be used as a part of the lower electrode plate to produce capacitors with better characteristics. At the same time, costs are reduced and yields are improved. In addition, while retaining the original two yellow light and etching processes, a capacitor with a high capacitance value can be made, and the design of the capacitor is more flexible. When the method of the present invention is used to make a capacitor on a specific wafer, the performance of the wafer can be improved. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention. [Simple illustration of the drawing] Simple description of the drawing

1 to 5 are schematic diagrams of a conventional method for fabricating a capacitor on a chip. 6 to 9 are schematic diagrams of a method for fabricating a capacitor on a wafer in the first embodiment of the present invention. Figures 10 to 15 are schematic diagrams of a method for fabricating a capacitor on a wafer in a second embodiment of the present invention. FIG. 16 is a schematic diagram of an equivalent circuit of the capacitor of FIG. 13. FIG. 17 is a schematic diagram of a method for fabricating a capacitor on a wafer in a third embodiment of the present invention. FIG. 18 is a schematic diagram of a method for fabricating a capacitor on a wafer in a fourth embodiment of the present invention. 17 1237902 Case number: 93114577 May 13, 1994 Amendment of symbols of the pattern Description 10, 100, 200, 300, 400 Wafer copper wires 12, 102, 202, 302, 334, 336, 402, 444, 446 14, 104 , 204, 304, 404 First dielectric layer 16, 122, 236, 315, 425 Isolation layer 18, 212, 412 First conductive layer 28, 108, 208, 308, 408 36, 118, 234, 314, 424 24 Lower plate pattern 26 Lower plate 32, 216, 416 34 38 Upper plate 42 Capacitance dielectric layers 44, 124, 214, 414 46, 126, 242 48, 128, 244 52 First terminal 54 Second terminal 106, 206, 306, 406 112, 312 116 Capacitance patterns 132, 134, 246, 248 222 First pattern 226 Second pattern 228, 418 232, 422 238 Fourth dielectric layer Second dielectric layer Upper electrode of the second conductive layer Pattern capacitor third dielectric layer first contact plug second contact plug barrier layer conductive layer aluminum pad first capacitor second capacitor

18 1237902 316, 322, 426, 432 318, 324, 428, 436 326, 436 328, 438 332, 442 Case No .: 93114577 Silicon oxide layer Stop layer Trench Contact hole Double mosaic structure May 13, 1994 Revised

19

Claims (1)

1237902 Case No .: 93114577 May 13, 1994 Amendment and patent application scope: 1. A method for making at least one capacitor on a semiconductor substrate, the surface of the semiconductor substrate includes at least a first dielectric layer And at least one conductive object is disposed in the first dielectric layer, the method includes the following steps: A barrier layer, a second dielectric layer, and a conductive layer are sequentially formed on the surface of the semiconductor substrate, and the barrier layer is in direct contact with the conductive object; an etching process is performed to remove a portion The barrier layer, the second dielectric layer, and the conductive layer, and the patterned barrier layer, the second dielectric layer, and the conductive layer constitute the capacitor; and a contact process is performed to make the capacitor The conductive layer is connected to a first terminal by a first contact plug. 2. The method according to item 1 of the patent application, wherein the capacitor is a metal-insulator-metal capacitor (MIMC). 3. The method of claim 1 in which the conductive material is formed using a copper process, and the barrier layer is used to prevent diffusion of copper atoms in the conductive material. 4. The method of claim 3, wherein the barrier layer comprises a tantalum layer (Ta layer), a tantalum nitride layer (TaN layer) or a titanium nitride layer (TiN layer) 5. The method of applying for the third item of the patent scope, wherein the conductive object is a part of a lower plate of the capacitor. 6. The method of claim 5 in which the conductive material covered by the patterned barrier layer is part of the lower electrode plate. 7. The method according to item 1 of the patent application scope, wherein the second dielectric layer comprises a 20 1237902 case number: 93114577 May 13, 1994, a modified stone oxide layer, a nitride stone layer or a high dielectric layer Electrical constant (high k) material layer. 8. The method of claim 1, wherein the conductive layer includes a titanium nitride layer (TiN layer) or a nitride button layer (TaN layer). 9. The method of claim 1, wherein after the etching process is performed, it further comprises a deposition process to sequentially form an isolation layer and a third dielectric layer on the surface of the semiconductor substrate. 10. The method of claim 1 in which the conductive object is electrically connected to a second terminal. 11. The method of claim 10, wherein a second contact plug is formed at the same time as the contact process is performed, so as to use the second contact plug to connect the conductive object to the second terminal. 12. The method of claim 1, wherein the first terminal system includes an aluminum bonding pad or a steel wire. 13. The method according to item 12 of the patent application scope, wherein the contact process is a single damascene process or a dual damascene process ° 14. It is fabricated on a semiconductor substrate A method for at least one capacitor. The surface of the semiconductor substrate includes at least a first dielectric layer and at least one conductive object wave is placed in the first dielectric layer. The method includes the following steps: A barrier layer, a first electrical layer, a first conductive layer, a third dielectric layer, and a second conductive layer are sequentially formed on the surface of the substrate, and the barrier layer is connected to the conductive object. Direct contact; 21 1237902 Case No .: 93114577 May 13, 1994 Corrected a first etching process to remove a portion of the second conductive layer and the third dielectric layer; A second etching process was performed to remove a portion The first conductive layer, the second dielectric layer, and the barrier layer, so that the patterned first conductive layer, the third dielectric layer, and the second conductive layer constitute a first capacitor, and the pattern is Kazuyuki The first conductive layer, the second dielectric layer and the barrier layer constitute a second capacitor; and a contact process is performed to connect the first conductive layer of the first capacitor to a first capacitor via a first contact plug respectively. The first terminal, the second conductive layer and the conductive object of the first capacitor are connected to a second terminal through a second contact plug. 15. The method according to item 14 of the patent application, wherein the first capacitor and the second capacitor are a metal-insulator-metal capacitor (MIMC). 16. The method of claim 14 in which the conductive material is formed using a copper process, and the barrier layer is used to prevent diffusion of copper atoms in the conductive material. 17. The method of claim 16 in the patent application range, wherein the barrier layer comprises a tantalum layer (Ta layer), a tantalum nitride layer (TaN layer) or a titanium nitride layer (TiN layer) 〇 18. For example, the method of claim 16 in which the conductive object is a part of a lower plate of the second capacitor. 19. The method of claim 18, wherein the conductive object covered by the patterned barrier layer is a part of the lower electrode plate. 20. The method according to item 14 of the patent application, wherein the second dielectric layer and the third dielectric layer include a stone oxide layer, a nitride stone layer, or a high dielectric constant 22 1237902 : 93114577 May 13, 1994 (high k) material layer. 21. The method according to item 14 of the application, wherein the first conductive layer and the second conductive layer include a titanium nitride layer (TiN layer) or a nitride button layer (TaN layer) ° 22. The method of claim 14 includes a pattern of the second conductive layer and the third dielectric layer exposing a portion of the patterned first conductive layer. 23. The method according to item 14 of the patent application, wherein after performing the etching process, further comprising a deposition process to sequentially form an isolation layer and a fourth dielectric layer on the surface of the semiconductor substrate. 24. The method of claim 14 in which the first terminal and the second terminal comprise an A1 bonding pad or a copper wire. 25. The method of claim 24, wherein the contact process is a single damascene process or a dual damascene process ° 23 1237902 Amended on May 13, 1994 No. 93114577 24 · ν · Γ, -I. ~ .. W.. ·-· · --- ·· *--··· 1237902 '^ r ϋ