TWI231649B - Automatic level correction apparatus with lower current loss for digital input circuit - Google Patents

Abstract

An automatic level correction apparatus with lower current loss for digital input circuit comprises a charge/discharge circuit, a chip circuit, and a latch circuit. One end of the charge/discharge circuit is connected with a voltage source, and the other end is grounded. The source pole of the chip circuit is connected with the voltage source, the drain pole of it is connected with a point between the latch circuit and an output, refereed as point B, and the gate pole of it is connected with the charge/discharge circuit. When the state of an external circuit is being changed, the point B can be adapted, and therefore can reduce power loss. The automatic level correction apparatus with lower current loss is applicable to various circuits and systems.

Description

1231649 V. Description of the invention (1) [Technical field to which the invention belongs] The automatic quasi-digit input of low leakage current of the input electrode "when electricity L" is turned on, and the input terminal is floating, this circuit installation will produce a Fixed voltage This-the circuit device will be turned on when the power is turned on, and when the external circuit changes state: after: ': 2 automatically loses power consumption; = = the ground follows the change, and there is no additional, can be Suitable for all kinds of circuits and systems.胄 Quasi-digit input circuit device [previous technology] It is expected to be used as a circuit for various types of information electronic products, and it will be replaced by the principle of analogy. Principles and technology will be replaced by & the most bright sea = heavy = determined speed. It also takes the example of Yuexian, that is, using iS * & ancient air traffic control to obtain a significantly reduced circuit body borrowed ... "instead of the microprocessor of the true = with the electric body, becoming the enabler Third: That is, logic = voltage input *, 〇w) level. Generally cool n 8) level or low (floating input of circuit 1 fills in f δ 'when the standby power supply is supplied, it provides digital 1…)-a clear upper line: 1: 1 η ρ test ..., number: ΪΪ 3 Bits, as the input of the aging of the circuit in the initial state: ί :: Ignore the slight voltage difference, and have a greater tolerance for parts that you can move. 1231649 V. Description of the invention (2) As shown in Figure 4 t, a resistor is directly connected to the voltage source v d d, 7. TtH d on: When supplying, you can provide a digital level for the output terminal r μ η via the resistor R 0, or you can change the power supply to ground (two provide = level. After that, the external circuit can be customized according to demand The edge is used for inputting the (I Ν) digital level to input to the internal circuit. And, when the power is supplied, it provides the high input terminal for the output # (〇υτ) ('f: the circuit provides the low digital level for input During the round, an additional current consumption n point will be generated through the resistor R 0, which will cause a considerable obstacle to the low power consumption circuit. Device two η: So heavy • 'Mainly because it not only causes the power supply to cause the product. Temperature near the body circuit (1 c) ^ One day Φ C element overheated and caused the electronic circuit to fail. Because t A-resistance R 〇 generates additional current consumption, it will have a great impact on the overall electrical + circuit Then I ruthenium wild 骽 1: sub-test with ί ::: 'ΐ the inventor has accumulated many years of practical experience in the semiconductor industry through the design of voltage-like circuits for a long time, and finally designed to respond to changes that can be appropriately followed' Will cause additional power consumption Bit input circuit: Automatic level of circuit and system with very low leakage current [Contents of the invention] Automatic level and gate circuit with extremely low leakage current: Install the charge and discharge circuit, t crystal circuit, the output terminal and input End circuit: Grab :: ㊁J state, 'can make the voltage state at point p and point B on the circuit easily follow the change

Page 7 1231649 V. Description of the invention (3) changes without additional power consumption. In order to achieve the above-mentioned object, the present invention uses a charge-discharge circuit, a body circuit and a latch circuit, wherein one end of the charge-discharge circuit is connected to a voltage source, and the other end is grounded, the source of the transistor circuit The pole is connected to the above-mentioned electric f source. 'The drain is connected to the point between the latch circuit and the circuit output.' The point is point B. The gate of the transistor circuit is connected to the charge and discharge. With this, when the external circuit changes state, the state at point B can easily follow the change, reducing power consumption. In order to facilitate a deeper understanding of the present invention, the embodiments are described in detail below.

[Embodiment] Referring to Figures 1 and 2, the function block circle of the present invention includes: charge: $ circuit 10, transistor circuit 20, latch circuit 30, and buffer discharge circuit 1 including resistor 1 1 And capacitor 1 2, the transistor system is a metal oxide semiconductor transistor PMOS, which includes a source, 2 poles 22 and a drain 2 3, and the latch circuit 3 〇 includes inverters J 1, 3 2 〇

Voltage level: T ί Upper: The voltage between capacitor 1 2 and gate 2 2 is A 12, and the electric terminal 1 9 is connected to the voltage source vdd. One terminal is connected to the electric transistor transistor resistance 1 and the terminal is grounded. The metal oxide electrode The source of the remote 3 · air-recognition S 2 1 is connected to the voltage source vdd, and the circuit on the output and input side of the wheel only goes to 屮 her & At 8 o'clock, the output of the gate circuit 3 0, the gate circuit composed of the second inverters 3 1 and 3 2 of its work # 4 includes the following steps:

1231649 V. Description of the invention (4) (1) Voltage source VH ^ When the resistor and capacitor are supplied, the voltage of resistor 1 1 and capacitor 1 2 is slow to produce two constant (Rc time constant) circuit. The voltage of 0 volts is charged to the voltage value of the voltage source vdd. (2) When the point A is 2 MOS 2 η 〇 0 special, the P bit of the metal oxide semiconductor transistor will be in an on (0N) state with the battery. So that point B will be the same as point B, and will pass through the latch circuit 3 0 and the punch (B uf will be set at a high (H 1 GH) level), and will be delayed (3) when A · point is charged. | J = Γ) 4 〇 Promote the internal circuit; at the same time, the voltage of the voltage source Vd d is equal to the voltage value of the voltage source (屈 ΐ). The conductor transistor PM 0 s 2 0 will therefore turn off the conductor transistor PM. ^ ΐ? V dd is no longer transmitted to point b via the metal oxide half «, ready M 0 S 2 0; Dimensional dimension: ΐ Γ? When the input port is floating, when the input port is floating, ^ ^ Ν points do not When connected to any circuit, this circuit can provide a preset initial state via 2 ί: Ϊ Ϊ without having to go through other :: circuits. And when an external circuit is connected and Start to supply the signal =, the signal provided by the external circuit can easily pass the signal to the internal circuit through the latch circuit 30 composed of the first and second inverters 3 1 and 3 2, and the metal oxide semiconductor is at this time The transistor PM 0 S 2 〇 is already turned off (0 FF). The power consumption network is suitable for use in a state such as a power saving mode, so the circuit of the present invention does not generate the extra μ power consumed by the conventional circuit, and the additional circuit required is also Quite a few, this • Α 人 田 · Zτ L You _ (Power sav 1231649

V. Description of the invention (5) The control input port of ng m0de) can provide the required preset initial state without connecting to any 4 circuits, which can effectively speed up the time and reduce the time required for production measurement. Additional measurement circuitry required. The circuit of one embodiment of the present invention is a circuit device with a movable pull-down · volt / 5 volt tolerant input unit circuit (t 〇 丨 e 『… 11 ^ C e 1 1 with active pu 11-d〇Wn), which can be used for ARf〇〇5 input cell, B. ^ It is a mechanism that can be set to "W" automatically in the initial state. Refer to Figure 3. P w r s t will be connected to a resistor similar to Figure 1-taste money. -The time constant circuit 1 is also turned on (ON), so the state of M * Ϊ ΐ is turned on (N). Therefore, the potential at point I Ν is pulled to ground (G Ν Γ > > the potential at point 1 n ^ is

1, 2, 4, r 'D) are the same' and the latch circuit composed of inverters INV 4, 5 and a level shift circuit is shifted) The potential is stabilized at a ground value at + (1 atch) structure. The IN point is set to a low (1 0w) state. It is known that U 1 1 and 0 2 will also be fixed to INV1 as Schmitt gger), which can be reduced by τ (Schmitt tri-bit adjustment (1 ev ei N Click the wrong action caused by noise. The electric 2 volt and .3 volt circuit with two hift) can be used to turn off the M 4 for this circuit. If you need to change the tender level, the R c time constant circuit will be directly Input the signal into the wheel, the state of the outgoing terminals ut 1 and 〇11 t 2, the J terminal (1 N) point can be. This has a movable type

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V 1231649 V. Description of the invention (6) Pull down the function of 3 volts / 5 volts surname rant ί η + Chou Tege Ni Ni input unit circuit (n 1 1 nput cpi〗 11 with act-down,. B. ^ T) , Also has a protection circuit for electrostatic discharge ο ran ee Puli. Therefore, according to the present invention, JL has the following advantages to make Wu Yan the following: τΪ ίΓ Low leakage! The automatic quasi-digit input circuit of the current * and the circuit composed of the electric unit and the transistor are set to the correct initial state, and the circuit state can be easily changed when the external rate is lost, and the section 2 and ^ = have extremely low The automatic quasi-bit-of-three-phase power transmission system for leakage current can directly apply the existing resistors, capacitors, and transistors to obtain economical applications suitable for various types of circuits and systems in the industry: extreme value. In summary, the present invention can achieve the intended purpose, and provide an automatic quasi-digit input circuit device with extremely low leakage current. By using the functions of a charge and discharge circuit, a transistor circuit and a latch circuit, When the external circuit changes state, the state of point b located on the circuit of the output and input can be changed easily without additional power consumption. 'Applicable to various circuits and systems, very industrial use The value of the patent application according to law.

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Claims (1)

1231649 VI. Application of Handle _-1. An automatic quasi-digit input circuit device with extremely low leakage current, comprising a charge and discharge circuit, a transistor circuit and a latch circuit, wherein one end of the charge and discharge circuit is connected There is a voltage source whose other end is grounded. The source of the transistor circuit is connected to the voltage source described above, the closed electrode is connected to the charge and discharge circuit, and the drain of the transistor circuit is connected to the latch circuit. And a point between the output terminal of the circuit, and this point is set to point B, so that the state of point B follows the external circuit state change: change to reduce the power consumer. 2. The automatic quasi-digit input circuit device with extremely low leakage current as described in item i of the scope of patent application, wherein the charge and discharge circuit is a resistor-capacitor circuit (RC circuit). 3. The automatic quasi-digit input circuit device with extremely low leakage current as described in item (1) of the scope of the patent application, wherein the transistor circuit is pMOS (metal oxide semiconductor), and its gate is connected to a resistor and Between capacitors. '4. The automatic quasi-digit input circuit device with extremely low leakage current as described in item 丄 of the scope of patent application, wherein the latch circuit is composed of two inverters. 5 The automatic quasi-digit input circuit device with extremely low leakage current as described in item 1 of the scope of patent application, further comprising a buffer between the point B and the output terminal.