1229740 五、發明說明（1) ' ---- 【發明所屬之技術領域】 本發明係有關於一種測試電路板電性特性的裝置以及方 $方=有關於一種測試半導體封裝基板電性特^的裝置以 【先前技術】 ，著在固定大小的半導體晶片（chip)上製造大量電晶體 之能力增加，該晶片上的電路變得更複雜且需要大量的外 部電性接點（external electrical c〇nnecti〇ns)。為了 達成所需外部接點的數目，用於半導體積體電路的基 電路設計也亦趨複雜。 土 為了節省成本避免不必要之浪費，製造業者必須在半 體封裝製程之前對基板的電性加以測試。基板的測試通 1牽涉偵測其是否出現短路（sh〇rt)以及斷路（〇pen)。 短路」係發生於當兩個應當分離的相鄰電路互相電性連 接時。「斷路」係發生於當兩個應當電性連接的端點之 的電路損壞時。習用的短路（short)以及斷路（〇pen)測 之通常要利用與基板上每一基板單元上所有電路連接的#導 電條進行。然而，許多種具有多個基板單元之基板條係由 不同於習知的方法製造，因此其不包含前述的導電條 (bar)。不具有導電條之基板目前只能使用「飛針」 (f lying probing)的方式進行測試。一般而言，「飛針 係將兩個測試的針狀測試器不斷進行物理移動兩兩地測^ ，基板上之所有端點。然而，隨著基板製造技術的進步: 每基板單元的面積可愈做愈小，每一個基板條上可容納1229740 V. Description of the invention (1) '---- [Technical field to which the invention belongs] The present invention relates to a device for testing the electrical characteristics of a circuit board and a method for testing the electrical characteristics of a semiconductor package substrate. The device uses [prior art] to increase the ability to make a large number of transistors on a fixed-size semiconductor chip. The circuit on the chip becomes more complicated and requires a large number of external electrical contacts (external electrical c. nnecti〇ns). In order to achieve the required number of external contacts, the basic circuit design for semiconductor integrated circuits is also complicated. In order to save costs and avoid unnecessary waste, manufacturers must test the electrical properties of the substrate before the half-package process. The test pass 1 of the substrate involves detecting whether a short circuit (short) and an open circuit (ooppen) occur. A "short circuit" occurs when two adjacent circuits that should be separated are electrically connected to each other. "Open circuit" occurs when the circuit between two terminals that should be electrically connected is broken. Conventional short and open circuit tests are usually performed using #conducting strips connected to all circuits on each substrate unit on the substrate. However, many kinds of substrate bars having a plurality of substrate units are manufactured by a method different from a conventional method, and thus do not include the aforementioned conductive bars. Substrates without conductive strips can currently only be tested using the "f lying probing" method. Generally speaking, "Flying probes are physically moving two test needle testers continuously to measure all the end points on the substrate. However, with the advancement of substrate manufacturing technology: the area of each substrate unit can be Get smaller and smaller, can be accommodated on each substrate strip
1229740 、發明說明（2) ^來越多個基板單元，使得所需測試之基板接點越來越 夕因此，利用「飛針」進行基板的短路（sh〇rt)以及斷 路（open)測試變成十分耗時以及沒有效率而無法用於量產 測試。 【發明内容】 本發明之目的係提供一種測試半導體封狀構造之基板之 電，特性的裝置以及方法，用以降低測試一基板上多個基 板，元的時間以及花費，能克服或改善先前技術中的上述 問題。 、為了達成上述及其他之目的，本發明提供一種裝置用以 $試一基板上複數個基板單元之電性特性，該裝置包含一 弟 4欢測器、一弟一檢測器以及一電子測量裝置。每一基 板單兀具有相對的第一以及第二面以及電路圖案，該電路 圖案包έ複數個第一端點形成於該基板單元的第一面以及 複數個苐一端點形成於該基板單元的第二面。 該裝置之第一檢測器包含複數個連接接點 (interconnect contacts)用以接觸該些基板單元之第一 鈿點。该裝置之第二檢測器具有一支撐件以及複數個導電 接墊設=該支撐件上，其中該第二檢測器係可移動靠近該 些基板單兀並且使其上的每一導電接墊與該些基板單元之 一的所有第二端點接觸。該電子測量裝置連接於該第一以 及第二檢測器用以測試電路特性。 本發明另提供一種測試一基板上複數個基板單元之電性 特性之方法。首先，使該第一檢測器之複數個連接接點 00810.ptd 第7頁 1229740 五、發明說明（3) (interconnect contacts)接觸該些基板單元之第一端 點’並且使該第二檢測器上之複數個導電接墊各與一基板 單元上之所有第二端點接觸。然後，使用該電子測量裝置 測試該些基板單元之電路特性。 本發明提供之測試方法可同時以系列的方式測試一機板 上之所有基板單元之電性，因此能降低測試一基板上多個 基板單元的時間以及花費。 【實施方式】 參照第1圖’標號1 〇 〇的元件係為本發明一實施例之待測 基板。該基板1 0 0主要包含四個區域A。第2圖係為其中一 區域A的放大圖，有複數個陣列排列之基板單元2〇〇設於區 域A中。參照第2以及第3圖，每一基板單元2 〇〇具有電路圖 案202分布於該基板單元2〇〇兩相對的第一及第二面3〇2、 304 (參見第3圖）。該電路圖案2〇2包含複數個端點3〇6形 成於該基板單元2〇〇的第—面3〇2以及複數個端點川形成 於該基板單元20 0的第二面3〇4(參見第3圖）。在本實施 例中，該基板100之電路圖案係由以下步驟形成。首先， ，該基板之第一以及第二面3〇2以及3〇4上各形成一層銅 箔。於該銅箔上形成具有電路圖案之光阻層之後，再以電 m將從該光阻層暴露㈣表㈣上金屬薄鍍層 屬薄梦二、At層ΐ是金層）。除去光阻層之後，以該金 屬屬錄層為遮罩(mask)圖案化該銅箱’以形成該導電圖案 〇2。在傳、、先的技術中，需先圖案化銅箔以得 再以電鍍的方式於導電圖案上鍍上錫層、鎳金層或是金 00810.ptd 第8頁 1229740 五、發明說明（4) 層。因此傳統上，母一基板單元皆具有_導電條（p 1 &七丨n g bar)與該基板單元的每一導電線路電性連接。然而，根據 此實施例所製造的基板1 00不包含該導電條，因此需要不 同於習知技術的測試裝置和方法，始能迅速有效地測試該 基板1 0 0上的所有基板單元2 〇 〇。 參照第3圖，本發明提供一種測試裝置，用以測試該基 板100上的ό亥些基板單元2〇〇上電路圖案2〇2之電性特性Q 該測試裝置包含兩個檢測器3 1 〇以及3 1 2可分別置於該待測 基板100的上下兩邊，以及一電子測量裝置314連接於該兩 個檢測器3 1 0以及3 1 2用以測試該些基板單元2 〇 〇之電路特 十生 ° ° 在此實施例中，檢測器31 0具有複數個針狀的連接接點 3 1 5。該檢測器3 1 0之連接接點3 1 5係對應該些基板單元2 〇 〇 之第一面3 0 2上的端點3 0 6而設置，並且用以接觸該些端點 30 6。該檢測器3 1 0可以是一種偵測卡（pr〇be card )。較 佳地，該檢測器3 1 0可同時接觸至少一個基板單元2 〇〇的所 有端點3 0 6。 麥照第3圖，該檢測器3 1 2係包含一支撐件3 1 6以及複數 個導電接墊3 1 8設於該支撐件3 1 6上。該支撐件3 1 6係連接 於一移動裝置（例如氣壓缸）320，藉此可使該檢測器31 2移 動靠近該些基板單元20 0。該支撐件具有一底板322以及一 柱狀部324，這種設計可大幅降低該支撑件316之重量，藉 此減少該移動裝置3 2 0的重量負荷。該支掠件3丨6之柱狀部 324可藉由一黏膠326固接於該移動裝置320。根據本發明1229740, description of the invention (2) ^ With more and more substrate units, the substrate contacts needed to be tested are getting more and more evening. Therefore, the use of "flying pins" for short circuit (short) and open circuit (open) testing of the substrate becomes Very time consuming and inefficient to use for mass production testing. [Summary of the Invention] The object of the present invention is to provide a device and method for testing the electricity and characteristics of a substrate with a semiconductor sealing structure, which can reduce the time and cost of testing multiple substrates on a substrate, and can overcome or improve the prior art. The above problems. In order to achieve the above and other objectives, the present invention provides a device for testing the electrical characteristics of a plurality of substrate units on a substrate. The device includes a brother detector, a detector, and an electronic measuring device. . Each substrate unit has opposite first and second sides and a circuit pattern. The circuit pattern includes a plurality of first endpoints formed on the first side of the substrate unit and a plurality of first endpoints formed on the substrate unit. The second side. The first detector of the device includes a plurality of interconnect contacts for contacting the first points of the substrate units. The second detector of the device has a supporting member and a plurality of conductive pads arranged on the supporting member, wherein the second detector is movable close to the substrate units and each conductive pad thereon is connected with the conductive pad. All of the second end points of one of the substrate units are in contact. The electronic measuring device is connected to the first and second detectors to test circuit characteristics. The invention also provides a method for testing the electrical characteristics of a plurality of substrate units on a substrate. First, make the plurality of connection contacts of the first detector 00810.ptd page 7 1229740 V. Description of the invention (3) (interconnect contacts) contact the first end points of the substrate units and make the second detector Each of the plurality of conductive pads is in contact with all second terminals on a substrate unit. Then, the electronic measurement device is used to test the circuit characteristics of the substrate units. The test method provided by the present invention can simultaneously test the electrical properties of all the substrate units on a board in a series of methods, thereby reducing the time and cost of testing multiple substrate units on a substrate. [Embodiment] Referring to FIG. 1, the component numbered 100 is a substrate to be tested according to an embodiment of the present invention. The substrate 100 mainly includes four regions A. Figure 2 is an enlarged view of one of the areas A, and a plurality of substrate units 200 arranged in an array are arranged in the area A. Referring to FIGS. 2 and 3, each substrate unit 2000 has a circuit pattern 202 distributed on the first and second surfaces 3202 and 304 opposite to the substrate unit 2000 (see FIG. 3). The circuit pattern 200 includes a plurality of end points 306 formed on a first side 300 of the substrate unit 200 and a plurality of end points formed on a second side 304 of the substrate unit 200 ( (See Figure 3). In this embodiment, the circuit pattern of the substrate 100 is formed by the following steps. First, a copper foil is formed on each of the first and second surfaces 302 and 304 of the substrate. After forming a photoresist layer with a circuit pattern on the copper foil, the photoresist layer will be exposed by electricity (the thin metal plating layer on the surface is a thin dream II, and the At layer is a gold layer). After the photoresist layer is removed, the copper box is patterned with the metal recording layer as a mask to form the conductive pattern 02. In the prior art, the first technology was to pattern the copper foil to obtain a tin layer, nickel-gold layer, or gold on the conductive pattern by electroplating. 00810.ptd Page 8 1229740 V. Description of the invention (4 ) Floor. Therefore, traditionally, a mother-substrate unit has a conductive strip (p 1 & n g bar) electrically connected to each conductive line of the substrate unit. However, the substrate 100 manufactured according to this embodiment does not include the conductive strip, and therefore requires a testing device and method different from the conventional technology, so that all the substrate units 200 on the substrate 100 can be quickly and efficiently tested. . Referring to FIG. 3, the present invention provides a test device for testing the electrical characteristics Q of the circuit pattern 200 on the substrate unit 200 on the substrate 100. The test device includes two detectors 3 1 〇 And 3 1 2 can be respectively placed on the upper and lower sides of the substrate to be tested 100, and an electronic measuring device 314 is connected to the two detectors 3 1 0 and 3 1 2 to test the circuit characteristics of the substrate units 2000. Ten degrees ° In this embodiment, the detector 3 10 has a plurality of needle-shaped connection contacts 3 1 5. The connection contacts 3 1 5 of the detector 3 1 0 are provided corresponding to the end points 3 06 on the first surface 3 2 of the substrate unit 2 00, and are used to contact the end points 3 06. The detector 3 1 0 may be a detection card (prObe card). Preferably, the detector 3 10 can simultaneously contact all the end points 3 06 of at least one substrate unit 2000. According to Fig. 3, the detector 3 1 2 includes a supporting member 3 1 6 and a plurality of conductive pads 3 1 8 provided on the supporting member 3 1 6. The supporting member 3 1 6 is connected to a moving device (such as a pneumatic cylinder) 320, so that the detector 31 2 can be moved close to the substrate units 200. The support member has a bottom plate 322 and a columnar portion 324. This design can greatly reduce the weight of the support member 316, thereby reducing the weight load of the mobile device 320. The columnar portion 324 of the swivel member 316 can be fixed to the moving device 320 by an adhesive 326. According to the invention
00810.ptd 第 9 頁 122974000810.ptd Page 9 1229740
另一實施例，如第4圖所示，該支撐件316可另包含一突出 部402，並且藉由複數個螺絲4〇4等固定件將該支撐件316 之突出部402固定於該移動裝置320。 如第5圖所示，該底板320上設有複數個呈陣列排列之導 電接墊3 1 8分別對應於該基板1 〇 〇之一區域a (參見第J圖） 中的基板單元200 (參見第2圖）。參照第3圖，每一導電 接塾318可與一基板單元200的第二面3〇4上所有端點308接 觸，使得該基板單元200上所有端點308可電性連接於該導 電接墊3 1 8。在此貫施例中，形成該些導電接塾3 1 8之步驟 係包含：先利用橡膠沖切模具製造複數個尺寸精確的導電 膠塊’再將該些導電膠塊黏貼於該支撐件31 6之底板3 2 2 上。為了使該導電接墊318能確實與其對應之基板單元2〇〇 上所有待測的端點3 0 8接觸，可在該導電接塾3 1 8上對應基 板單元200之晶片设置區204(見於第2圖）的地方形成孔洞 5 02，藉此有助於使該導電接墊3 18與基板單元2〇〇上環繞 晶片設置區2 0 4的所有端點3 0 8密合。 此外，在黏貼該導電膠塊時，需要將該些導電膠塊黏在 精確的位置’藉此讓該些導電接塾318與該些基板單元2〇〇 有對應的相對位置。因此如第6〜8圖所示，可於該底板3 2 2 上設置複數個突起點6 0 2、突起塊狀物7 〇 2或是凹槽8 〇 2藉 此標不該導電膝塊應黏附的位置。 該電子測量裝置3 1 4可根據電腦程式，控制該檢測器3 i 〇 的連接接點3 1 5輪流對不同之端點3 〇 6送出訊號，並且接收 反應訊號藉此測試該基板單元2 0 0之電性特性，並且偵測In another embodiment, as shown in FIG. 4, the supporting member 316 may further include a protruding portion 402, and the protruding portion 402 of the supporting member 316 is fixed to the mobile device by fixing members such as a plurality of screws 40. 320. As shown in FIG. 5, the base plate 320 is provided with a plurality of conductive pads 3 1 8 arranged in an array corresponding to a substrate unit 200 in an area a (see FIG. J) of the substrate 100 (see FIG. J). (Figure 2). Referring to FIG. 3, each conductive connection 318 can be in contact with all the terminals 308 on the second surface 300 of the substrate unit 200, so that all the terminals 308 on the substrate unit 200 can be electrically connected to the conductive pad. 3 1 8. In this embodiment, the steps of forming the conductive contacts 3 1 8 include: firstly manufacturing a plurality of conductive rubber blocks with precise dimensions by using a rubber die-cutting die, and then attaching the conductive rubber blocks to the support member 31. 6 on the bottom plate 3 2 2. In order to make the conductive pad 318 surely contact all the terminals 3 0 8 to be tested on the corresponding substrate unit 2000, the conductive pad 3 1 8 may correspond to the wafer setting area 204 of the substrate unit 200 (see (Figure 2) where holes 502 are formed, thereby helping the conductive pad 318 to be in close contact with all the terminals 308 on the substrate unit 200 surrounding the wafer setting area 208. In addition, when pasting the conductive rubber blocks, the conductive rubber blocks need to be adhered to precise positions', so that the conductive contacts 318 and the substrate units 2000 have corresponding relative positions. Therefore, as shown in Figs. 6 to 8, a plurality of protruding points 6 0 2, protruding blocks 7 〇2 or grooves 8 〇2 can be provided on the bottom plate 3 2 2 to mark whether the conductive knee block should be used. Sticky location. The electronic measuring device 3 1 4 can control the connection points 3 1 5 of the detector 3 1 5 in turn to send signals to different endpoints 3 0 6 according to a computer program, and receive a response signal to test the substrate unit 2 0 Electrical characteristics of 0, and detect
00810.ptd 第10頁 1229740 五、發明說明（6) §亥基板單元200是否出現短路（sh〇rt)以及斷路（〇pen)等現 象。 本發明另提供一種測試一基板上複數個基板單元之電性 特性之方法。首先，使該檢測器31〇之該些連接接點31 5接 觸忒些基板單元2 0 0之端點3 〇 6。當只有檢測器3丨〇與該些 基板單元200之端點306電性連接時，可利用該電子測量裝 置314測試該些基板單元2〇〇上電路圖案是否有短路的現 象。然後，使該檢測器312上之該些導電接墊318各盥一基 板早TO20 0上之所有端點3〇8接觸。當檢測器31〇與312同時 與該些基板單元20 0電性連接時，可利用該電子測量裝置 31 ^測試該些基板單元2〇〇上電路圖案是否 \ 本之裝置以及方法可測試不具導電= 板亚且可同犄測試一基板上的多個基板單元之電 ，。與傳統的飛針測試法比較起來， 供 :。本發明可大幅降低測試所消耗的：間=產= 用於測試量產的基板。 ^风丰因此可 雖然本發明已以前述較佳實 當;IK;:;動藝：，在不脫離:發 圍當視後附之申請專利範者=本發明之保護範 00810.ptd 第11頁 1229740 圖式簡單說明 【圖式簡單說明】 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯，下文特舉本發明較佳實施例，並配合所附圖示，作詳細 說明如下。 第1圖：根據本發明一實施例之基板之上視圖； 第2圖：第1圖基板之一區域A之局部放大上視圖； 第3圖：根據本發明之一實施例，以本發明提供之裝置測 試待測基板之不意圖， 第4圖：根據本發明一實施例之檢測器之部分剖視圖； 第5圖：根據本發明一實施例之檢測器之上視圖； 第6圖：根據本發明一實施例之檢測器之底板剖視圖； 第7圖：根據本發明一實施例之檢測器之底板剖視圖；以 及 第8圖：根據本發明一實施例之檢測器之底板剖視圖。 圖號說明： 100 基板 200 基板單元 202 電路圖案 204 晶片設置區 302 第一面 304 第二面 306 端點 308 端點 310 檢測器 312 檢測器 314 電子測量裝置 315 連接接點00810.ptd Page 10 1229740 V. Description of the invention (6) § Whether the substrate unit 200 has a short circuit (short) and an open circuit (oop). The invention also provides a method for testing the electrical characteristics of a plurality of substrate units on a substrate. First, the connection points 315 of the detector 310 are brought into contact with the end points 306 of the substrate units 200. When only the detector 3 is electrically connected to the terminal 306 of the substrate units 200, the electronic measuring device 314 can be used to test whether the circuit patterns on the substrate units 200 are short-circuited. Then, each of the conductive pads 318 on the detector 312 is brought into contact with all the terminals 308 on the substrate as far as TO200. When the detectors 31 and 312 are electrically connected to the substrate units 200 at the same time, the electronic measuring device 31 can be used to test whether the circuit patterns on the substrate units 200 are not tested. The device and method can test that there is no conductivity = Board Asia and can test the electricity of multiple substrate units on a substrate simultaneously. Compared with the traditional flying probe test method, for:. The invention can greatly reduce the consumption of testing: time = production = substrate for testing mass production. ^ Feng Feng is therefore available although the present invention has been based on the aforementioned better practice; IK;:; Page 1229740 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiment of the present invention in detail with the accompanying drawings as follows. Fig. 1: Top view of a substrate according to an embodiment of the present invention; Fig. 2: Partial enlarged top view of an area A of the substrate of Fig. 1; Fig. 3: According to an embodiment of the present invention, provided by the present invention The device does not intend to test the substrate to be tested. Figure 4: Partial cross-sectional view of the detector according to an embodiment of the present invention; Figure 5: Top view of the detector according to an embodiment of the present invention; Figure 6: According to the present invention Sectional view of a bottom plate of a detector according to an embodiment of the invention; FIG. 7: Sectional view of a bottom plate of a detector according to an embodiment of the invention; and FIG. 8: Sectional view of a bottom plate of a detector according to an embodiment of the invention. Description of drawing number: 100 substrate 200 substrate unit 202 circuit pattern 204 wafer setting area 302 first side 304 second side 306 endpoint 308 endpoint 310 detector 312 detector 314 electronic measurement device 315 connection contact
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