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TWI298189B - Phase change material memory device and method of fabricating the same - Google Patents

Phase change material memory device and method of fabricating the same Download PDF

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Publication number
TWI298189B
TWI298189B TW95118717A TW95118717A TWI298189B TW I298189 B TWI298189 B TW I298189B TW 95118717 A TW95118717 A TW 95118717A TW 95118717 A TW95118717 A TW 95118717A TW I298189 B TWI298189 B TW I298189B
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Taiwan
Prior art keywords
layer
phase change
manufacturing
change material
dielectric
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TW95118717A
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Chinese (zh)
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TW200744159A (en
Inventor
Chung Yi Chen
ming yu Lin
Ching Hung Fu
Yueh Chi Wu
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Promos Technologies Inc
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Priority to TW95118717A priority Critical patent/TWI298189B/en
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Publication of TWI298189B publication Critical patent/TWI298189B/en

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1298189 九/發明說明: 【發明所屬之技術領域】 本發明係有關一種記憶體元件及其製造方法, 一 相變材料之記憶體元件及其製造方法。 疋一種具 【先前技術】 ,著半導„的更新演進,記憶 •速往物理極限邁進。其中,相變材料記憶體 量密度等優點,是目前極力發展的非揮發性記憶之= 地相J^hase Change Materi啦在著至少兩個 恝’一為非晶體(Amorphous)狀態,另一為晶體 相,,在這兩個狀態之間可逆地轉變。此相^以 從曰曰體狀悲轉變為非晶體狀態,亦可再由非 ϋΐ為f?體狀<%,直到全部轉變為非晶體狀態為止。若溫度 由於Ui材,則將可由非晶體狀態逐漸地恢復為晶體狀態。 ίϊϊΐϊ=ίί,相之原子結構較無秩序,因此其於非晶體 之ΙΓϋΐ:相時之電阻值為高。從而,由相變材料 F可區为出相變材料之至少二個不同穩定狀態。 特性應f上,變材料之『溫度變化—相變—電阻變化』 杜士兔4 Η乍為^己匕體兀件之暝寫功能之控制,使該記憶體元 成為一相交隨機存取記憶體(Phase Change Random Access 1298189 M_y ; PRAM)。具體衫’祕域材料翻於城體元 ^己憶體胞時,係-個以電流方式加熱之導體材料,作 度=熱器’以改變其溫度’達到控制相變材ί之 L,r丨果/、ί"’較為f見之相變材料為硫族元素化合 ,(ChalCOgenide)所組成之合金,其包含週期表上第六族 ,射較為穩定的相變材料合金為鍺銻碲(GeSbT :: ^實際應用上,根據實驗發現,當於作為加熱器之&體 相變材丨4之間加人-界面層’將可降低通人導體材料之操作 ^ ’而收小之電流所產生讀低加熱 料產生相機讀果,有秘記鐘元狀操作蛾相夂材 由於在έ己憶體元件之操作上,需仰賴高 方能發巧元件之讀寫功能。又,々於相錳騐 2之Ϊ寫功能’全部依賴相變材料之相轉變控制效果上,^相 轉變狀悲之控制十分關鍵而重要。然❿,習知之 & ,況下,即會使得相變;=,4口; 此’如何朗刖34域材料之·於記鐘元件 做為多階(murn-i,使用,實為一個亟待努力触的問題衣。 【發明内容】 有鑑於此,本發明之一目的係捭 法’該方法包含以下步驟。首;^=;;種f憶體元件之製造方 f!層:用以形成:開口以暴露出該 下電極。其次,去i销口内之介電層侧壁以及該 壁上形成二第一導ΐ間二;電j成以= 條有,形成一界面層,以覆蓋該第 I298l89 後隙气’其中’該界面層之厚度係由下往上逐漸遞增。最 7成一相變材料層,以覆蓋該介電層以及該開口内之界面層。 體元^明之再—目的係提供—種具有多階段相轉變特性之記憶 壁、該記憶體元件係包含-下電極、—介電層、—導電間隙 包人二界面層、一相變材料層,該介電層係位於該下電極上方且 該pi of σ以暴露出其1Γ方之部分下雜,該導電間隙壁係位於 導電介電層側壁以及該下雜之上方,該界面層係覆蓋該 居t i壁,且該相變材料層係覆蓋該介電層及該和内之界面 曰,、中,該界面層之厚度係由下往上逐漸遞增。 【實施方式】 如柄ί If以本發日錄造方法之—較佳實補,具體說明本發明 ^用相變材料作為記憶體元件之記憶體胞圊 巧於-下電極10上形成一介電層12以覆蓋下‘二 以I當之光罩(未顯示)圖案化該介電層12,藉以在介電芦之 ^當,置形成-開π 14’並暴露出介電層12下方之部j二 1〇。其中,該下_ 10係以傳統之技術沉獅成於一魏底( ^de)專)所構成。其次,介電層12為一内層介電層(ι咖 leectnc ’ ILD) ’主要作為一電性與熱能之絕緣體。因此 合宜阻隔電與熱之材料,均可介電層12。舉例言之 體實施例中,可以二氣化石夕為介電層12之材料。 /、 接著’形成-第-導電層16,以覆蓋於介電層12之上 J開口 14内之介電層12之側壁以及經開σ 14所暴露出之部g 電極10。可使用任何合宜之材料以任何合宜之傳統沉積技^^ 1298189 =第-導電層16 ’例如,使用 方式沉積-金屬材料而形成該第一導積或物理氣相沉積之 其次,請參閱第2圖,圖中顯示去 以於開π 14内之介· 12側壁上j之弟-導電層16’ 較佳實施例中,可以非等向性 ^ 4導電間I8。於一 面部分之第一導電層16,而保留除位於介電層12上表 部分第-導電層16,於開口 14内之介=介電層12側壁上之 18之結構。於此,須說明者,於除:2』則壁上形成間隙壁 程步驟時,未必須將開口 14底部、弟—導電層16之製 J-:電層16全部移除。此即,無:;之:巧圣1〇上方之 分之苐-導電層16,或者將開口 M 4—底。P疋否仍保留部 僅留下如第2圖之間隙壁18結構——電層16移除, 行,亦不實質地影響本發明所揭露相變^^=後^程之進 以下為方便制起見,㈣暴露出開口之特性。 面為例。 &邛之下電極10上表 睛繼續參閱第3圖,以任何合宜之方 ,以覆蓋於第2圖所示之結構上。舉例二導電層 之方式沉積該第二導電層2〇,以覆蓋;了利:物理氣相 之弟一導電間隙壁18結構上、以及開口 Η内 1極^上。接著’再以—非等向性爛方式去之^分下 2〇,取後形成覆蓋於第-導電間隙壁18上、且二:第7導電層 遞增之一界面層(lnterfacial L )22, 二,下往上逐漸 構側壁外之厚度為厚,且於間隙壁18結構側壁18結 上厚度逐漸遞增之構形。較佳地,此界面層22卜戸、見—由下往 最薄處厚度之至少L5倍,更佳為至少2倍。須厚度係為 -上厚下薄之界輯結構之方法並不僅限於物理氣相成^ 8 1298189 露 於本發明中,所採用以構成界面層22之第 Ϊ採===,層16材料之電阻“例言ί材 田抓用鶴金屬料-導電層b之材料 彳:之 -物料為第二導電層2〇之材料··鈦、氮化自=群組之 氮化组、及其組合。如後詳述,本發明經_匕鈦、 結構之界面層22,且其電阻值大於第一導 月厚下薄 長所含相變材料層於完全非晶體狀能I^ θ材枓,可有效延 圖,面覆層 之界面層22、以及開口 14底部覆盍二J層12、開口 14内 何合宜之方式以形成該相變材料層斤 式進行形成相變材料層24之步驟。可於;“ 相變材料。於此,當相變材料層24 ;== = 值必織_壁18與界面層22>誠^_1冊日$其阻 變材料,則其阻值必須較間隙壁採用低阻值相 ί24之材料可為硫族元素化合物,較佳地, 為鍺銻碲合金。一適用於本發明之特定相 ^ ί _ 18採祕。於形成相變材料層241298189 Nine/Invention Description: TECHNICAL FIELD The present invention relates to a memory element and a method of fabricating the same, a memory element of a phase change material, and a method of fabricating the same.疋A kind of [previous technology], the semi-conducting update evolution, memory and speed to the physical limit. Among them, the phase change material memory mass density and other advantages, is currently the development of non-volatile memory = the ground phase J ^hase Change Materi is at least two 恝' one in the Amorphous state, the other is the crystal phase, and reversibly transforms between these two states. In the amorphous state, it can be changed from non-ϋΐ to f? body shape until all of them are converted to an amorphous state. If the temperature is due to the Ui material, it will gradually return to the crystal state from the amorphous state. Ίί, the atomic structure of the phase is relatively disordered, so it is in the amorphous state: the resistance value of the phase is high. Therefore, the phase change material F can be distinguished as at least two different stable states of the phase change material. On the upper part of the material, "temperature change - phase change - resistance change" Du Shitu 4 is the control of the write function of the body, so that the memory element becomes a intersecting random access memory (Phase Change Random Access 129 8189 M_y ; PRAM). The specific shirt 'secret material turned over to the city body ^ when recalling the body cell, the system - a conductor material heated by current, the degree = heat 'to change its temperature' to achieve control phase change L,r丨果/, ί" 'The phase change material is a chalcogenide compound, an alloy composed of (ChalCOgenide), which contains the sixth group of the periodic table, and the relatively stable phase change material The alloy is bismuth (GeSbT :: ^ practical application, according to the experiment, when adding a human-interface layer between the & body phase material 丨4 as a heater will reduce the operation of the conductor material ^ 'And the small current generated by the reading of the low heating material produces a camera reading fruit, there is a secret clock element operation moth phase coffin due to the operation of the έ 忆 体 体 元件 元件 需 需 需 高 高 高 高 高 高 高 高 高Function. In addition, 々 相 相 锰 验 验 验 验 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' That will make the phase change; =, 4 ports; this 'how to recite the 34 domain material in the clock component As a multi-step (murn-i, use, it is a problem that needs to be touched by the hard work. [Invention] In view of this, one of the objects of the present invention is the method of the method comprising the following steps: first; ^=; a manufacturing layer f: layer for forming: an opening to expose the lower electrode. Secondly, a sidewall of the dielectric layer in the pin opening and a second guiding channel are formed on the wall; j is formed as a strip, forming an interfacial layer to cover the I298l89 back gap gas 'where' the thickness of the interfacial layer is gradually increased from bottom to top. The most 7-in-one phase change material layer covers the dielectric layer And an interface layer within the opening. The body element is further provided with a memory wall having a multi-stage phase transition characteristic, the memory element comprising a lower electrode, a dielectric layer, a conductive gap, a second interface layer, and a phase change material layer. The dielectric layer is located above the lower electrode and the pi of σ is exposed to a portion of the conductive layer. The conductive spacer is located on the sidewall of the conductive dielectric layer and above the lower impurity. The ti wall is covered, and the phase change material layer covers the dielectric layer and the interface between the dielectric layer, and the thickness of the interface layer gradually increases from bottom to top. [Embodiment] If the handle ί If is made by the method of the present invention, it is better to use the phase change material as the memory element of the memory cell to form a medium on the lower electrode 10. The electrical layer 12 is patterned to cover the dielectric layer 12 under the lithography (not shown), thereby forming a - π 14' and exposing the dielectric layer 12 under the dielectric reed. The second part of the j. Among them, the lower _ 10 series is made up of the traditional technology of the lion into a Wei (the (de) special). Secondly, the dielectric layer 12 is an inner dielectric layer (ILD) which acts primarily as an insulator for electrical and thermal energy. Therefore, it is preferable to block the electrical and thermal materials, and the dielectric layer 12 can be used. For example, in the embodiment, the material of the dielectric layer 12 may be a gas. Then, a -first conductive layer 16 is formed to cover the sidewall of the dielectric layer 12 in the J opening 14 over the dielectric layer 12 and the portion g electrode 10 exposed by the opening σ 14 . Any suitable material may be used in any suitable conventional deposition technique ^^1298189 = first conductive layer 16', for example, by depositing a metal material to form the first or physical vapor deposition, see second In the figure, the figure shows that in the preferred embodiment, the conductive layer 16' on the sidewall of the dielectric layer 12 is opened. The preferred embodiment can be anisotropic. The first conductive layer 16 is partially disposed on the surface of the first conductive layer 16 except for the first conductive layer 16 on the surface of the dielectric layer 12 and on the sidewall of the dielectric layer 12 in the opening 14. Here, it should be noted that, in addition to: 2", when the gap wall step is formed on the wall, it is not necessary to remove all of the J-: electrical layer 16 of the bottom of the opening 14 and the conductive layer 16. That is, no:; it: the top of the 圣 〇 1 苐 导电 - conductive layer 16, or the opening M 4 - bottom. P疋No, the remaining portion only leaves the structure of the spacer 18 as shown in FIG. 2—the electrical layer 16 is removed, and does not substantially affect the phase change disclosed in the present invention. See, (d) expose the characteristics of the opening. Face as an example. The upper surface of the electrode 10 under & 继续 continues to refer to Fig. 3, in any suitable manner, to cover the structure shown in Fig. 2. The second conductive layer 2 is deposited by way of a second conductive layer to cover the structure of the physical gas phase, the conductive spacer 18, and the opening of the opening. Then, in the non-isotropic manner, the second layer is formed, and the second layer is formed on the first conductive layer 18, and the second layer is increased by one interface layer (lnterfacial L) 22, Second, the thickness of the outside of the sidewall is gradually thicker, and the thickness of the sidewall 18 of the spacer 18 is gradually increased. Preferably, the interface layer 22 is at least L5 times, more preferably at least 2 times thicker from the bottom to the thinnest portion. The method in which the thickness is the upper-thickness and thin-layered structure is not limited to the physical vapor phase formation. 8 1298189 is disclosed in the present invention, and is used to form the interface layer 22 of the first layer ===, layer 16 material Resistance "Example ί material field grabs the crane metal material - the material of the conductive layer b 之: - the material is the second conductive layer 2 〇 material · titanium, nitrided from the group of nitride groups, and combinations thereof As will be described later in detail, the present invention is characterized in that the interfacial layer 22 of the structure of titanium and titanium has a resistance value greater than that of the phase change material layer contained in the thin and long thickness of the first meniscus thickness in the completely amorphous energy. The step of forming the phase change material layer 24 can be performed by forming the phase change material layer 24 in such a manner that the interface layer 22 of the surface cladding layer and the bottom layer of the opening 14 cover the second J layer 12 and the opening 14 are suitable. Available; "phase change material. Here, when the phase change material layer 24; == = value must be woven _ wall 18 and interface layer 22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The material may be a chalcogenide compound, preferably a niobium alloy. A specific phase of the invention is applied to the invention. Forming a phase change material layer 24

It 26 ° -- 為該上電極26。 5之但不限於,可採關齡金層作 1298189 體元之製$方法’可製造—具有相變材料之記憶 上電極26。其中,介電層12位於下電極1〇之^+^^ 14以暴露出其下方之部分下電極1〇 〇導電間 =歼 内之介電層U側壁以及下電極1〇之上面;::口; 隙壁18,相變材料層24覆蓋介電声 二5後盍導電間 22 ’而上電極26則覆蓋相變材日ϋ4 之厚度係由下往上逐漸遞增。 補疋,界面層22 ㉟體:寫用一相變材料之相轉變特性,作為記 與相變_24之間’因此本發狀記⑽ 可己,内之導電間隙壁18的操作:流 之相轉變=;。詳:二件^ 導雷間隙辟18 #作上’當作為加熱器之 、i_i 18^2;^^=目細_分的電流 ϊί相if? ’ f該區域之相變材制始發生相轉變之現象,; iiUt變材料層24中位於該已轉變成非晶體狀離,區 相交材㈣24全部轉縣非晶雜祕止。 1298189 變二步 將使相 Η上層 在整個相變材料層24之相轉變過程中,可相 ,曰’ 變之穩定狀態。於一較佳之實施例中,除τ盾杰J侍夕階段相轉 體狀態二個,態义外,可額外地獲得二個穩定的狀態與非晶 發生,因此可以有效地延長相變材料層24之 ' >?5p ^C/{UI is ^ Ο Δ. -> 4-a i a _i_ t「日 1。足而 段 J(〇,〇) > (0,1)>(1,0)^:^; ;;;:: 穩戈且具多階段相變材料之記憶體元件及可 以作為新一代之記憶體元件。 /、衣&方法 用此四個狀態於記龍元件之讀寫功能時°應 體_)、ro η、nno—m — 胃應3也作為記 實施=?此ΐϊί人員所瞭解的,以上所述僅為本發明之較佳 離本發明限定本發明之申請專利範圍;凡其它未脫 下述“請專所完成之·改變或修飾,均應包含在 【圖式簡單說明】 壯能第5醜示本發明细相變材料以製造多階段相變 狀悲之C憶體元件之示意圖。 【主要元件符號說明】 10 下電極 14 開口 18 第一導電間隙壁 22 界面層 26 : 上電極 12 :介電層 Μ:第一導電層 2〇 :第二導電層 24 :相變材料層It 26 ° -- for the upper electrode 26. 5, but not limited to, can be used to make a 1928189 voxel method. The method can be manufactured as a memory upper electrode 26 with a phase change material. Wherein, the dielectric layer 12 is located at the lower electrode 1 ^ ^ ^ ^ 14 to expose a portion of the lower electrode 1 〇〇 conductive region = the dielectric layer U sidewall and the lower electrode 1 〇 above; The gap wall 18, the phase change material layer 24 covers the dielectric sound 2 and the back surface of the conductive layer 22', and the upper electrode 26 covers the phase change material. The thickness of the day 4 gradually increases from bottom to top. Replenishment, interface layer 22 35 body: write phase transition characteristics of a phase change material, as between the phase change and the phase change _24, so the operation of the conductive gap (18), the operation of the conductive spacer 18: flow Phase transition =;. Details: Two pieces ^ Guide Thunder clearance 18 #作上'When it is used as a heater, i_i 18^2; ^^=The current is _分的相ϊif?' f The phase changer in this area begins to occur The phenomenon of transformation, the iiUt variable material layer 24 is located in the amorphous phase, and the intersecting materials (4) 24 all turn to the county. 1298189 Changing the two steps will make the phase of the phase change in the phase transition of the phase change material layer 24, and the phase can be stabilized. In a preferred embodiment, in addition to the state of the phase change body of the τ shield Jie J, the two states can be obtained in addition to the amorphous state, so that the phase change material layer can be effectively extended. 24' >?5p ^C/{UI is ^ Ο Δ. -> 4-aia _i_ t "Day 1. Foot and paragraph J (〇, 〇) >(0,1)> (1, 0)^:^; ;;;:: Memory components with stable phase and phase change materials and can be used as a new generation of memory components. /, Clothing & method uses these four states in the Dragon component When reading and writing functions, the body should be _), ro η, nno-m - the stomach should also be implemented as a record. The above is only a preferred embodiment of the present invention. The scope of the patent application; where the other does not remove the following "please complete the change, or modify, should be included in the [simplified description of the schema] Zhuangneng 5th shows the fine phase change material of the present invention to produce a multi-stage phase change Schematic diagram of the sorrowful C memory element. [Main component symbol description] 10 Lower electrode 14 Opening 18 First conductive spacer 22 Interfacial layer 26 : Upper electrode 12 : Dielectric layer Μ: First conductive layer 2 〇 : Second conductive layer 24 : Phase change material layer

Claims (1)

1298189 、申請專利範圍: 一種記憶體元件之製造方法,該製造方法包含: 提供一下電極; 於該下電極上方形成一介電層; 方介電層’用以形成―開口,並暴露出該介電層下 方部份之該下電極; 3一 Γί”於該開口内該介電層側壁; 形成一界面層,覆盍該第一導電間隙壁,1 厚度由下往上逐漸遞增;以及 八Μ I曰 層。形成-相紐冊’錢該介電相及綱叫之該界面 2· 製造方法,其中形成該第- 導電層之步驟係 3.如物2所㈣織,其巾綱㈣料係為鎮。 .如步所㈣繊,㈣购—㈣間義之 暴露部^電:電覆蓋該開口内該介電層側壁以及該 • D内料㈣繼^導電知於該開 ^ ㈣物處之厚度騎 1 6. 1298189 界面層最薄處厚度之至少2倍。 如之製造方法,其中形成該界面層之步驟更包含·· 蓋該該第二導電層,以形成覆 係义電^該第二導電層材料之電阻值 9. τ,製造方法,其中該第二導電層之材料係 ΐ組合 統鈦、嫣化鈦、⑽化鈦、氮化组、及 1〇* 5 之製造方法’其中該相變材料層之材料係為硫 12.=t所述之製造方法,其彻__之材料係為 13ΐίί。12所狀製造雜,射軸紐辦之材料係為 變材 14.如請求項1所述之製造方法,更包含形成一上電極於 料層上方之步驟。 Μ 2 1298189 15· 一種疏體元件,該記紐元件包含: 一下電極; 介電部’以暴露出該 之上方^電間隙壁’位於該開口内該介電層側壁以及該下電極 增;^面層,覆蓋該導電間隙壁且其厚度係由下往上逐漸遞 一相變材料層,覆蓋該介電層以及該開Π内之該界面層。 16.如請求項15所述之記憶體元件,其中該導電層係為-金屬層。 月求項I6所述之s己憶體元件,其中該金屬層之材料係為鶴。 1⑵樹處之厚度 中該界面層最厚處之厚度 21. ΐΐϊϋ或2G所述之記憶體元件,其中該界面層之材料係 t自^下群組:鈦、氮化鈦、鶴化鈦、氣銘化欽、氮化组 具組合。 A 22. 如請求項15所述之記憶體元件,其中該相變材料層之材料係 3 1.298189 為硫族元素化合物。 23. 如請求項22所述之記憶體元件,其中該相變材料層之材料係 為錄銻蹄合金。 24. 如請求項23所述之記憶體元件,其中該相變材料層之材料係 為 Ge2Sb2Te5。 25. 如請求項15所述之記憶體元件,其更包含一上電極覆蓋該相 變材料層。1298189, the scope of patent application: a method for manufacturing a memory device, the manufacturing method comprising: providing a lower electrode; forming a dielectric layer over the lower electrode; and forming a dielectric layer to form an opening, and exposing the dielectric a portion of the lower electrode of the lower portion of the electrical layer; 3 Γ ” 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于I 曰 layer. Forming - phase book 'money the dielectric phase and the interface of the interface 2 · manufacturing method, wherein the step of forming the first conductive layer is 3. The second (four) weave, the towel (four) material The department is the town. If the step is (4) 繊, (4) purchase - (4) the sense of the exposed part ^ electricity: electricity covering the opening of the dielectric layer sidewall and the D material (4) followed by the conductive knowledge of the opening ^ (four) The thickness of riding 1 6. 1298189 is at least 2 times the thickness of the thinnest part of the interface layer. The manufacturing method, wherein the step of forming the interface layer further comprises: covering the second conductive layer to form a coating system The resistance value of the second conductive layer material is 9. τ, manufacturing method The material of the second conductive layer is a combination of titanium, titanium telluride, (10) titanium, nitrided group, and 1〇* 5 manufacturing method, wherein the material of the phase change material layer is sulfur 12.= The manufacturing method described in the above is a material of 13 ΐ ίί. The material of the injection shaft is made of a material. The manufacturing method according to claim 1 further comprises forming a The step of the electrode above the layer. Μ 2 1298189 15 · A body element comprising: a lower electrode; a dielectric portion 'to expose the upper ^ electrical spacer' in the opening The sidewall and the lower electrode are provided with a surface layer covering the conductive spacer and having a thickness gradually transferring a phase change material layer from the bottom to the top, covering the dielectric layer and the interface layer in the opening. The memory device according to claim 15, wherein the conductive layer is a metal layer, wherein the material of the metal layer is a crane. 1 (2) the thickness of the tree The thickness of the interface layer is the thickest part 21. The memory element described in ΐΐϊϋ or 2G, The material of the interface layer is a combination of titanium, titanium nitride, titanium, yttrium, and nitriding. A 22. The memory component of claim 15, wherein The material of the phase change material layer is 1.298189 which is a chalcogen compound. 23. The memory element of claim 22, wherein the material of the phase change material layer is a hoof alloy. 24. The memory device, wherein the material of the phase change material layer is Ge2Sb2Te5. 25. The memory device of claim 15, further comprising an upper electrode covering the phase change material layer. 44
TW95118717A 2006-05-26 2006-05-26 Phase change material memory device and method of fabricating the same TWI298189B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8530939B2 (en) 2009-02-19 2013-09-10 Micron Technology, Inc. Cross-point memory structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8530939B2 (en) 2009-02-19 2013-09-10 Micron Technology, Inc. Cross-point memory structures

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