[go: up one dir, main page]

TWI295774B - Method and system for managing virtual memory - Google Patents

Method and system for managing virtual memory Download PDF

Info

Publication number
TWI295774B
TWI295774B TW92113022A TW92113022A TWI295774B TW I295774 B TWI295774 B TW I295774B TW 92113022 A TW92113022 A TW 92113022A TW 92113022 A TW92113022 A TW 92113022A TW I295774 B TWI295774 B TW I295774B
Authority
TW
Taiwan
Prior art keywords
data
block
mentioned
flash memory
logical block
Prior art date
Application number
TW92113022A
Other languages
Chinese (zh)
Other versions
TW200424853A (en
Inventor
Chiu Yu-Ping
Original Assignee
Htc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Htc Corp filed Critical Htc Corp
Priority to TW92113022A priority Critical patent/TWI295774B/en
Publication of TW200424853A publication Critical patent/TW200424853A/en
Application granted granted Critical
Publication of TWI295774B publication Critical patent/TWI295774B/en

Links

Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Description

I295774 , 7—-_-___ 五、發明說明^ 【發明所屬之技術領域】 本發明係有關於一種管理虛擬記憶體的方法及系統, 寺別是針對快閃記憶體而言。 【先前技術】 非揮發性半導體記憶體,例如:快閃記憶體(n ash "^mory ) ’是有助於將資料長期儲存於電腦系統中,尤其 疋針對掌上型電腦(p〇cket pc)。快閃記憶體剩餘的空間 有助於儲存不同的軟體擴充,例如:CpQ OPT丨⑽jACKET、 重要的文件或資料。 存取快閃記憶體並不容易。快閃記憶體就像一個硬 碟被分割成§午多頁(page)和區塊(block)。而不是只寫 入一個字元(word)在一頁中,而是全部的頁必須同時寫 入’且單獨的位元組(by tes)無法寫入。在寫入之前,頁 =須利用快閃記憶體的清除週期,清除先前的資料。全部 區塊中的頁’會在同時間内被清除。舉列而言,假設一個 區塊中有1 6頁,當所有區塊中的頁在同時間内都被清除 了 ’則每頁中的5 1 2 by t e也會被一起清除。 快閃έ己憶體用於儲存資料是簡單的,它需要一個虛擬 5己憶體的管理系統及方法,以達到一快閃檔案系統。 【發明内容】 ...... 本發明主要目的係為.利用快閃記憶體剩餘的空間作為 一快閃檔案系統。 ^ ^為達到上述目的,本發明提出一種管理虛擬記憶體的 系統及方法’適用於快閃記憶體系統。在緩衝器中的邏輯I295774, 7--_-___ V. EMBODIMENT DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method and system for managing virtual memory, which is for flash memory. [Prior Art] Non-volatile semiconductor memory, such as flash memory (n ash "^mory ) 'is helpful for long-term storage of data in computer systems, especially for handheld computers (p〇cket pc ). The remaining space in the flash memory helps to store different software extensions, such as: CpQ OPT丨(10)jACKET, important files or data. Accessing flash memory is not easy. Flash memory is like a hard disk divided into § no more pages and blocks. Instead of just writing one word (word) on one page, all pages must be written at the same time 'and a single byte (by tes) cannot be written. Before writing, page = must use the flash memory clear cycle to clear the previous data. Pages in all blocks will be cleared at the same time. For example, suppose there are 16 pages in a block. When all the pages in the block are cleared at the same time, then 5 1 2 by t e in each page will be cleared together. It is simple to use flash memory to store data. It requires a virtual management system and method to achieve a flash file system. SUMMARY OF THE INVENTION The main purpose of the present invention is to utilize the remaining space of the flash memory as a flash file system. ^ ^ To achieve the above object, the present invention proposes a system and method for managing virtual memory that is suitable for use in a flash memory system. Logic in the buffer

0746-8150twf(nl);910009-0-tw;joanne.ptd 第5頁 1295774 五、發明說明(2) &lt; 區塊係用以儲存從快閃記憶體中之實體區塊複製得來之資 料。 一輸入/輸出裝置,需要一操作系統存取第一資料。 操作系統在緩衝器中,搜尋邏輯區塊的資料。若資料位址 相同,則在緩衝器中有邏輯區塊儲存第一資料,並且會被 β 存取。若資料位址不相同,則在緩衝器中沒有邏輯區塊儲 ‘ 存第一資料,並且操作系統會在快閃記憶體中,搜尋實體 區塊中的資料。 在搜尋邏輯區塊資料之前,操作系統會檢查邏輯區塊 中的異常旗標是否被致能,若是,則快閃記憶體中的操作φ 系統會將邏輯區塊寫回實體區塊;若否,當操作系統除去 緩衝器中的邏輯區塊,則一寫回程序會被儲存。 操作系統在快閃記憶體中,搜尋實體區塊的資料。若 資料位址相同,則在快閃記憶體中的實體區塊會儲存第一 資料並且將其複製到一邏輯區塊。若資料位址不相同,則 實體區塊不會在快閃記憶體中,儲存第一資料。回到開始 處去存取資料。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,,下文特舉出較佳實施例,並配合所附圖式,作詳 B 細說明如下: _ 【實施方式】 第1圖顯示一管理虛擬記憶體之系統方塊圖。系統包 括:一輸入裝置1 0、一輸出裝置、一操作系統檔案系統 30、一緩衝器40以及一快閃記憶體50。0746-8150twf(nl);910009-0-tw;joanne.ptd Page 5 1295774 V. Invention Description (2) &lt; Block is used to store data copied from physical blocks in flash memory . An input/output device requires an operating system to access the first data. The operating system is in the buffer and searches for the data of the logical block. If the data addresses are the same, there is a logical block in the buffer that stores the first data and is accessed by β. If the data addresses are not the same, there is no logical block in the buffer to store the first data, and the operating system searches for the data in the physical block in the flash memory. Before searching for logical block data, the operating system checks whether the abnormal flag in the logical block is enabled. If so, the operation φ in the flash memory will write the logical block back to the physical block; When the operating system removes the logical block in the buffer, a write back program is stored. The operating system searches for data in the physical block in the flash memory. If the data addresses are the same, the physical block in the flash memory stores the first data and copies it to a logical block. If the data addresses are not the same, the physical block will not store the first data in the flash memory. Go back to the beginning to access the data. The above and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Figure 1 shows a system block diagram of managing virtual memory. The system includes an input device 10, an output device, an operating system file system 30, a buffer 40, and a flash memory 50.

0746-8150twf(nl);910009-0-tw;joanne.ptd 第6頁 1295774 五、發明說明(3) 第2 A圖顯示虛擬記雕 括:邏輯區塊nU〜mA。快;;記憶體 '緩衝器40包 邏輯區塊m 1〜mA和實體區、°思包括:實體區塊η 1〜nB。 第2B圖顯示一邏輯Α η ηβ,存取均是利用位址。 實體區塊複製過來的資:/内容。邏輯區塊包括··由一 常旗標。邏輯區塊的更新θ ==二及用以代表寫回的一異 定。 更新疋根據本身被指定位址的範圍而 若邏輯區塊被變更,則里 邏輯區塊會被摒辛,並日i : 八払將。知操作系統3 0, 包括 塊未被變更,^作===閃記,5〇°若邏輯區 時,一寫回程序會被儲存。’f、、友衝^ 40中的邏輯區塊 第3圖顯示管理虛擬士产 下列步驟: 錢5己憶體的輸入資料流程圖 步驟301:輸入資料程序開始。 步驟302··由輸入裝置1〇輸入資料]^1。 入。步驟30 3:輸入裝置1〇要求操作系統3〇將資料㈤寫 步驟304:操作系統3〇在緩衝器4〇的邏輯區 資料Dxl。 孜寸 卜步驟305 :若資料位址與資料Dx 1之位址相同,則在緩 衝器40中有一邏輯區塊mxl儲存資料1)}(;1,然後執行步驟 306。若資料位址與資料Dxl之位址不相同,則在緩衝器仙 中’沒有邏輯區塊儲資料J)x 1,然後執行步驟3 〇 7。 步驟30 6 :緩衝器4〇中的邏輯區塊mxi被更新成儲存資 0746-8150twf(nl);910009-0-tw;j〇anne.ptd 第7頁 1295774.0746-8150twf(nl);910009-0-tw;joanne.ptd Page 6 1295774 V. Invention Description (3) Figure 2A shows the virtual record: logical block nU~mA. Fast;; memory 'buffer 40 packets logical block m 1~mA and physical area, including: physical block η 1 ~ nB. Figure 2B shows a logical Α η ηβ with access using the address. The assets copied from the physical block: / content. The logical block consists of a constant flag. The update of the logical block θ == two and an exception to represent the write back. Update 疋 If the logical block is changed according to the range of the specified address, the logical block will be smashed, and the day i: gossip will be. Knowing the operating system 3 0, including the block has not been changed, ^ === flash, 5 〇 ° If the logic area, a write back program will be stored. Logic of the 'f, 友, 冲 ^ 40 Figure 3 shows the management of the virtual sergeant. The following steps: Input data flow chart of the money 5 mnemonic Step 301: Enter the data program to start. Step 302·· Input data]^1 from the input device 1〇. In. Step 30 3: The input device 1 requires the operating system 3 to write the data (5). Step 304: The operating system 3 is in the logical area Dxl of the buffer 4. Step 305: If the data address is the same as the address of the data Dx 1, a logical block mx1 is stored in the buffer 40 to store the data 1)} (; 1, and then step 306 is performed. If the data address and data If the address of Dxl is not the same, then in the buffer, there is no logical block storing data J) x 1, and then step 3 〇7 is executed. Step 30 6: The logical block mxi in the buffer 4〇 is updated to the storage resource 0746-8150twf(nl); 910009-0-tw; j〇anne.ptd page 7 1295774.

料Dxl。邏輯區塊mxl的異常旗標被致能。 步驟307:若有邏輯區塊的異常旗標(dirty flag)被致 月b,則執行步驟3〇8。若沒有邏輯區塊的異常旗標被致 能’則執行步驟30 9。 步驟308 :當有邏輯區塊(假設mx丨)之異常旗標被致 能,在快閃記憶體50中的實體區塊nkl的資料被緩衝器4〇 中的邏輯區塊mxl的資料更新。 步驟309 :操作系統30在快閃記憶體5〇中搜尋儲存 料Dxl的實體區塊。 、 —步驟31 0 :若資料位址相同,則在快閃記憶體5〇中有一 貫體區塊nxl儲存資料Dxi,然後執行步驟311。若資料位 址不相同,則在快閃記憶體5G中,沒有實體區塊用以儲存 資料Dxl,然後執行步驟3〇1。 、步驟311 :操作系統30將快閃記憶體50的實體區塊ηχ1 複製到在緩衝器40中的一邏輯區塊mzl,然後執行步驟 30 6。邏輯區塊mzi被資料Dxi更新。 第4圖顯示管理虛擬記憶體的輸出資料流程圖。 下列步驟: 步驟4 0 1 :輸出資料程序開始。Material Dxl. The exception flag of the logical block mxl is enabled. Step 307: If the dirty flag of the logical block is caused by the monthly b, then step 3〇8 is performed. If no exception flag of the logical block is enabled, then step 319 is performed. Step 308: When the abnormal flag of the logical block (assuming mx丨) is enabled, the data of the physical block nk1 in the flash memory 50 is updated by the data of the logical block mx1 in the buffer 4〇. Step 309: The operating system 30 searches the flash memory 5 for the physical block of the storage Dx1. - Step 31 0: If the data addresses are the same, a block block nx1 stores the data Dxi in the flash memory 5, and then step 311 is performed. If the data addresses are not the same, in the flash memory 5G, there is no physical block for storing the data Dxl, and then step 3〇1 is performed. Step 311: The operating system 30 copies the physical block η χ 1 of the flash memory 50 to a logical block mz1 in the buffer 40, and then performs step 306. The logical block mzi is updated by the data Dxi. Figure 4 shows the flow chart of the output data for managing virtual memory. The following steps: Step 4 0 1 : The output data program starts.

步驟402:輸出裝置20要求輸出資料Dx2。 步驟403:輸出裝置20要求操作系統3〇返回資料“?。 步驟4〇4:操作系統3〇在緩衝器4〇的邏輯區塊中, 步驟405:若資料位址與資料Dx2之位址相同,則在緩Step 402: The output device 20 requests the output data Dx2. Step 403: The output device 20 requests the operating system 3 to return the data "?. Step 4: 4: the operating system 3 is in the logical block of the buffer 4", step 405: if the data address is the same as the address of the data Dx2 Is slowing down

12957741295774

衝器40中一邏輯區塊mx2儲存資料Dx2,然後執行步驟 406。若資料位址與資料Dx2之位址不相同,則在緩衝器 中’沒有邏輯區塊儲資料Dx2,然後執行步驟4〇7。 步驟406 :若資料位址與資料Dx2之位址相符合,緩衝 器40中的邏輯區塊mx2所儲存資料的Dx2會被返回。 步驟407 :若有邏輯區塊的異常旗標被致能,則執行步 驟4 0 8右’又有邏輯區塊的異常旗標被致能,則執行步驟 409。 娜 步驟408:當邏輯區塊(假設mk2)之異常旗標被致能, 在快閃記憶體50中的實體區塊nk2的資料被緩衝器4〇中的 邏輯區塊mk2的資料所更新。 步驟409 :操作系統3〇在快閃記憶體5〇中搜尋儲 料Dx2的實體區塊。 、 —步驟410 ··若資料位址相同,則在快閃記憶體5〇中有一 貫體區塊nx2儲存資料Dx2,然後執行步驟41ι。若資料位 址不相同,則在快閃記憶體5〇中,沒有實體區塊用以 資料Dx2,然後執行步驟4〇1。 步驟411 ··操作系統3〇將快閃記憶體5〇的實體區塊 複製到緩衝器40中的一邏輯區塊^?,然後執行步驟4〇6。 邏輯區塊mz2被資料dx2更新。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明:任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 μ βA logical block mx2 in the buffer 40 stores the data Dx2, and then step 406 is performed. If the data address is not the same as the address of the data Dx2, then there is no logical block in the buffer to store the data Dx2, and then step 4〇7 is performed. Step 406: If the data address matches the address of the data Dx2, the Dx2 of the data stored in the logical block mx2 in the buffer 40 is returned. Step 407: If the abnormal flag of the logical block is enabled, step 408 is performed, and the abnormal flag of the logical block is enabled. Then, step 409 is performed. Step 408: When the abnormal flag of the logical block (assuming mk2) is enabled, the data of the physical block nk2 in the flash memory 50 is updated by the data of the logical block mk2 in the buffer 4. Step 409: The operating system 3 searches for the physical block of the storage Dx2 in the flash memory 5〇. - Step 410 · If the data addresses are the same, a block block nx2 stores the data Dx2 in the flash memory 5〇, and then step 41ι is performed. If the data addresses are not the same, in the flash memory 5, there is no physical block for the data Dx2, and then step 4〇1 is performed. Step 411: The operating system 3 copies the physical block of the flash memory 5〇 to a logical block in the buffer 40, and then performs step 4〇6. The logical block mz2 is updated by the data dx2. While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of this application is subject to the definition of the scope of the patent application. β β

1295774· ^ I 圖式簡單說明 第l圖顯示一管理虛擬記憶體之系統方塊圖。 第2 A圖顯示虛擬記憶體及快閃記憶體。 第2B圖顯示一邏輯區塊的内容。 第3圖顯示管理虛擬記憶體的輸入資料流程圖。 第4圖顯示管理虛擬記憶體的輸出資料流程圖。 ~ 【符號說明】 π 1 0〜輸入裝置; 20〜輸出裝置; 3 0〜操作系統; 40〜緩衝器; $ 5 0〜快閃記憶體。 &lt;11295774· ^ I Brief Description of the Diagram Figure 1 shows a system block diagram of managing virtual memory. Figure 2A shows virtual memory and flash memory. Figure 2B shows the contents of a logical block. Figure 3 shows the flow chart of the input data for managing virtual memory. Figure 4 shows the flow chart of the output data for managing virtual memory. ~ [Symbol description] π 1 0~ input device; 20~ output device; 3 0~ operating system; 40~ buffer; $5 0~ flash memory. &lt;1

0746-8150twf(nl);910009-0-tw;joanne.ptd 第10頁0746-8150twf(nl);910009-0-tw;joanne.ptd Page 10

Claims (1)

城5774 六、申請專利範圍 1 · 一種適用於快閃記憶體系絲田 去,包括下列步驟: 、 g理虛擬記憶體的方 輸入/輪出裝置,存取 資 ,利用一操作系統判斷在—緩貝/斗, 、存上述第一資料; 釘中疋否有邏輯區塊儲 虽上述緩衝器中有一第—邏紗— 守,,存取上述第一邏輯區塊;°°龙儲存上述第一資料 當上述緩衝器中沒有邏輟 則判斷是否有-第二邏輯區塊^ =上述第-資料時, 將上气第二邏輯區塊之第二資料寫=標被致能; 一第二實體區塊; 寫回上述快閃記憶體中的 邦·斷上述快閃記情體中I 述第一資料;以及μ 疋否有一第一實體區塊儲存上 虽上述快閃記憶體中的上述第垂触广心 -資料時,則將儲存於上述第= = 5存上述第 製到一第三邏輯區塊。 $粗區塊中的弟一資料複 統之管理二:專^乾圍第1項所述之適用於快閃記憶體系 理ΐ,己憶體的方法,其中,使用輸入/輸出震置 存取弟料的步寫入上述第一資料。 播夕11!請專利範圍第2項所述之適用於'陕閃記憶體系 擬記憶體的方法,其中,當上述緩衝器中有上 St二5,儲存上述第一資料時,則存取上述第一邏 區:。…V驟係用以將上述第一資料寫入到上述第^邏輯 第11頁 0746-8150twf(nl);910009-0-tw;j〇anne.ptd 1295774 、、申請專利範圍 ____ 4·如申請專利範圍第彳 統之管理虛擬記情體的^1項所述之適用於快閃記憶體系 。管理虛擬記憶二=,所:之適,於快閃記憶體系 邏輯區塊儲存上述 ;::U緩衝器中有上 上述第-=塊 上述第一邏 -於入/V理虛擬記憶體的系統,包括, 輪入/輪出裝置,用以存料. ~緩衝器,且有籍盤、鹿弟貝枓, 區塊中複製而得H· U區塊,用以儲存由複數實體 =記憶體’具有複數實體區: 叛出叙置之間的資料存取; 、表衡态μ及 /、中’右缓衝器中有一繁一、s結厂 ;時,則操作系統存取上述;一;;=儲存上述第-資 有ΐ述第一邏輯區塊儲存上述第一資料栌,右緩衝器中沒 ;弟:邏輯區塊之異常旗標被致能;上二::判斷是否有 弟ΐ邏輯區塊的第二資料更新成上述,=知作系統將上述 塊;_在上述快問記憶體中是ΐϊ'體【的一第 =儲存上述第-資料,若快閃記憶體第-實體 =龙儲存上述第一資料時,則上述操作系t述第一實體 十之上述第一實體區塊所儲存的上述第一快閃記憶體 弟三邏輯區塊’並且更新上述第三邏二區:料’複·到一 TOM 第12頁 〇746.8150twf(nl);91〇〇〇9.〇.tw;J〇anne.ptd 1295774 六、申請專利範圍 7其= :固第6項所述之管理屋擬記二 係用以寫入上述第—資料。 于取弟〜資 統 二:申請專利範園第7項所述之管理虛 若上述緩衝器中有上述第 公,體的系 入上述第一邏輯區塊。 、輯£塊,係用以寫 請專利範園第6項所述之f 己 ΐ用以巧㈣系統利用輸入/輪出裝置存:Γί 係用以碩取上述第—資料。 弟一貝 統 第 如申請專利範圍第9項所述之管理虛擬 ί:’若亡述緩衝器中有上述第-邏輯區塊 取上二二,則插作系統存取上述第一邏輯區塊,传‘以二 取上述第一邏輯區塊。 係用以讀City 5774 Sixth, the scope of application for patents 1 · A suitable for the flash memory system silk field, including the following steps: , g virtual memory of the input / wheel device, access to resources, using an operating system to judge Bay/bucket, and save the first data; whether there is a logical block in the nail, although there is a first-logo-shoulder in the buffer, accessing the first logical block; °°Long stores the first When there is no logic in the buffer, it is judged whether there is - the second logical block ^ = the above-mentioned first data, the second data of the second logical block is written = the flag is enabled; a second entity Blocking; writing back to the above-mentioned flash memory, breaking the above-mentioned first flash data in the flash memory; and μ having a first physical block storing the above-mentioned droop in the above flash memory When the touch is wide-data, it will be stored in the above == 5 to store the above-mentioned third to the third logical block. The management of the data in the coarse block: the management of the data in the coarse block: the method described in Item 1 for the flash memory system, the method of recalling the body, in which the input/output is used for access The steps of the younger brother are written in the above first data.夕夕11! Please apply the method described in item 2 of the patent scope to the memory of the Shaanxi flash memory system, wherein when the above buffer has an upper St 2 and 5, the first data is stored, then the above is accessed. The first logical area: ...V is used to write the first data to the above-mentioned first logic page 11 0746-8150twf (nl); 910009-0-tw; j〇anne.ptd 1295774, the scope of patent application ____ 4 · Applicable to the flash memory system as described in item 1 of the management virtual case of the patent application scope. Management virtual memory two =, the appropriate: in the flash memory system logic block storage of the above;:: U buffer in the above-mentioned first - = block above the first logic - in / / logical memory system , including, wheeled/rounded device for stocking. ~Buffer, and has a home plate, Ludi Bellow, H.U block copied in the block for storage by complex entities = memory 'has a plurality of physical areas: data access between the treason and the narrative;; the balance state μ and /, the middle 'right buffer has a complex, s-factory; when, the operating system accesses the above; ;;=Save the above-mentioned first-status description of the first logical block to store the first data, no in the right buffer; brother: the abnormal flag of the logical block is enabled; the second two:: determine whether there is a brother The second data of the logical block is updated to the above, = the system is known to be the above block; in the above-mentioned fast memory, the first part of the memory is stored as the first data, if the flash memory is - When the entity=the dragon stores the first data, the operation is performed on the first physical block of the first entity ten. The first flash memory brother's three logical blocks' and update the above third logic two area: material 'complex to a TOM page 12 〇 746.8150twf (nl); 91 〇〇〇 9. 〇. tw; J 〇anne.ptd 1295774 6. Patent application scope 7: = The management house plan described in Item 6 is used to write the above-mentioned data. In the case of the younger brother, the application is as described in item 7 of the Patent Park. If the above-mentioned metric is in the above buffer, the above-mentioned first logical block is incorporated. The block is written for the purpose of writing the patent described in item 6 of the patent garden. The system uses the input/round-out device: Γί is used to obtain the above-mentioned data. The first management of the first virtual block is as follows: if the above-mentioned logical block is taken over by the second logical block, the system is accessed by the system. Passing 'takes the first logical block above. Used to read 0746-8150twf (nl) *,910009-0- tw; j oanne. ptd 第13頁0746-8150twf (nl) *,910009-0- tw; j oanne. ptd第13页
TW92113022A 2003-05-14 2003-05-14 Method and system for managing virtual memory TWI295774B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92113022A TWI295774B (en) 2003-05-14 2003-05-14 Method and system for managing virtual memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92113022A TWI295774B (en) 2003-05-14 2003-05-14 Method and system for managing virtual memory

Publications (2)

Publication Number Publication Date
TW200424853A TW200424853A (en) 2004-11-16
TWI295774B true TWI295774B (en) 2008-04-11

Family

ID=45068538

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92113022A TWI295774B (en) 2003-05-14 2003-05-14 Method and system for managing virtual memory

Country Status (1)

Country Link
TW (1) TWI295774B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI406128B (en) * 2008-04-18 2013-08-21 Silicon Motion Inc Non-volatile memory apparatus and method for accessing a non-volatile memory apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI406128B (en) * 2008-04-18 2013-08-21 Silicon Motion Inc Non-volatile memory apparatus and method for accessing a non-volatile memory apparatus

Also Published As

Publication number Publication date
TW200424853A (en) 2004-11-16

Similar Documents

Publication Publication Date Title
JP4005142B2 (en) Flash memory mass storage system
AU2007239066B2 (en) Describing and querying discrete regions of flash storage
US8095726B1 (en) Associating an identifier with a content unit
US10452562B2 (en) File access method and related device
US7096342B2 (en) Flexible LUN/LBA interface for content addressable reference storage
CN105190571B (en) Page table data management
US20160070501A1 (en) Method and system for automatically preserving persistent storage
TW200900930A (en) Hierarchical immutable content-addressable memory processor
US20060149902A1 (en) Apparatus and method for storing data in nonvolatile cache memory considering update ratio
JPH05210637A (en) Method of simultaneously controlling access
JPH08328762A (en) Semiconductor disk device and memory management method thereof
JP2015515047A (en) Method and apparatus utilizing non-uniform hash function to place records in non-uniform access memory
KR20070024573A (en) File Management Methods for Optimal Performance
TW589530B (en) Method and apparatus for physical address-based security to determine target security
US20090164738A1 (en) Process Based Cache-Write Through For Protected Storage In Embedded Devices
US7051251B2 (en) Method for storing data in a write-once memory array using a write-many file system
TWI237759B (en) Method for data accessing in a computer and the computer thereof
JP5062909B2 (en) Copy files from one directory to another
CN107577492A (en) The NVM block device drives method and system of accelerating file system read-write
TWI295774B (en) Method and system for managing virtual memory
TWI359377B (en) System and method for providing execute-in-place f
US6928511B2 (en) Method and system for managing virtual memory
US8909875B1 (en) Methods and apparatus for storing a new version of an object on a content addressable storage system
JP2005196793A (en) Method, system and product for reserving memory
JP2013109404A (en) Information processing device

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent