TWI250831B - Circuit board structure and method for fabricating the same - Google Patents

Abstract

A circuit board structure and a method for fabricating the same are proposed, wherein a core substrate formed with a metal layer on surfaces thereof and a plurality of plated through holes therein is provided. A conductive layer is formed on the surface of the terminal portions of the plated through holes, and a patterned circuit layer is formed on the core substrate by patterning the metal layer. A conductive film and a first resist layer are formed on the circuit layer, wherein a plurality of openings are formed in the resist layer to expose the conductive film and at least an opening is formed corresponding to the terminal portion of the plated through hole. Then, the conductive film which isn't covered by the first resist layer is removed and a second resist layer is formed to cover the conductive film remaining in the opening of the first resist layer. A third resist layer is formed to cover the opening excluding the plated through hole and a metal layer is formed on the plated through hole exposed to the second resist layer for an electrical connection pad by an electroplating process. Moreover, the third resist layer is removed and a protective metal layer is formed on the electrical connection pad of the core substrate by an electroplating process.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to an electroplated via structure for electrically connecting upper and lower circuit layers in a circuit board. Circuit board structure and its method of manufacture. [Prior Art]

Ik is booming in the electronics industry, and electronic products are gradually entering the trend of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the circuit J carrying the semiconductor chip is gradually formed by the double-layer board. It evolved into a multi-layer board (Muiti iayer b〇ard), and in a limited space, 'Interlayer fonnec^ion' is used to expand the available circuit layout area on the board, = must match the two high line density The integrated circuit needs to be accommodated under the same board unit (four)? The number of lines and materials: should be: high-performance chips such as processors, chipsets and graphics chips! The board also needs to improve its pass-through signal... bandwidth, η 士 寻 35, to achieve a high 1 / 0 number. = light and short, multi-function 35, high speed and high-frequency opening direction, the circuit board has been oriented to the thin line and the road board process from the traditional 100 micron line to display the existing electricity ...), the line spacing is one and deep; 3 ◦ micron below, and continue to face smaller (two, two =

17660 懋.ptd Page 11 1250831 V. Invention Description (2) In order to improve the precision of the wiring of the circuit board, the operation (Bui Id-up), that is, on the surface of a core Boar^i) ^ The layer is electrically connected to the upper and lower layers of the conductive blind vias in the insulating layer. Among them, the key to the density of the road board is to make a multilayer circuit board according to the current situation. Referring to Figures 1A to 1c, the _ additive Pr〇cess, SAP) line is added to the core circuit board 1 〇, and a laser drilling technique is formed on the surface to connect the core circuit board to the insulation. 1 内 Inner layer line Next, a pattern line is formed on the insulating layer 1 1 by applying a graph on the seed layer 13 with an electroless gold layer 13 ′ to form a pattern line on the surface of the 5 layer. Thereafter, the resist layer 14 is peeled off and the seed layer 13 under the etching layer 14 is formed (as shown in FIG. 1C, the insulating layer and the build-up wiring layer are repeatedly formed, and the circuit board is formed.) A multilayer circuit board (Core circuit stacking multiple layers of insulation and conductors for the line-growth system) affects the electrician's multi-νλ ~ layer process semi-additive method (Semi_ layer process, first, provide _ insulation The layer ill uses the laser layer 11 to form an opening 11 and a drill layer ( 2 (as shown in Fig. U). The steel form forms a plug-in resist layer "backward; |; the seed layer 15 (as shown in the figure: In order to remove the previous coverage of the resistance, such as the use of such I--with multi-layer lines, the conventional multi-drawer electronic signal produced by the layering method is to be transmitted from the board to the lower layer. & Θ €路板, 续续Η '呑海讯缺高增层层层层,上线层层< 邕雷死^ Court must be from V冤目孔,路路层层层, and then pass through The core of the core circuit board (Plated through hole, ΡΤΗ), core 1 money through hole box Bu layer green road layer,

17660 全懋.ptd 12th tribute !25〇831 V. Invention description (3) —— The conductive blind hole between the layer of the I-added circuit layer and the lower layer of the added layer are in the lower layer of the circuit board. If the signal transmission path is too long, it may cause the inductance to increase, resulting in: Cross-talk or noise, which will damage the electrical transmission. In addition, since a plurality of plated via holes are formed in the core circuit board, and the patterned circuit layer is formed on the build-up circuit layer formed on the core circuit board and the lower surface, the connection must be extended from the plated via hole. ^) Two, to form a conductive via, which not only wastes the wiring area of the board, is not conducive to miniaturization of the package trend, but also affects the board position due to the flashing of the via hole position during the line layout; Flexibility. Furthermore, if a conductive blind hole is formed directly on the plating via hole, if a conductive blind hole is to be directly formed on the plating via hole, a metal layer is formed on the surface of the entire circuit board having the plating via hole. And subsequently forming a conductive blind hole on the via hole of the key, so that a metal layer of sufficient thickness is formed on the resin of the poor hole of the through hole to avoid == in the process, the gold j layer is plugged with resin The effect is cracking or even separation,: 'Because the gold-sensitive layer is formed on the entire surface of the board at the same time, ^ is too thick or uneven thickness due to the thickness of the metal 钵: by, for example, a patterning process, Forming a conductive line and knowing the accuracy of the board, and can not form a tight connection, because the area of the integrated circuit (IC) can be reduced, and the ancient parts, the characteristics of the two-legged features have been tough, /, Axiong, degree and multi-route board process possession" two: = =

17660 Full 懋.ptd Page 13 1250831

For: When the same size as the chip ^ $ j- , ,, is only 1 _ 2 times of the wafer, how to develop a fine line that can be imaginary (Finp · • with t > 如玎士J 》) Not related to Clrcult) and the circuit board of South Line Density, this is undoubtedly an important research and development topic for the semiconductor industry and other "generation"-generation technology. In view of the above-mentioned conventional technology, it provides a circuit board structure and The electrical connection is formed on the system, and the electric circuit has a fine circuit structure. The other object of the invention is to reduce the conductive blind hole wiring space and form a better electrical distance. - the purpose is to shorten the signal transmission path to improve the electrical quality of the circuit board in one step. Another object of the present invention is to increase the layout of the circuit board layout to achieve the above and other purposes. The method comprises the steps of: providing a core layer, and forming a plurality of key contacts to form a conductive layer on the surface of the via hole to form a patterned layer; Forming a conductive film; in the conductive defect, the main purpose of the present invention is to directly supply a circuit board structure and a method thereof to the remaining electrical connection end of the plated via circuit board, and to provide the conductive blind hole plating layer The relationship between the circuit board structure and its manufacturing method avoids the generation of _ disturbances and noises, and provides a circuit board structure and its manufacturing area, and improves the interlayer circuit (flexibility. The present invention discloses a half circuit board junction board. The surface of the core plate has a metal hole; the electric circuit of the 6-core core plate is formed; the gold of the surface of the patterned S-core plate forms a first patterned resist layer on the core film of the patterned circuit structure.

17660 全懋.ptd page 14 1250831 5. Invention description (5), by forming a plurality of openings to reveal a portion of the conductive film, wherein at least one opening corresponds to the end of the plating via; a conductive film covered by the first patterned resist layer; forming a second patterned resist layer on the core layer to cover the conductive film remaining in the opening of the first resist layer; Forming a third resist layer on the opening to cover the opening outside the plating via; performing an electroplating process to form a metal layer on the end of the conductive via of the second pattern resist. Thus, a metal layer for subsequent electrical connection is selectively formed on a portion of the plated via. Thereafter, the third resist layer is removed, and an electroplating process is performed to form a metal protective layer on the surface of the electrical connection end (the metal layer including the end of the plated via hole), and then the second layer is removed. a first patterned resist layer and a conductive film covering the underlying conductive film, and then a patterned solder resist layer is formed on the core layer of the surface on which the patterned trace is formed, and a portion of the metal protective layer on the surface of the electrical connection end is exposed . That is, through the above process, the present invention firstly covers the region where the patterned thin line is formed by using the resist layer, and then selectively forms a metal layer at the end portion of the partially plated via hole without affecting the circuit board layout space and the fine line. The process can be further applied in the line build-up process, and the electrical connection end formed on the plated via hole is used to reduce the setting of the electrical connection end required for receiving the conductive blind hole and the circuit occupied by the wire. Board space, which effectively increases the density of line wiring. In addition, the present invention also discloses a circuit board structure, which comprises: a core layer having a patterned circuit and a plurality of plated through holes extending through the core plate, wherein at least one electrical connection is formed. End shape

1766Q 全懋.ptd Page 15 1250831 V. Description of the invention (6) In the electroplated via hole, the electrical connection end on the through hole: the protective layer is covered on the electricity and the side; And a pattern rejection::, above the sexual connection::, and at least - the opening is exposed outside the opening of the electrical ΐ:;, can be dreamed by #; ^ @ J should Hai electric mine through hole end Ray w ί Ϊ Protective layer: to effectively adhere to the electrical connection::: layer. The "strong" metal can be a multi-layer circuit board that completes the front-end process. ', the forbearing laminate is thus 'by the circuit board structure of the present invention and the part of the electroplating that is to be formed into an electrical connection." In the meantime, hunting to increase the density and flexibility of the wiring line can shorten the conductive path and reduce the inductance, crosstalk and noise generation; in addition, the electrical connection on the plating via is independent in the process, and not The process of affecting the remaining electrical connection ends of the circuit board and the conductive lines; the end: for subsequent connection with conductive elements, providing the electrical connection; the electrical conduction of the electronic 7G piece (semiconductor chip or circuit board) Alternatively, a conductive via of a line build-up structure may be formed on the electrical connection end of the plating via to reduce the space required to extend the connection pad when the conductive hole is formed. In order to increase the density and flexibility of the wiring, and to shorten the conductive path, reduce the inductance, crosstalk and miscellaneous paint. In order to avoid the need to form an electrical connection on the plated vias in the prior art, it is necessary to be in the overall circuit. Forming a metal layer having a thickness that is too thick or uneven in thickness causes a defect in the subsequent formation of a conductive line and an electrical connection end in the patterning process, and cannot form a circuit board or the like with a fine line structure, and is provided A circuit board structure with a fine circuit and a high wiring density.

1766G Full 懋.ptd Page 16 1250831 V. Description of the Invention (7) [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific embodiments, and those skilled in the art can easily disclose the contents disclosed in the present specification. Other advantages and effects of the present invention are understood. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the circuit board structure of the present invention and a method of manufacturing the same will be described in detail with reference to Figs. 2A to 2B. It should be noted that these drawings are simplified schematic diagrams, and only the circuit board architecture of the present invention is illustrated in a schematic manner. However, the drawings only show the components related to the present invention, and the components shown therein are not in actual implementation, and the actual number of components, shape and size ratios in actual implementation is a selective design, and the components thereof. The layout type can be more complicated. As shown in Figures 2 and 2, first, a core layer 20 having a thin metal layer formed thereon may be provided, and the core layer 20 may also be a multilayer circuit board which has been pretreated. In the embodiment of the present embodiment, the core layer 20 is composed of an insulating layer 200 and a thin metal layer 20 formed on the surface of the insulating layer 2000; a mechanical or laser drill is used. A plurality of through holes 2 0 2 are drilled into the core layer 20 in a manner such as a hole (as shown in FIG. 2B). Wherein, the insulating layer 200 can be an epoxy resin, a polyimide, a Cyanate Ester, a glass fiber, a bis-succinimide/trinitrogen Well (B isma 1 eimide T riazine, Β T ) or mixed epoxy resin and glass fiber FR5 material, the metal thin layer 20 0 is generally better in conductivity

17660 全懋.ptd Page 17 1250831 V. Description of the invention (8) Copper (C u ) is mainly used as the wire material for signal transmission, and the thin metal layer 2 0 1 can be pressed or deposited on the insulating layer first. It is made by using Resin coated copper (RCC) on 2000. This embodiment is described by taking a resin laminated copper foil (RCC) as an example. As shown in Fig. 2C, next, by physical vapor deposition (P VD ), chemical vapor deposition (CVD), electroless plating, or chemical deposition, etc. 'such as sputtering, evaporation, arcing Arc vapor deposition, I〇n beam sputter ing, La ser ab 1 ati on deposition, electric paddle-promoted chemical vapor deposition or no electric key A conductive layer (not shown) is formed on the surface of the core layer 20 and the through hole 220, and the conductive layer is used as a current conduction path on the surface of the core layer 20 and A metal layer 203 having a sufficient thickness is formed by a key on the wall of the through hole 2 〇2. As shown in FIG. 2D, the through hole 2 0 2 is filled with a filler material (such as an ink resin), and a conductive via hole (PTH) 2 0 5 is formed, thereby electrically conducting the core. The metal layer of the upper and lower surfaces of the layer 20 is 2 0 3 . Next, a conductive layer is formed on the surface of the end portion of the electroconductive via hole 20 5 which exposes the core layer 2 . It can perform a direct plating (DP) process on the anger layer plate 20 to form a conductive film 20 3a such as palladium (Pd) on the surface of the anger layer plate, and then chemically Stripping the process so that the palladium metal layer is attached to the end surface of the filling material 220 of the plating via hole 205, or is made of a chemical copper or the like, so that the bonding material of the keyhole 2 0 5 is filled. 2 04 end surface is covered with a conductive film 20 3a; in addition, as shown in Figure 2D'

17660 懋.ptd 1250831 V. Description of the Invention (9) It is also possible to form a conductive layer (not shown) on the surface of the core layer 20 by electroless plating or the like, and the conductive layer is used as a current conduction. a path for electroplating to form a conductive thin layer 2 1 such as copper (Cu) on the surface of the core layer 20 (the end portion of the filling material 220 including the plating via hole 205) (the thickness is usually 3) To 1 0// m). The conductive thin layer 21 or the conductive film 203a' formed on the end surface of the filling material 204 of the plating via hole 205 is mainly used as a current conduction path, and is selectively conductive in the subsequent plating process. A plated metal layer is formed on the hole 250. The following description of the subsequent process is mainly to form a conductive film 2 0 3 a which can be formed, for example, of palladium or copper, on the core layer 20, and at the end of the filling material 2 0 4 of the plating via hole 200. Covering a method of electroplating copper, the subsequent process mode is similar to the process steps described below, and therefore will not be further described herein, and will be described first. As shown in Fig. 2E, the metal layer on the surface of the core sheet is patterned to form a patterned line. A resist layer (not shown) such as a dry film or a photoresist may be formed on the core layer 20, and subjected to exposure, development (D eve 1 〇pment), etc., so that the resistance The layer is formed with a plurality of openings to expose the surface metal layer of the core layer 20, and the etch process is performed to remove portions of the metal layer not covered by the resist layer, thereby forming a patterned line 2 2 such as 2F As shown in the figure, a conductive film 23 is formed on the core layer 20 of the patterned circuit 2 2 , and the conductive film 23 is mainly used as a current conduction path for plating a metal layer, which may be metal, alloy or The plurality of metal layers are stacked and formed of a group of metals selected from the group consisting of copper, tin, copper, titanium, and copper-chromium alloy. The conductive film 23 can be deposited by physical vapor deposition

17660 懋.ptd Page 19 1250831 V. Description of invention (10) Forming (PVD), chemical vapor deposition (CVD), electroless plating or chemical deposition, etc., such as sputtering (Sputtering), evaporation (Evap〇) Rat ion), arc vapor deposition, ion beam sputtering, laser, laser ablation deposition, plasma-assisted chemical vapor deposition or electroless plating form. However, in accordance with practical experience, the conductive film 23 is preferably composed of copper-free copper particles. As shown in FIG. 2G, a first patterned resist layer 24 ′ is formed on the conductive film 23, so that the resist layer 24 is formed with a plurality of openings 240 to expose the patterned line 2 2 . The terminal portion is electrically connected, and at least one of the resist layer openings 240 selectively exposes the end of the plated via hole 2 〇5. The resistive openings 240 are used to expose portions of the electrical connections that are subsequently used as circuit boards. The edge resist layer 24 can be a dry film or a photoresist for use as a plating resist layer in subsequent electrical clock processes. As shown in Fig. 2, the portion of the conductive film 23 that is not covered by the first patterned resist layer 24 is removed. As shown in Fig. 2I, a second patterned resist layer 25' is formed on the core layer to cover the conductive film 23 remaining in the opening of the first resist layer. As shown in FIG. 2J, a third resist layer 2 6 is formed on the core layer 2 以 to cover the first patterned resistive opening 2 4 0 outside the plating via 2 〇 5, and And performing a plating process to form a metal layer on the end portion of the plating via hole 205 which exposes the second patterned resist layer 25, so that a portion of the plated via hole 2 〇5 can be selectively formed directly. The subsequent function is a metal layer of the electrical connection terminal 27. Among them, because the plating metal layer is only

17660 escort.ptd Page 20 1250831 V. Invention Description (11) Selectively formed on part of the plating via 2 〇5, so in addition to being formed on the electric forging via 20 5, at the same time A patterned thin line is formed on the remaining area of the core board. As shown in FIG. 2K, after the electrical connection end 27 is formed on the plating via 2 〇 5, the third resist layer 26 can be removed, and the patterned line on the surface of the core board can be removed. A portion of the electrical connection terminal 2 2 显 is exposed to the first patterned resistive layer opening 240. As shown in FIG. 2L, an electroplating process is performed to form a metal protective layer 2 8, such as nickel, on the surface of the electrical connection end 27, 2 2 显 in the first patterned resistive layer opening 220. The metal metal layer can be electrically connected to the conductive component (such as a bonding wire, a solder ball, or a metal bump, etc.) by the metal protective layer 28. As shown in FIG. 2M, the second patterned resist layer, the first patterned resist layer, and the conductive film covering the underlying conductive film are removed, and then a patterned solder resist layer 29 is formed to expose the electricity. The surface of the connecting ends 27, 221 is divided into a metal protective layer 28. In addition, the second Μ ' diagram, which is as shown in the previous 2nd D, is shown on the surface of the core layer 20 (including the end of the filling material 2 〇 4 of the plating via 2 〇 5) When a conductive thin layer 21 such as copper (Cu) is formed, a metal layer for selectively acting as the electrical connection end 27 is selectively formed on the partially-plated via hole 2〇5 via the foregoing process, and is electrically connected. 27 The surface is formed with a metal protective layer 2, which is made of a circuit board structure. As shown in Figures 2M and 2M', through the foregoing process, the present invention also discloses a circuit board structure which comprises a core layer and is reversed, and has a surface formed thereon.

1250831 V. Description of the Invention (12) The case circuit 2 2 and a plurality of plated vias 205 extending through the core plate 20, and at least one of the electrical connection ends formed on the plated vias 205 a protective layer 28, which is coated on the upper surface of the electroplated via hole 220 and the upper surface and the side of the remaining electrical connection end; and one, f = reject I dry layer 2 9, formed on the surface of the core layer, such that the solder resist 1 is formed into a plurality of openings to expose the electrically conductive 21 of the patterned line 2 2 and at least one opening corresponds to the plated via 2 0 5 end layer 28, 'connecting end, to strengthen the metal protective layer 28 by the portion of the metal protective end 27 covered by the solder resist layer 29 to effectively adhere to the electrical connection cover: The upper surface of the electrical connection end 27 of the electric inlet via 200 is connected to the metal protective layer 28 of the crucible, the crucible, and the remaining electrical connection end - the germanium layer 29. . The patterned circuit structure of the protective layer 28 forms a solder-resisting end portion to form a mountain as shown in FIG. 1, and the y is in the electric money conducting hole 305 3 1 in the anger layer 30 to receive the conductive hole 32 for the end, two It can also be used as a follow-up line to form a conductive structure on the 増 layer structure, and the 俾 can be directly connected to the galvanic via 305. Thus, the conductive blind hole 32 can be reduced to reduce the electrical connection: Electricity: 匕32 electric and effective i secret t between short and short conductive i-m, male and 曰 曰 线路 line layout space, upgrade 绦玖 && + electric U work re-sustainable who > say & The secret M system is zoomed out, the spring road layout is activated, and then, the circuit board structure. One has a multi-layer circuit structure. Further, although the previous drawings of the present invention are described by 雔 M and a laminate, the present invention

Page 22 1250831 V. Description of the Invention (13) The process of the invention can also be applied to a multi-layer board, that is, the core layer board of the previous figure can be a multi-layer board which has completed the front-end process, and can be formed according to the foregoing process. A circuit board structure having a multi-layer circuit structure, as shown in FIGS. 4A and 4B, is a circuit board 40 A having a four-layer circuit structure obtained by applying the foregoing process of the present invention, and a circuit board 4 having a six-layer circuit structure. 0 B. Of course, the application of the present invention is not limited to the aforementioned two-layer, four-layer, or six-layer circuit boards, and can be applied to any circuit board having a multi-layer circuit structure. Therefore, with the circuit board structure of the present invention and the method of manufacturing the same, the electrical connection end can be selectively formed on a portion of the plated via hole for forming the electrical connection end for subsequent connection of the conductive element to provide the circuit board. Electrically conductive connection with other electronic components (semiconductor wafers or circuit boards), or conductive bead holes formed on the electrically conductive connection ends of the electroplated vias, and the formation of conductive blind vias (C ο nductivevia), it is necessary to extend the space of the connection pad (Pad), thereby increasing the wiring density and flexibility, and shortening the conductive path, reducing inductance, crosstalk and noise generation; in addition, the plating via hole The electrical connection ends are formed independently in the process, without affecting the process of the remaining electrical connection terminals and the conductive lines of the circuit board, so as to avoid the formation of electrical connection terminals on the electric conduction vias in the prior art. It is necessary to form a metal layer having an excessive thickness or an uneven thickness on the entire circuit board, resulting in the subsequent formation of a conductive line and an electrical connection terminal in the patterning process. , Deleted and can not form a fine wiring structure, etc., serve to provide a fine line (F i n e C i r c u i t) and high-density wiring circuit board construction. The above description is only the preferred embodiment of the present invention, and is not intended to be limiting.

17660 懋.ptd Page 23 1250831 V. OBJECT DESCRIPTION OF THE INVENTION (14) The technical scope of the present invention is defined by the technical scope of the present invention, which is broadly defined in the following claims, any technical entity completed by others or The method of the present invention is to be construed as being the same as the scope of the claims.

17660 全懋.ptd Page 24 1250831 Schematic description of the drawing [Simple description of the drawing] Figure 1A to Figure 1C is a schematic diagram of the fabrication process of the circuit board structure of the conventional semi-additive method; 2A to 2M BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2D' and 2M' are schematic cross-sectional views showing another embodiment of the circuit board structure manufacturing method of the present invention; FIG. 3 is a circuit board structure manufacturing method of the present invention. A schematic cross-sectional view applied to a build-up structure; and FIGS. 4A and 4B are schematic cross-sectional views of a circuit board structure method of the present invention applied to a multilayer board. 10 core circuit board 11 insulation layer 110 opening 12 inner layer circuit layer 13 seed layer 14 resistance layer 15 patterned circuit layer 2 0 core layer 2 0 0 insulation layer 201 metal layer 2 0 2 through hole 2 0 3 metal layer

17660 全懋.ptd Page 25 1250831 Schematic description 2 0 3 a Conductive film 2 0 4 Filler 2 0 5 Plating via 21 Conductive thin layer 22 Patterned line 221 Electrical connection end 23 Conductive film 2 4 Resistive layer 24 0 Resistive layer opening 25 Resistive layer 2 6 Resistive layer 27 Electrical connection end 2 8 Metal protection layer 29 Repellent layer 30 Core layer 3 0 5 Plating via 31 Line buildup structure 32 Conductive blind hole

17660 Full 懋.ptd第26页

Claims (1)

1250831 6. Patent application scope 1. A method for manufacturing a circuit board structure, comprising: providing a core layer having a metal layer on the surface thereof and forming a plurality of plated through holes; thereby exposing the core layer Forming a conductive layer on the surface of the end of the plating via; patterning the metal layer on the surface of the core layer to form a patterned circuit; forming a conductive film on the core layer of the patterned circuit; forming a conductive film on the conductive film a first patterned resist layer, wherein a plurality of openings are formed to expose a portion of the conductive film, wherein at least one opening corresponds to an end of the plating via; the removal is not covered by the first patterned resist layer a conductive film; a second patterned resist layer is formed on the core layer to cover the conductive film remaining in the opening of the first resist layer; and a third resist layer is formed on the core layer to cover An opening other than the plating via; and an electroplating process to form a metal layer on the end of the plating via exposing the second patterned resist layer as an electrical connection port 2. The method of fabricating a circuit board structure according to claim 1, wherein the conductive layer on the surface of the end of the plating via is formed by direct plating (DP). 3. The method of fabricating a circuit board structure according to claim 1, wherein the inside of the plating via is filled with a filler. 17660 懋.ptd Page 27 1250831 VI. Patent Application Range 4. The method of manufacturing a circuit board structure according to claim 1, wherein the conductive layer on the surface of the end of the plating via is formed by chemical deposition. 5. The method of fabricating a circuit board structure according to claim 4, wherein the conductive layer on the surface of the end portion of the plating via is made of one of copper and palladium. 6. The method of fabricating a circuit board structure according to claim 1, wherein the surface of the core board is formed by using the conductive layer as a current conducting path to form a conductive thin layer on the surface of the core board. 7. The method of fabricating a circuit board structure according to the first aspect of the invention, wherein the conductive layer on the surface of the end portion of the electric forging via hole is formed by using no electric key. 8. The method of fabricating a circuit board structure according to claim 1, wherein the core layer is a resin laminated copper foil (RCC). 9. The method of fabricating a circuit board structure according to claim 1, wherein the core board is a multilayer circuit board that completes the front stage process. The method of manufacturing the circuit board structure of claim 1, wherein the metal layer on the plating via serves as an electrical connection terminal, which is selectively formed on the partially plated via hole and is pre-utilized. The resist layer covers the area where the thin lines are formed without affecting the process of the remaining line layout space and fine lines. 1 1. The method for manufacturing a circuit board structure according to claim 1 or 10, wherein the electrical connection end can be used as a circuit board for subsequently connecting conductive elements. 17660 全懋.ptd Page 28 1250831 VI. Patent Application Range 1 2. For the method of manufacturing the circuit board structure of claim 1 or 10, wherein the electrical connection end can be used as a subsequent line build-up structure. For conductive blind holes, 俾 can form conductive blind holes on the plated vias to shorten the conductive path, increase the wiring space, and improve the layout flexibility. 1 . The method of manufacturing a circuit board structure according to claim 1 or 10, further comprising: removing the third patterned resist layer and performing an electroplating process to form a metal on a surface including the electrical connection end; a protective layer; removing the second, first patterned resist layer, and a conductive film covering the underlying layer; and forming a patterned solder resist layer on the core layer of the surface on which the patterned trace is completed, thereby exposing the electrical property A portion of the metal protective layer on the surface of the connection end. A method of fabricating a circuit board structure according to claim 13 wherein the metal protective layer is a nickel/gold metal layer. The circuit board structure comprises: a core layer having a patterned circuit structure and a plurality of plated through holes penetrating the core plate, wherein at least one electrical connection end is formed on the plating a metal protective layer covering the upper surface of the electrical connection end of the electroplated via hole and the upper surface and the side of the remaining electrical connection end; and a patterned solder resist layer formed on the via hole The core plate surface, the rejection 17660 懋.ptd Page 29 1250831 VI. Scope of Application The solder layer is formed with a plurality of openings to expose the electrical connection of the gold protective layer. The circuit board structure of claim 15 wherein the core layer is a resin laminated copper foil (R C C ). The circuit board structure of claim 15, wherein the core board is a multilayer circuit board that completes the front stage process. 1 8 . The circuit board structure of claim 15 , wherein the electrical connection end can be used as a circuit board for subsequently connecting the conductive component. The circuit board structure of claim 15 wherein the electrical connection end of the plating via is selective to the partially plated via hole without affecting the process of the remaining patterned circuit structure. 2 0. The circuit board structure of claim 15 of the patent scope, wherein the electrical connection end can be used as a conductive blind hole in the subsequent line build-up structure to form a conductive blind hole on the conductive hole of the electric mine. In order to shorten the conductive path, increase the wiring space, and improve the flexibility of the line layout. 2 1. The circuit board structure of claim 15 wherein the metal protective layer is a nickel/gold metal layer. 17660 Full 懋.ptd第30页