I241674§4twf.doc/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電容結構，且 種具有三度空間之立體電極的電容結構。、&有關於一 【先前技術】 電容器是一種在積體電路中不可 ;器的設計與;程中’必須要考慮到電容器的 置面積’因此需要提出較佳的電容器設計與製程。” 單元動態隨機存取記憶體(DRAM)的記憶 早4通申％為,己憶胞，memory cell)，通常包括 以及用以儲存位元龍的電容器，以作為—個帥元:，— 其中藉由對在半導體基底上之電容器陣列中的每二電容哭 =擇性地充電或放電，便可達到儲存資料的目的。對ς 在固疋操作麵下工作的記㈣f容ϋ而言，其電極間距 及其介電質的介電常數JU定時，電容 ^ 曰 定電容器的電容值。 電極的表面積便決 睛參考SM，麟*為習知之—種平行板電容 。如圖丨所示’平行板電容結構刚包括— =、-下電極板120以及配置於上電袖ιι〇與 虽反12〇之間的一介電層13〇，其中上電極板ιι〇 極板120係相互平行並維持一間距d。習知此種付 ==〇〇係利用上電極板110與下電極板12〇之間所產 生的平灯電場來獲得所期望的電容值，亦即所 電容(parallel plate capadtance)。因此，平行板電容結構刚 Ι241674§— $電容值大小係正比於上電極板⑽與下電極板ΐ2〇之面 不斷長足進步’積體電路 構因Uti與高積集化發展’習知此種平行板電容結 的需求。換言之，以前述之動態隨機存取記憶體 二’右^用習知之平行板電容結構，勢必 ==?使用較大面積之上、下電極板，導賴存 儲存資料的錯i。如此一來’此電容值的減少將可能造成 古接2 ’如何在現行的積體電路製程中提出-種真有 二=;容=容結構，以娜電容所佔的平 容器性处^ Η Θ可有效增加電極的表面積，以提存電 fi明=二7疋目前積體電路設計中的首要課題。 以I本發明的目的就是在提供—種高性能之電容結構， 在相對較小的佈線空間内，產生較大之電容值。 基柄月的另一目的是提供一種電容結構，用以改善 板上的空間利用程度，進而提高電路設計之彈性。 其係其他目的’本發明提出一種電容結構， 、木構於-基板内。此電容結構包括多個電極組、至少 相互2電插塞以及至少一第二導電插塞，其中電極組係 哲並分別位於基板的不同層之中，且每一電極组包 -第-電極以及圍繞第一電極配置之一第二電極：此 I2416^g4twfdoc/c 外第^電插塞與第二導電插塞係配置於 中爾電極組内的第一電_相互二^ 電插塞而相互耦接，且兩相鄰電極組内的第二電 極係相互對應，並藉由第二導電插塞而相互編妾。 在本發明之-較佳實施例巾，上敎每—第一電極 例如是呈塊狀或環狀。此外，每—第二電極例如是呈環狀。 在本I月之較佳貫施例中，上述之每一電極組例 如更包括-第三電極，且這些第三電極係分別圍繞第二電 極配置。此外，每一第三電極例如是呈環狀。 在本發明之-較佳實施财，上叙基板例如包括 至少-介電層，其係配置於兩相鄰之電極組之間，而第一 導電插塞與第二導電插塞係位於此介電層内。 本發明更提出另-種電容結構，係架構於一基板内。 此電容結構包括多個電極組、多_—導電插塞以及多個 第二導電減，其巾電極組仙互對應並分顺於基板的 不同層之中’而每-電極組包括多個第—電極盘多個第二 電極，且第-電極與第二電極係相互交替而呈、一矩陣排 列。此外’第-導電插塞與第二導電插塞係配置於兩相鄰 電極組之間，其中兩相鄰電極組内之第—電極係相互對 應’並分別藉由第-導電插塞而相互_，且兩相鄰電極 組内之第一電極係相互對應，並分別藉由第二導電插塞而 相互輛接。 在本發明之一較佳實施例中，上述之每一第一電極 例如是呈塊狀。此外’上述之每一第二電極例如是呈塊狀。 12416器— ,ι、^發明之-較佳實施射，上述之基板例如包括 至V 電層’其係配置於兩相鄰之電極組之間，而第一 V電插塞與第二導電插塞係位於此介電層内。 在本發明之—較佳實施例中，上述之基板例如包括 -第-電源層，且第_電極係祕至第—電源層。此外， 基板例如更包括-第二電源層，且第二電極係祕至該第 二電源層。 基於上述，本發明係於多層基板内形成垂直之電容 結構’以期在三度空間的立體電極之間產生電場，而獲得 所期望的電容值。因此，藉由本發明之電容結構可在相對 1父小的佈線空_ ’產生所需之電容值，以有效節省基板 上的佈線空間，進而提高電路設計之彈性。 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 [第一實施例] 請參考圖2，其繪示本發明之第一實施例之一種電容 結構的立體示意圖，其中為清楚表示電容結構，圖2未繪 示完整之基板。如圖2所示，電容結構2〇〇係架構於一基 板(未繪示）内，此基板例如是半導體基板、電路板或其他 類型之線路基材。此外，電容結構2〇〇包括電極組21〇與 220、第一導電插塞252以及第二導電插塞254，其中電 極組210與220係相互對應並分別位於基板(未繪示）的不 12416¾ 4twf.doc/c 同層’在一實施例巾，電極組21〇與22〇例如是分別位於 基板内之一介電層（未繪示）的相對兩側。 ，再參考圖2 ’電極組21〇包括一第一電極212以及 ϋ電極212配置的—第二電極214 ’而電極組220 匕括一第—電極222以及圍繞第一電極222配置的一第二 ，極224 ’且第一電極212以及第二電極214係分別盘第 一電極222以及第二電極224才目對應。其中 组2 内㈣一電極犯與第二電極214係位於基板之同1層10 而可藉由同-道製程製作而成，因此可在圖案的對位上辞 =較精確之控制。同理，電極組22〇内的第一電極222 = =電極224亦可同時形成，而在製程上獲得較為精確的 控制。此外，第一導電插塞252係位於介電層（未緣示)内， f配置於第-電極212與222之間，以使得第一電極 :、222可藉由第一導電插塞252相互耦接。同理，第二導 $插塞254係位於介電層（未繪示⑽，並配置於第二電極 124之間’以使得第二電極214與224可藉由第二 導電插塞254相互耦接。 在本實施例中，第一電極212與222例如是呈塊狀， f措由第—導電插塞252相連接而構成柱狀之第-電極結 一 =72，且第二電極214與224例如是呈環狀，並藉由第 一、電插塞254相連接而構成圍繞第一導電構一 =電極結構274。其中，第一電極結構2二丄 ¥電插塞242麵接至下層之電源層262，而第二電極結 構274例如可向外或向上麵接至其他位置之電源層（未綠 12416欲— 示)，f在第一電極結構272與第二電極結構274之間產 生電場’進而提供所需之電容值。I241674§4twf.doc / c IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a capacitor structure and a capacitor structure having a three-dimensional three-dimensional electrode. &Amp; There is a [prior art] capacitor is a kind of device design and integrated circuit in the integrated circuit. In the process, we must consider the capacitor's area, so we need to propose a better capacitor design and manufacturing process. The memory of the unit's dynamic random access memory (DRAM) is 4% as early as the memory cell, which usually includes and capacitors to store the bit dragon as a handsome cell :, where The purpose of storing data can be achieved by crying for every two capacitors in a capacitor array on a semiconductor substrate, selectively charging or discharging. For the record of working under the solid operating surface, the The distance between the electrodes and the dielectric constant of the dielectric, JU, are used to determine the capacitance value of the capacitor. The surface area of the electrode is closely referenced to SM, and Lin * is a familiar one—a kind of parallel plate capacitor. The plate capacitor structure just includes — =, — the lower electrode plate 120 and a dielectric layer 13 disposed between the power-on sleeve ιι0 and the reverse electrode 120, in which the upper electrode plate ιιο electrode plate 120 is parallel to each other and maintained A distance d. It is known that this kind of payment == 〇〇 uses the flat lamp electric field generated between the upper electrode plate 110 and the lower electrode plate 120 to obtain the desired capacitance value, that is, the parallel plate capadtance. . Therefore, the parallel plate capacitor structure just 241241§— The value of the capacitor value is directly proportional to the surface of the upper electrode plate 电极 and the lower electrode plate ΐ20. The 'integrated circuit structure Uti and high integration development' are familiar with the needs of such parallel plate capacitor junctions. In other words, the The above-mentioned dynamic random access memory II 'uses a conventional parallel plate capacitor structure, which is bound to ==? Use a larger area of upper and lower electrode plates, which leads to the error i of stored data. In this way, this capacitor The decrease of the value may cause the ancient connection 2 'How to put forward in the current integrated circuit manufacturing process-there are two kinds of = = capacity structure, the flat container property occupied by the na capacitor ^ Η Θ can effectively increase the surface area of the electrode In order to save the electricity, it is the most important issue in the current integrated circuit design. The purpose of the present invention is to provide a high-performance capacitor structure in a relatively small wiring space. Capacitance value. Another purpose of the base handle is to provide a capacitor structure to improve the degree of space utilization on the board, thereby improving the flexibility of the circuit design. It is another purpose. 'The present invention proposes a capacitor structure. base The capacitor structure includes a plurality of electrode groups, at least two electrical plugs with each other, and at least one second conductive plug, wherein the electrode groups are respectively located in different layers of the substrate, and each electrode group includes-第- Electrode and one second electrode arranged around the first electrode: This I2416 ^ g4twfdoc / c outer electric plug and a second conductive plug are the first electric_two electric plugs arranged in the Zhonger electrode group ^ electric plug And they are coupled with each other, and the second electrode systems in two adjacent electrode groups correspond to each other, and are mutually knitted by the second conductive plug. In the preferred embodiment of the present invention, each of the first The electrode is, for example, a block or a ring. In addition, each of the second electrodes is, for example, a ring. In the preferred embodiment of this month, each of the above electrode groups, for example, further includes a third electrode, and these third electrodes are respectively arranged around the second electrode. In addition, each third electrode has a ring shape, for example. In the preferred embodiment of the present invention, the above-mentioned substrate includes, for example, at least a dielectric layer, which is disposed between two adjacent electrode groups, and the first conductive plug and the second conductive plug are located in this medium. Within the electrical layer. The invention further proposes another capacitor structure, which is structured in a substrate. This capacitor structure includes multiple electrode groups, multiple conductive plugs, and multiple second conductive sub-groups. The electrode groups of the capacitors correspond to each other and are arranged in different layers of the substrate. -The electrode plate has a plurality of second electrodes, and the first electrode and the second electrode are alternately arranged in a matrix. In addition, the "first conductive plug and the second conductive plug are arranged between two adjacent electrode groups, in which the first-electrode systems in the two adjacent electrode groups correspond to each other" and are mutually connected by the first conductive plugs, respectively. _, And the first electrode systems in two adjacent electrode groups correspond to each other, and are connected to each other by second conductive plugs, respectively. In a preferred embodiment of the present invention, each of the first electrodes is in a block shape, for example. In addition, each of the above-mentioned second electrodes has a block shape, for example. 12416 器 — ， ι ， ^ 发明 的-It is preferable to implement the above-mentioned substrate, for example, to the V electrical layer, which is disposed between two adjacent electrode groups, and the first V electrical plug and the second conductive plug A plug is located within this dielectric layer. In a preferred embodiment of the present invention, the aforementioned substrate includes, for example, a first power source layer, and the first electrode is from the first power source layer. In addition, the substrate further includes, for example, a second power source layer, and the second electrode is connected to the second power source layer. Based on the above, the present invention is to form a vertical capacitance structure 'in a multilayer substrate in order to generate an electric field between three-dimensional electrodes in a three-dimensional space, and obtain a desired capacitance value. Therefore, with the capacitor structure of the present invention, a required capacitance value can be generated in a relatively small wiring space, so as to effectively save the wiring space on the substrate, thereby improving the flexibility of the circuit design. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment] [First embodiment] Please refer to FIG. 2, which illustrates a schematic perspective view of a capacitor structure according to a first embodiment of the present invention. In order to clearly show the capacitor structure, FIG. 2 does not show a complete substrate. As shown in FIG. 2, the capacitor structure 200 is structured in a substrate (not shown). The substrate is, for example, a semiconductor substrate, a circuit board, or another type of circuit substrate. In addition, the capacitor structure 200 includes electrode groups 21 and 220, a first conductive plug 252, and a second conductive plug 254. The electrode groups 210 and 220 correspond to each other and are respectively located at 12416 of a substrate (not shown). 4twf.doc / c Same layer 'In one embodiment, the electrode groups 21 and 22 are, for example, located on opposite sides of a dielectric layer (not shown) in the substrate, respectively. Referring again to FIG. 2 'the electrode group 21o includes a first electrode 212 and a second electrode 214 configured with a rhenium electrode 212' and the electrode group 220 includes a first electrode 222 and a second electrode 222 disposed around the first electrode 222. The electrodes 224 'and the first electrode 212 and the second electrode 214 correspond to the first electrode 222 and the second electrode 224, respectively. Among them, the first electrode 214 and the second electrode 214 in Group 2 are located on the same layer 10 of the substrate and can be made by the same-channel process, so the pattern alignment can be controlled with greater precision. Similarly, the first electrode 222 == electrode 224 in the electrode group 22 can also be formed at the same time, and more precise control can be obtained in the manufacturing process. In addition, the first conductive plug 252 is located in a dielectric layer (not shown), and f is disposed between the first electrodes 212 and 222, so that the first electrodes: 222 can communicate with each other through the first conductive plug 252. Coupling. Similarly, the second conductive plug 254 is located in the dielectric layer (not shown) and is disposed between the second electrodes 124 so that the second electrodes 214 and 224 can be coupled to each other through the second conductive plug 254 In this embodiment, the first electrodes 212 and 222 are block-shaped, for example, f is connected by the first conductive plug 252 to form a columnar first electrode junction = 72, and the second electrode 214 and 224 is, for example, in a ring shape, and is connected by the first and electrical plugs 254 to form a first conductive structure = electrode structure 274. Among them, the first electrode structure 22 is electrically connected to the lower layer. Power supply layer 262, and the second electrode structure 274 can be connected to the power supply layer of other locations outward or upward (not green 12416) —f is generated between the first electrode structure 272 and the second electrode structure 274. The electric field 'in turn provides the required capacitance value.
[第二實施例J 成除了上述第一實施例之塊狀第一電極212與222以 及％狀第二電極214與224之搭配外，本發明之電容結構 的電極更可具有其他不同型態之設計。 —請參考圖3，其繪示為本發明之第二實施例之一種電 谷、^構的立體示意圖，其中為清楚表示電容結構，圖3未 繪示基板。如圖3所示，電容結構3〇〇係架構於基板内， 其中電極組310與320例如分別包括環狀之第一電極312 與322以及環狀之第二電極314與324，且第二電極314 與324例如分別圍繞第一電極312與322。此外，第一電 極312與322分別藉由第一導電插塞352與第導電 则_二電極3…4,以分別二成：f 極結構372與一第二電極結構374，其中第一電極結構372 與第二電極結構374可相互耦合，而提供所需之電容值。 值得一提的是，在本發明之其他實施例中，第一電 極之形狀更例如可以是圓形、條形、多邊形或其他形態， 而第二電極除可為上述之矩形環之外亦可為圓形環、多邊 形裱或其他形態，然其詳細結構與相關配置請參考上述實 施例，下文將不再重複贅述。 " [第三實施例] 請參考圖4，其繪示為本發明之第三實施例之一種電 容結構的立體示意圖。如圖4所示，電容結構4〇〇之電極 I2416^4twfdoc/c 組410與420除了具有第一電極412與422以及圍繞第一 電極412與422的第二電極414與424之外，更分別包括 第三電極416與426，其申第三電極416與426係分別圍 繞第二電極414與424。 二電極416與426係呈環狀，並藉由第三導電插塞456相 _ 互耦接，而構成一第三電極結構476。在本實施例中，第 一電極結構472與第三電極結構476例如更分別 插塞442與446 _至基板下層之電源層462，而第^ 極結構444例如可向上麵接至基板上層之電源層（未繪 承接上述，第一電極412與422係呈塊狀，並藉由 第一導電插塞452相互輕接，而構成一第一電極結構472。 此外，第二電極414與424係呈環狀，並藉由第二導電插 塞454相互耦接，而構成一第二電極結構474。另外，第 示）。因此’第1極結構472與第三電極結構[Second Embodiment J] In addition to the matching of the block-shaped first electrodes 212 and 222 and the% -shaped second electrodes 214 and 224 of the first embodiment described above, the electrodes of the capacitor structure of the present invention may have other different types. design. -Please refer to FIG. 3, which is a three-dimensional schematic diagram of a valley structure according to a second embodiment of the present invention. In order to clearly show the capacitor structure, FIG. 3 does not show the substrate. As shown in FIG. 3, the capacitor structure 300 is structured in a substrate, wherein the electrode groups 310 and 320 include, for example, first electrodes 312 and 322 in a ring shape and second electrodes 314 and 324 in a ring shape, and the second electrode 314 and 324 surround the first electrodes 312 and 322, respectively. In addition, the first electrodes 312 and 322 are respectively formed by the first conductive plug 352 and the second conductive electrode _2, 3 ... 4: f-pole structure 372 and a second electrode structure 374, of which the first electrode structure 372 and the second electrode structure 374 can be coupled to each other to provide a desired capacitance value. It is worth mentioning that, in other embodiments of the present invention, the shape of the first electrode may be, for example, a circle, a bar, a polygon, or other shapes, and the second electrode may be a rectangular ring as described above. It is a circular ring, a polygonal frame, or other shapes, but for the detailed structure and related configuration, please refer to the above embodiments, which will not be repeated hereafter. [Third Embodiment] Please refer to FIG. 4, which is a schematic perspective view of a capacitor structure according to a third embodiment of the present invention. As shown in FIG. 4, the electrode I2416 ^ 4twfdoc / c group 410 and 420 of the capacitor structure 400 has a first electrode 412 and 422 and a second electrode 414 and 424 surrounding the first electrode 412 and 422, respectively. The third electrodes 416 and 426 are included, and the third electrodes 416 and 426 surround the second electrodes 414 and 424, respectively. The two electrodes 416 and 426 are in a ring shape, and are mutually coupled by a third conductive plug 456 to form a third electrode structure 476. In this embodiment, the first electrode structure 472 and the third electrode structure 476 are, for example, plugs 442 and 446 to the power supply layer 462 below the substrate, respectively, and the ^ th electrode structure 444 can be connected to the power supply on the upper layer of the substrate, for example. The layer (not shown above), the first electrodes 412 and 422 are block-shaped, and are lightly connected to each other through the first conductive plug 452 to form a first electrode structure 472. In addition, the second electrodes 414 and 424 are It is ring-shaped and is coupled to each other through the second conductive plug 454 to form a second electrode structure 474. In addition, shown in FIG. Therefore, the first electrode structure 472 and the third electrode structure
置與耗接方式進行變更， [第四實施例] 當可滿足多元化之設計需求。 三電極結構476可具 74耦合產生所需之電 11 I2416^§4twfd〇c/c 、 值付 ^的疋，以上述之多種不同型態的電容結構 為基礎，本發明更提出由多個電容單元相互並聯所構成之 電容結構。 。月參考圖5，其緣示本發明之第四實施例之一種電容 結構的立體示意圖。本實施例之電容結構500例如是由第 一實施例所揭示的多個電容結構2〇〇所組成，其中相鄰電 容結構200内的第二電極結構274係相互鄰接，而第一電 極結構272係分別位於其所對應之第二電極結構274内。 以另一角度觀之，本實施例之電容結構5〇〇的每一 電極組510/520中例如具有一網格狀之第二電極514/524， 以及對應位於第二電極514/524之網格内的多個第一電極 512/522，其中相對應之第一電極512與522例如是藉由 第一導電插塞552相互耦接，並藉由導電插塞542耦接至 下層之電源層562。此外，第二電極514與524例如是藉 由一個或多個第二導電插塞554(圖5所示為多個)相互耦 接，並可耦接至同一平面上之外側電源或上層的電源層（未 緣示）。 [第五實施例] 除了上述之多種電容結構之外，本發明更提出一種 具有矩陣排列之電極的電容結構。 請參考圖6 ,其繪示為本發明之第五實施例之一種電 容結構的立體示意圖，其中為清楚表示電容結構，圖6未 繪示完整之基板。如圖6所示，電容結構6〇〇例如是架構 於一基板(未繪示）内，此基板例如是半導體基板、電路板 12 I2416^4twfdoc/c 或其他類型之線路基材。電容結構60〇包括電極組61〇、 620與630、多個第一導電插塞652以及多個第二導電插 塞654，其中電極組610、620與63Θ係相互對應並分別 位於基板的不同層之中，而間隔有介電層（未繪示）。 請再參考圖6，電極組610包括相互交替而呈一矩陣 排列的多個第一電極612與多個第二電極614，而電極組 620包括相互交替而呈一矩陣排列的多個第一電極幻2與 多個第二電極624，且電極組63〇包括相互交替而呈一矩 ，排列的多個第一電極632與多個第二電極634。此外， 第一導電插塞652係配置於電極組610、62〇與63〇之間（例 如疋位於上述之介電層内），且第一電極612、622與632 係相互對應，並分別藉由第一導電插塞652而相互耦接。 另外，第一導電插塞654亦配置於電極組61〇、62〇與63() 之間（例如疋位於上述之介電層内），且第二電極6丨4、624 與634係相互對應，並分別藉由第二導電插塞幻*而相互 在本貫施例中，第一電極612、622與632例如是呈 =，並藉由第-導電插塞652相連接而構成多個柱狀之 一:電極結構672，且每-第一電極結構672例如可藉由 一 V電插塞042耦接至下層之電源層662。此外，第二電 =614、624與634同樣是呈塊狀，並藉由第二導電插塞 相連接而構成多個柱狀之第二電極結構㈣，其中每 :第二電極結構674例如可藉由一導電插塞644祕至上 層之電源層664,且第-電極結構奶與第二電極結構㈣ 13 4twf.d〇c/cPlacement and consumption methods are changed. [Fourth embodiment] When multiple design requirements can be met. The three-electrode structure 476 may have 74 couplings to generate the required electricity 11 I2416 ^ §4twfdoc / c, and the value of 疋 is based on the above-mentioned various types of capacitor structures. The present invention further proposes a multi-capacitor structure. Capacitive structure composed of units connected in parallel with each other. . FIG. 5 is a schematic perspective view of a capacitor structure according to a fourth embodiment of the present invention. The capacitor structure 500 in this embodiment is, for example, composed of a plurality of capacitor structures 2000 disclosed in the first embodiment. The second electrode structure 274 in the adjacent capacitor structure 200 is adjacent to each other, and the first electrode structure 272 is adjacent to each other. They are respectively located in the corresponding second electrode structures 274. Viewed from another angle, each electrode group 510/520 of the capacitor structure 500 in this embodiment has, for example, a grid-shaped second electrode 514/524, and a grid corresponding to the second electrode 514/524. A plurality of first electrodes 512/522 in the grid, wherein the corresponding first electrodes 512 and 522 are coupled to each other through the first conductive plug 552, and are coupled to the lower power layer through the conductive plug 542, for example. 562. In addition, the second electrodes 514 and 524 are coupled to each other through one or more second conductive plugs 554 (a plurality are shown in FIG. 5), and may be coupled to an external power source or an upper layer power source on the same plane. Layer (not shown). [Fifth embodiment] In addition to the above-mentioned various capacitor structures, the present invention further proposes a capacitor structure having electrodes arranged in a matrix. Please refer to FIG. 6, which is a schematic perspective view of a capacitor structure according to a fifth embodiment of the present invention. In order to clearly show the capacitor structure, FIG. 6 does not show a complete substrate. As shown in FIG. 6, the capacitor structure 600 is, for example, structured in a substrate (not shown). The substrate is, for example, a semiconductor substrate, a circuit board 12 I2416 ^ 4twfdoc / c, or other types of circuit substrates. The capacitor structure 60 includes electrode groups 61, 620, and 630, a plurality of first conductive plugs 652, and a plurality of second conductive plugs 654. The electrode groups 610, 620, and 63Θ correspond to each other and are located on different layers of the substrate. Among them, a dielectric layer (not shown) is provided at intervals. Please refer to FIG. 6 again, the electrode group 610 includes a plurality of first electrodes 612 and a plurality of second electrodes 614 which are alternately arranged in a matrix, and the electrode group 620 includes a plurality of first electrodes which are alternately arranged in a matrix. Magic 2 and a plurality of second electrodes 624, and the electrode group 63o includes a plurality of first electrodes 632 and a plurality of second electrodes 634 that are alternately arranged at a moment. In addition, the first conductive plug 652 is disposed between the electrode groups 610, 62 and 63 (for example, 疋 is located in the above-mentioned dielectric layer), and the first electrodes 612, 622, and 632 correspond to each other, and are respectively borrowed. The first conductive plugs 652 are coupled to each other. In addition, the first conductive plug 654 is also disposed between the electrode groups 61, 62, and 63 () (for example, 疋 is located in the above-mentioned dielectric layer), and the second electrodes 6, 4, 624, and 634 correspond to each other. In addition, in the present embodiment, the first electrodes 612, 622, and 632 are respectively formed by the second conductive plug magic *, and a plurality of pillars are formed by connecting the first conductive plug 652. One of the shapes: the electrode structure 672, and each of the first electrode structures 672 can be coupled to the lower power layer 662 through a V electrical plug 042, for example. In addition, the second electrodes = 614, 624, and 634 are also block-shaped, and are connected by a second conductive plug to form a plurality of columnar second electrode structures. Each of the second electrode structures 674 may be Via a conductive plug 644 to the upper power supply layer 664, and the first electrode structure and the second electrode structure ㈣ 13 4twf.d〇c / c
I24167S Γ465^ 係相互交替而呈矩陣排列。藉由此矩陣排列之第一電極結 構672與第二電極結構674，可相互耦合形成電場，進而 提供所需之電容值。 值得注思的疋，雖然上述所有實施例僅緣示具有雙 層電極組之電容結構，但在實際應用上’本發明之電容結 構更可例如是由兩層以上之電極組相互祕堆疊而成，而° 八相關結構與配置凊參考上述實施例，在此不再重複贅 述。 綜上所述，本發明係藉由導電插塞耦接基板内不同 層的夕個電極，以形成三度空間之立體電 三度空間之立體電極可有效料基板上的佈線^猎= 視，求進彳了？元㈣電她置與設計，進而提高電路設計 之彈性。此外，由於每—電極組内的第—電極與第二電極 係位於基板之同―層，因此在線路_的製作上可 精確之控制，進而提供較佳之效能。 、权 雖然本發明已以較佳實施例揭露如麸 以限，，任何熟習此技藝者，在不脫離 =犯_ ’當可作些許之更動與潤飾，因此本發明之: 濩範圍當視後社_料職_界定者為準。 ’、 【圖式簡單說明】 圖1繪示為習知之一種平行板電容結構的示意圖。 圖2繪示為本發明之第-實關之 立體示意圖。 电合、、口構的 圖3繪示為本發明之第二實施例之—種電容結構的 I24167§4twf.d〇c/c 立體示意圖。 圖4繪示為本發明之第三實施例之一種電容結構的 立體示意圖。 圖5繪示為本發明之第四實施例之一種電容結構的 立體示意圖。 圖6繪示為本發明之第五實施例之一種電容結構的 立體示意圖。 【主要元件符號說明】 100 :平行板電容結構 110 :上電極板 120 :下電極板 130 :介電層 d :間距 200、300、400、500、600 :電容結構 210、220、310、320、410 ' 420、510、520、610、 620、630 :電極組 212、222、312、322、412、422、512 ' 522、612、 622、632 :第一電極 214、224、314、324、414、424、514、524、614、 624、634 :第二電極 416、426 :第三電極 242、442、446、542、642、644 :導電插塞 252、352、452、552、652 :第一導電插塞 254、354、454、554、654 :第二導電插塞 15 12416¾ 4twf.doc/c 456 :第三導電插塞 262、462、562、662、664 :電源層 272、372、472、672 ··第一電極結構 274、374、474、674 :第二電極結構 476 :第三電極結構 12416¾ 4twf.doc/cI24167S Γ465 ^ are alternately arranged in a matrix. The first electrode structure 672 and the second electrode structure 674 arranged in this matrix can be coupled to each other to form an electric field, thereby providing a desired capacitance value. It is worth noting that although all the above embodiments only show the capacitor structure with a double-layer electrode group, in practice, the capacitor structure of the present invention can be, for example, formed by stacking two or more electrode groups with each other secretly. For the related structure and configuration, please refer to the above embodiment, which will not be repeated here. In summary, the present invention couples the electrodes of different layers in the substrate through conductive plugs to form a three-dimensional three-dimensional space. The three-dimensional three-dimensional electrode can effectively wiring on the substrate. Do you want to enter? Yuan Ye Dian places and designs, thus improving the flexibility of circuit design. In addition, since the first electrode and the second electrode in each electrode group are located on the same layer of the substrate, the production of the circuit can be accurately controlled, thereby providing better performance. Although the present invention has been disclosed in a preferred embodiment, such as limited to bran, anyone who is familiar with this skill will not deviate from = guilty_ 'when you can make some changes and retouching, so the scope of the present invention: Society _ materials job _ defined whoever prevails. [Brief description of the drawings] FIG. 1 shows a schematic diagram of a conventional parallel plate capacitor structure. FIG. 2 is a three-dimensional schematic view of the first aspect of the present invention. Figure 3 of the electric coupling and opening structure is a three-dimensional schematic diagram of I24167§4twf.doc / c, which is a capacitor structure according to the second embodiment of the present invention. FIG. 4 is a schematic perspective view of a capacitor structure according to a third embodiment of the present invention. FIG. 5 is a schematic perspective view of a capacitor structure according to a fourth embodiment of the present invention. FIG. 6 is a schematic perspective view of a capacitor structure according to a fifth embodiment of the present invention. [Description of main component symbols] 100: Parallel plate capacitor structure 110: Upper electrode plate 120: Lower electrode plate 130: Dielectric layer d: Pitch 200, 300, 400, 500, 600: Capacitor structure 210, 220, 310, 320, 410 '420, 510, 520, 610, 620, 630: electrode group 212, 222, 312, 322, 412, 422, 512' 522, 612, 622, 632: first electrode 214, 224, 314, 324, 414 , 424, 514, 524, 614, 624, 634: second electrodes 416, 426: third electrodes 242, 442, 446, 542, 642, 644: conductive plugs 252, 352, 452, 552, 652: first Conductive plugs 254, 354, 454, 554, 654: second conductive plug 15 12416¾ 4twf.doc / c 456: third conductive plug 262, 462, 562, 662, 664: power supply layers 272, 372, 472, 672 ·· First electrode structure 274, 374, 474, 674: Second electrode structure 476: Third electrode structure 12416¾ 4twf.doc / c
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