§日修正/更正/補充 -----^^ 88121747 __年月 曰 絛正_ 五、發明說明（1) 一 ~ 5 -1發明領域： 本發明係有關於上升式源極/沒極之製作方法，特別 疋有關於降低小切面效應（f a c e t e f f e c t )之上升式源椤 /汲極之製作方法。 _ 5-2發明背景： 隨著積體電路的逐漸密集，半導體製程的尺寸有曰漸 縮小的趨勢。為順應此製程縮小趨勢，因而針對接觸結構 的改良’提出了上升式（ra i sed )源極/汲極的製作。此 型％之接觸結構’通常以植入換雜質的擴散效應來製作接 合點。且其接合深度（j Unc t i on de p th)可被大大地減低， 例如在極大型積體電路（ULSI )的結構中已可低於60nm。 但要形成如此淺的接合並與之接觸，使用傳統接觸程序便 不免對結構造成傷害。此時選擇性磊晶增生（selective epitaxial growth， SEG)技術因應而生。而第一、第二圖 顯示的’即為利用SEG所形成之上升式源極/汲極之製程剖 面。 參照第一圖，首先，以傳統之沈積及微影程序，於基 底1上形成閘極5 ^並於閘極之側邊，以沈積、回蝕的方式 ’形成介電間隙壁7。之後，選擇性地將矽增生在基底1上 ’形成隆起之源極/汲極9。接著’對此源極/汲極9進行離 子植入。而此植入之摻雜質，便開始由源極/汲極向下擴§ Day correction / correction / supply ----- ^^ 88121747 __Year month and month 绦 正 _ V. Description of the invention (1) 1 ~ 5 -1 Field of invention: The present invention relates to a rising source / impulse The manufacturing method is particularly related to the manufacturing method of the rising source / drain which reduces the faceteffect. _ 5-2 Background of the Invention: As integrated circuits become denser, the size of semiconductor processes tends to shrink. In order to comply with the shrinking trend of this process, for the improvement of the contact structure, a “rai sed” source / drain fabrication is proposed. This type of contact structure 'usually uses a diffusion effect of implantation to make a junction. And its junction depth (j Unc t i on de p th) can be greatly reduced, for example, it can be lower than 60 nm in the structure of a very large integrated circuit (ULSI). However, to form such a shallow joint and make contact with it, the use of traditional contact procedures will inevitably cause damage to the structure. At this time, selective epitaxial growth (SEG) technology was developed in response. The first and second figures show 'is the cross-section of the rising source / drain process using SEG. Referring to the first figure, first, a gate electrode 5 ^ is formed on the substrate 1 by a conventional deposition and lithography process, and a dielectric gap wall 7 is formed by means of deposition and etch-back ′ on the side of the gate electrode. After that, silicon is selectively grown on the substrate 1 to form a raised source / drain 9. Next, an ion implantation is performed on this source / drain 9. The implanted dopant begins to expand downward from the source / drain
第4頁 2001.02. 02.004 4 Λ月 曰 修正 五、發明說明（2) 政而參入基底.以形成技人 甘J* /ν 接a ’其接合輪廓8亦描纟合於第一阁 。圏中還繪有隔離區2，装孫ρ, φ u d彻、.S於弟圖 〇 ^ Λ ^其係用以電性隔離各相鄰元件。 最後，再進行自我對準软仆广 Μο ^ 丁旱矽化（sal aide )製程，將矽化金 屬9成形於閘極及源極/汲極 ^ 具導電性。 A極之上見第-圖，使擴散區罗 然而使用SEG所形成之上升式源極/汲極’通常會有小 切面現象（faceting)產生，見第一、第二圖小切面6。而 此小切面的發生’其主要歸因於矽沈積過程中，晶格堆積 速率的差異所致’舉例來說，< 1 〇 〇 >面就要比< Π 1 >面要快 的多，因此其成形之表面也就不一致。表面的不平坦，將 使後續植入的離子滲透不均勻。其結果使切面區離子的滲 入要較其餘之SEG區來得深’而致使接合輪廓形成一凹槽 狀，如第一圖所示°同理’其矽化金屬的形成，亦趨向凹 檜輪廓（位於切面區）的產生，如第二圖所示，元件漏電 的情形因而大為提高。 欲降低小切面效應’或有於低溫低壓下’藉由D C S -HchH2混合氣體的輔助效應；亦可將各接合面定位於<1〇〇 〉面，再進行沈精。而本發明所提出的，則是利用多一層 間隙壁的屏障，來舒緩小切面的形成。 5 - 3發明目的及楙述，Page 4 2001.02. 02.004 4 Λ 月 Said amendment V. Description of the invention (2) Political participation in the base. To form a technician Gan J * / ν then a ′, its joint profile 8 is also described in the First Pavilion. There is also an isolation zone 2 in the frame, which is filled with the sun ρ, φ u d, and .S Yudi. 〇 ^ Λ ^ It is used to electrically isolate adjacent components. Finally, a self-aligned soft-serving MEMS is used to process the sal aide process, and the silicide metal 9 is formed on the gate and source / drain electrodes. It is conductive. Above the A pole, see Figure-to make the diffusion zone. However, the rising source / drain 'formed by using SEG usually has a small faceting phenomenon. See the first and second small facets 6. And the occurrence of this small section “is mainly due to the difference in the lattice stacking rate during the silicon deposition process”, for example, the <1〇〇> face is faster than the < Π 1 > face More, so the surface of its formation is also inconsistent. The uneven surface will make the ion implantation of the subsequent implantation uneven. As a result, the penetration of ions in the cut surface area is deeper than the rest of the SEG area, and the joint contour is formed into a groove shape, as shown in the first figure. Cut plane area), as shown in the second figure, the situation of leakage of components is greatly improved. To reduce the small section effect ’or at low temperature and low pressure’ by the auxiliary effect of the D C S -HchH2 mixed gas; each joint surface can also be positioned at the <100> plane and then refined. The invention proposes to use an extra layer of barriers to ease the formation of small sections. 5-3 invention purpose and description,
第5頁 2001.02. 02. 005Page 5 2001.02. 02. 005
修正 傳統以選擇性增生程序所製 顯的小切面，而衍生出諸多 、切面現象的存在’使小切面 蓉於上述之發明背景中， 作之上升式源極/沒極具有明 缺點。本發明的目的在舒緩，J 效應得以降低。 極/汲極 成介電間 壁於介電 形成的源 擇性增生 源極/汲 斜度，舒 低β此外 而形同源 切對應（ 弭至最小 叩柢煨以上所述之 結構及 隙壁於 間隙壁 極/汲 源極/ 極的增 緩了晶 ，此矽 極/汲 與源極 其製造 閘極之 的側邊 極層相 没極區 生程序 格堆疊 間隙壁 極的部 /〉及極 方法。 側壁。 ，此石夕 同或略 。由於 多了 — 的速度 的存在 分結構 )的厚 本發明 首先， 之後， 間隙壁 薄。接 多了前 延展之 差異， ，亦可 。因此 度與斜 提供了 一 以沈積、 再沈積、 的沈積厚 著，由該 述矽間隙 基底，其 使小切面 行事先填 ，矽間隙 度，可將 回蝕程序形 回蝕矽間隙 度約與後續 基底上，選 壁的屏障， 緩緩上升之 效應得以降 補的作用， 壁右有一適 切面效應消 圖式簡單說明： 而揭ΐ發ϋ Ξ容可經由下述實施例與其相關圖示的聞述 '、 和第二圖簡示傳統上升式源極/汲極的Correcting the traditionally produced small facets by selective proliferation procedures, and deriving many existences of the facet phenomenon, makes the small facets in the above-mentioned background of the invention, and the rising source / promise has obvious shortcomings. The purpose of the present invention is to soothe and reduce the J effect. The pole / drain becomes a dielectric selective source-derived source / drain slope formed by the dielectric wall, and the low β also corresponds in a tangential manner (弭 to the minimum 结构 structure and gap wall described above). The crystals are slowed down due to the gap wall / drain source / pole. The silicon / drain and the source electrode are fabricated on the side of the gate electrode, and the electrode region is stacked. Method. The thickness of the side wall is the same as or slightly different. Due to the existence of more speed, the thickness of the structure of the invention is first, and then the gap is thin. The differences between the previous extensions are also acceptable. Therefore, the degree and slope provide a thick deposition, re-deposition, and deposition. From the silicon gap substrate, which fills the small cross-sections in advance, the silicon gap can be etched back to the silicon gap. Subsequent selection of the barrier of the wall, the effect of the slow rise can be reduced and supplemented. The right side of the wall has a tangent plane effect. The elimination diagram is briefly explained: Wenshu ', and the second figure shows the traditional rising source / drain
第6頁 2001.02.02. 006 /^470 ] 8 五、發明說明（4) 製程結構，第三至第七圖則依序展示製作本發明實施例之 上升式源極/汲極結構之關鍵步驟。 第一圖顯示傳統之上升式源極/汲極結構，其具明影 小切面，並具凹狀接合輪廓； 第二圖顯示，傳統之上升式源極/汲極結構，經自行 對準矽化金屬製程，其矽化金屬層輪廓不均勻； 第三圖顯示根據本發明實施例之介電間隙壁，形成於 閘極側邊； 第四圖顯示根據本發明實施例之發層沈積程序； 第五圖顯示根據本發明實施例之石夕間隙壁，經回敍， 形成於介電間隙壁之側邊； 序第六圖顯示根據本發明實施例之選擇性矽磊晶增生程 之技=成上升式之源極/汲極，圖中並描繪出其經摻雜後 钱合輪廓； 第七圖顯示根據本發明實施例，金屬矽 〜構。 X形之終極 Δ Δ7 η 1 qPage 6 2001.02.02. 006 / ^ 470] 8 V. Description of the invention (4) Process structure, and the third to seventh diagrams sequentially show the key steps for making the rising source / drain structure of the embodiment of the present invention. . The first picture shows a traditional rising source / drain structure with a small shadow plane and a concave joint profile. The second picture shows a traditional rising source / drain structure, which is self-aligned and silicided. The metal process has a non-uniform outline of the silicided metal layer. The third figure shows a dielectric spacer according to an embodiment of the present invention formed at the gate side. The fourth figure shows a hairline deposition process according to an embodiment of the present invention. Fifth The figure shows the Shi Xi gap wall according to the embodiment of the present invention, which is formed on the side of the dielectric gap wall after recounting. The sixth figure shows the technique of selective silicon epitaxial growth process according to the embodiment of the present invention = ascending The source / drain of the formula is shown in the figure and the doped coin profile is depicted in the figure; the seventh figure shows the metal silicon structure according to the embodiment of the present invention. X-shaped ultimate Δ Δ7 η 1 q
* » < <^ι> I 五、發明說明（5) 主要部分之代表符號： 1矽基底 2介電隔離區 5閉極 6 源極/;及極上之小切面 7介電間隙壁 8接合輪廓 9 源極/汲極 11矽化金屬層 10 珍基底 20介電隔離層 3 0 閘極 4 0 介電間隙壁 5 0矽層/矽間隙壁 60 源極/汲極 7 0石夕化金屬層 88接合輪廓 5 - 5發明詳細說明： 以下對製程與結構之描述並不包括積體電路製造的完 整流程。本發明所沿用的現有技藝，在此僅作重點式的引 用，以助本發明的闡述。而前述之相關圖示並未依比例繪* »≪ < ^ ι > I V. Description of the invention (5) Representative symbols of main parts: 1 silicon substrate 2 dielectric isolation region 5 closed electrode 6 source /; and small section on the pole 7 dielectric gap 8 Bonding profile 9 source / drain 11 siliconized metal layer 10 precious substrate 20 dielectric isolation layer 3 0 gate 4 0 dielectric spacer 5 0 silicon layer / silicon spacer 60 source / drain 7 0 Layer 88 joint profile 5-5 Detailed description of the invention: The following description of the process and structure does not include the complete process of integrated circuit manufacturing. The prior art used in the present invention is only used as a key reference here to help explain the present invention. The aforementioned related icons are not drawn to scale
第8頁 曰 修正 4 4^7I曰修正/史正/補充 案號 88121747 五、發明說明（6) --- 製，其作用僅在表現本發明之結構特徵。 :在我們將參閱第三至第七s，對本發明實施例做一 沣盡解說。在第三圖中，見閘極30座落於矽基底1〇上。此 :基質，根據其作用及所在而定’可摻雜成η型或P- t而溝錢離區㈣散布於晶圓各處，肖以隔離各元件 電首先，沈積一介電層於元件表面’此介 ΚΙ:?乳化物或氮化物。經回钱程序，閉極3〇之側壁 即有介電間隙壁4 〇形成。 之後 中上述之 低壓化學 類可以是 層進行非 40的側邊 刻與濕Ί虫 此矽間隙 層間，以 ，沈積一層厚約1〇0至50〇埃之矽於元件表面，其 f積的方法至少包含電漿強化化學氣相沉積法、 :相沉積法等方法’如第四圖所*。此砂層的種 ^雜過或未經播雜的多晶矽或非晶矽。再對此矽 向丨生银刻以开> 成另一間隙壁5 0於介電間隙壁 ，其中上述之非等向性蝕刻的方法至少包含乾蝕 j ’例如電漿蝕刻、活性離子蝕刻，&第五圖。 =50緩衝於介電間隙壁和後續形成之源極/汲極 降低小切面效應。 接著*由該基底10上，選擇性增 growth ) - μ έΜ nn ^ Rnn selective 41. ^ ώ κ / \ π 签瓜，丹硬後工 —緩了晶格堆^；速度差異，使小切面效應得 mu.r»u«nr* ________ 源極/ m ^ DG 6⑽埃之⑪或残層，而形成隆起之 屏障功品6 〇，如第六圖所示。由於多了矽間隙壁5 0的 =粗Γ切鍺的增生程序多了—延展之基底，其緩緩上Page 8: Amendment 4 4 ^ 7I: Amendment / Shizheng / Supplement Case No. 88121747 V. Description of the invention (6) --- The system only functions to represent the structural features of the present invention. : In the following we will refer to the third to seventh s, and make an exhaustive explanation of the embodiment of the present invention. In the third figure, the gate electrode 30 is located on a silicon substrate 10. This: The substrate, depending on its role and location, can be doped into η-type or P-t and the trenches are scattered around the wafer. To isolate the electrical components, first, a dielectric layer is deposited on the components. The surface 'this medium KIL :? Emulsions or nitrides. After the money-back procedure, a dielectric gap wall 40 was formed on the side wall of the closed electrode 30. After that, the above-mentioned low-pressure chemical type can be a layer of non-40 side engraving and a silicon interlayer between the wet tapeworm to deposit a layer of silicon with a thickness of about 100 to 50 angstroms on the surface of the device, and the f product method At least the plasma enhanced chemical vapor deposition method and the phase deposition method are included as shown in the fourth figure *. Species of this sand layer are polycrystalline silicon or amorphous silicon with or without seeding. The silicon is then etched with silver to form another gap wall 50 on the dielectric gap wall, wherein the above-mentioned method of anisotropic etching includes at least dry etching, such as plasma etching, reactive ion etching, etc. &Amp; Fifth Figure. = 50 is buffered in the dielectric spacer and the source / drain formed later to reduce the small-section effect. Then * from the substrate 10, selectively increase growth)-μ ΜΜ nn ^ Rnn selective 41. ^ ώ κ / \ π Sign melon, Dan hard workmanship-slow down the lattice pile ^; speed difference, make small cut effect You get mu.r »u« nr * ________ source / m ^ DG 6 ⑽ ⑪ 残 残 or residue, and form a raised barrier work 6 〇, as shown in the sixth figure. Since there are more silicon spacers 50 = coarser Γ-cut germanium, there are many more hyperplasia procedures—the extended base, which slowly rises.
mm 第9頁 2001.02.02.009 充 ϋ·;ίΊΓ· 索就 88Γ2Π47 ‘ 五 '發明說明（7) 以降低。此外，此矽間隙壁的存在，亦可行事先填補的作 用，而形同源極/汲極的部分結構。因此，矽間隙壁若有 -適切對應（與源極/没極）的厚度與斜度，可將切面 消弭至最小。 ‘ 此時植入離子於源極/汲極區，其接合輪廓8 8則可 平順，如第六圖所示。而當石夕化金屬層70於該問極和該源 極/汲極上以自我對準方式形成之時，示於第七圖，則不 會有特別突出而深厚的金屬區存纟，造成接合漏渴的情形 以上所述僅為本發明$ 定本發明之申請專利範圍； 精神下所完成之等效改變達 專利範圍内。 較佳實施例而已，並非用以限 凡其它未脫離本發明所揭示之 修飾，均應包含在下述之申請mm Page 9 2001.02.02.009 Charge ϋ ·; ίΊΓ · Ask for 88Γ2Π47 ‘five’ invention description (7) to reduce. In addition, the existence of this silicon spacer can also be filled in advance, and it has a partial structure with the same source / drain. Therefore, if the silicon spacer has a thickness and slope corresponding to (appropriate to the source / non-electrode) thickness, the section can be minimized. ‘At this point, the ions are implanted in the source / drain region, and the bonding profile 8 8 is smooth, as shown in the sixth figure. When the Shixihua metal layer 70 is formed on the question and source / drain electrodes in a self-aligned manner, as shown in the seventh figure, there is no particularly prominent and deep metal region existing, resulting in bonding. A thirsty situation described above is only the scope of the present invention to determine the scope of patent application for the present invention; equivalent changes made in the spirit are within the scope of the patent. The preferred embodiments are not intended to limit all other modifications that do not depart from the disclosure of the present invention, and should be included in the following applications