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TW367499B - Multi-level DRAM sensing design - Google Patents

Multi-level DRAM sensing design

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Publication number
TW367499B
TW367499B TW087108990A TW87108990A TW367499B TW 367499 B TW367499 B TW 367499B TW 087108990 A TW087108990 A TW 087108990A TW 87108990 A TW87108990 A TW 87108990A TW 367499 B TW367499 B TW 367499B
Authority
TW
Taiwan
Prior art keywords
bit
area
line
switching transistors
sensing amplifier
Prior art date
Application number
TW087108990A
Other languages
Chinese (zh)
Inventor
Ming-Hua Ji
Hong-Xiang Cai
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW087108990A priority Critical patent/TW367499B/en
Application granted granted Critical
Publication of TW367499B publication Critical patent/TW367499B/en

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Abstract

A kind of multi-level DRAM sensing design which detects the level of charge and interprets the digital data presented by DRAM cell. The design includes a multi-level sensing amplifier structure composed of the first and the second bit-line with the first and second area respectively; the first and second pair of isolation switching transistors separate the first and second area of the first bit-line and the first and second area of the second bit-line respectively; a latch sensing amplifier which has the first and second input connected with the pair of isolated switching transistors respectively the output connected to the external circuit; a cross coupled capacitor used to couple the charge transfer between the first area of the first bit-line and the second area of the second bit-line; a control logic region connected to DRAM cells for controlling selection of each DRAM cell and connected to latch sensing amplifier for controlling activation of sensing amplifier and also connected to isolation switching transistors for controlling the activation and deactivation of isolated switching transistors.
TW087108990A 1998-06-06 1998-06-06 Multi-level DRAM sensing design TW367499B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087108990A TW367499B (en) 1998-06-06 1998-06-06 Multi-level DRAM sensing design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087108990A TW367499B (en) 1998-06-06 1998-06-06 Multi-level DRAM sensing design

Publications (1)

Publication Number Publication Date
TW367499B true TW367499B (en) 1999-08-21

Family

ID=57941228

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087108990A TW367499B (en) 1998-06-06 1998-06-06 Multi-level DRAM sensing design

Country Status (1)

Country Link
TW (1) TW367499B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI655631B (en) * 2013-11-27 2019-04-01 密西根大學董事會 Memory circuitry and method of reading data from memory circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI655631B (en) * 2013-11-27 2019-04-01 密西根大學董事會 Memory circuitry and method of reading data from memory circuitry

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