TW202542570A - Adapter board, its manufacturing method and optical chip packaging structure - Google Patents

Abstract

This disclosure provides an adapter board, its manufacturing method, and an optical chip packaging structure. The adapter board includes: a glass substrate including one or more conductive vias, the conductive vias including through-holes penetrating the glass substrate and conductive material filling the through-holes; and an optical coupling structure disposed on a first surface of the glass substrate, wherein the glass substrate further includes a three-dimensional waveguide network for optically interconnecting multiple optical chips packaged on the adapter board, the optical coupling structure including a coupling optical waveguide covering the optical input and output ports of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide, and the optical coupling structure further includes one or more first conductive structures penetrating the optical coupling structure, which are electrically connected to the one or more conductive vias respectively.

Description

Adapter board, its manufacturing method and optical chip packaging structure

This patent application claims priority to Chinese patent application No. 202210369385.3, filed on April 8, 2022. This disclosure relates to the field of semiconductor packaging, specifically to an adapter board for optical chip packaging, an optical chip packaging structure, a computing accelerator, and a method for manufacturing the adapter board and the optical chip packaging structure.

When packaging photonic integrated circuits (PICs, also known as photonic chips), electronic integrated circuits (EICs, also known as electronic chips) are typically stacked on top of the photonic integrated circuits to form a hybrid photonic-electronic integrated circuit (hybrid photonic-electronic chip), thereby creating a hybrid optoelectronic system and accelerating computation. To reduce chip size, electrical connections can be transferred to the substrate or printed circuit board (PCB) via vertical interconnects (e.g., through silicon vias (TSVs)).

However, silicon interposers with embedded TSVs still face cost challenges. Silicon wafers are semiconductor substrates with low resistivity and high dielectric constant; thin silicon wafers are difficult to process, and manufacturing TSVs remains expensive due to the long processing time for drilling and electroplating copper to fill the vias. Furthermore, previous technologies typically required additional optical fibers to achieve optical interconnects between different optical chips, resulting in excessively large package sizes for optoelectronic hybrid modules.

In view of the above problems, this disclosure aims to provide an interposer based on a glass substrate (e.g., a glass wafer) and its manufacturing method, as well as an optical chip packaging structure using this interposer and its manufacturing method. Due to the high resistivity, low electrical loss, adjustable coefficient of thermal expansion, and good mechanical strength of the glass substrate, the interposer based on the glass substrate has low manufacturing cost and can be effectively used for optical chip packaging. Furthermore, this disclosure also aims to provide an optical chip packaging structure and its manufacturing method that uses thermally adiabatic coupling to couple optical signals between optical waveguides on the interposer and optical waveguides on the optical chip. This coupling method occupies a small area, allows for close-packing of waveguides, improves integration, and reduces package size.

The first aspect of this disclosure provides an adapter board for optical chip packaging, comprising: a glass substrate including one or more conductive vias, the conductive vias including through-holes penetrating the glass substrate and conductive material filling the through-holes; and an optical waveguide structure disposed on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides, the one or more optical waveguides being used for optical interconnection of multiple optical chips packaged on the adapter board, and the refractive index of the one or more optical waveguides being greater than the refractive index of the coating layer and the glass substrate, and the optical waveguide structure further including one or more first conductive structures penetrating the optical waveguide structure, which are electrically connected to the one or more conductive vias respectively.

In some embodiments, the aforementioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the aforementioned cladding layer is silicon dioxide.

In some embodiments, the adapter plate further includes: a dielectric layer disposed on a second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

The second aspect of this disclosure provides another adapter board for optical chip packaging, comprising: a glass substrate including one or more conductive vias, the conductive vias including through-holes penetrating the glass substrate and conductive material filling the through-holes; and an optical coupling structure disposed on a first surface of the glass substrate, wherein the glass substrate further includes a three-dimensional waveguide network for optically interconnecting multiple optical chips packaged on the adapter board, the optical coupling structure including a coupling optical waveguide covering the optical input and output ports of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide, and the optical coupling structure further including one or more first conductive structures penetrating the optical coupling structure, which are electrically connected to the one or more conductive vias respectively.

In some embodiments, the refractive index of the coupled optical waveguide is lower than that of the three-dimensional waveguide network but higher than that of the cladding layer.

In some embodiments, the aforementioned coupling optical waveguide is a silicon nitride optical waveguide, and the aforementioned cladding layer is made of silicon dioxide.

In some embodiments, the adapter plate further includes: a dielectric layer disposed on a second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

In some embodiments, the aforementioned three-dimensional waveguide network is a network structure formed by inducing local glass within the aforementioned glass substrate to increase the refractive index of the local glass.

The disclosed cooperating supplier provides another adapter board for optical chip packaging, comprising: a glass substrate including one or more first conductive vias, the first conductive vias including through-holes penetrating the glass substrate and conductive material filling the through-holes; and an electrical interconnection structure disposed on a first surface of the glass substrate, wherein the electrical interconnection structure includes one or more wiring layers and a coating layer covering the one or more wiring layers, the coating layer being a dielectric material, the one or more wiring layers being used for electrically interconnecting multiple electronic chips above the optical chip packaged on the adapter board, and the electrical interconnection structure further including one or more first conductive structures penetrating the electrical interconnection structure, which are electrically connected to the one or more first conductive vias respectively.

In some embodiments, at least two of the aforementioned multilayer wiring layers are electrically connected through a second conductive structure.

In some embodiments, the aforementioned coating layer is a multi-layered structure formed by alternating layers of silicon nitride and silicon dioxide.

In some embodiments, the adapter board further includes an optical waveguide structure disposed on the surface of the electrical interconnection structure away from the glass substrate. The optical waveguide structure includes one or more optical waveguides and an cladding layer surrounding the one or more optical waveguides. The one or more optical waveguides are used to optically interconnect multiple optical chips packaged on the adapter board. The refractive index of the waveguides is greater than that of the cladding layer. The optical waveguide structure also includes one or more third conductive structures penetrating the optical waveguide structure and electrically connected to the one or more first conductive structures respectively.

In some embodiments, the aforementioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the aforementioned cladding layer is silicon dioxide.

In some embodiments, the adapter plate further includes: a dielectric layer disposed on the second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more fourth conductive structures penetrating the dielectric layer, which are electrically connected to the one or more first conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.

The fourth aspect of this disclosure provides a method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming one or more conductive vias in the glass substrate; disposing an optical waveguide structure on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides; and forming one or more first conductive structures penetrating the optical waveguide structure in the coating layer and electrically connecting them to the one or more conductive vias respectively, wherein the refractive index of the one or more optical waveguides is greater than the refractive index of the coating layer.

In some embodiments, the aforementioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the aforementioned coating layer is silicon dioxide.

In some embodiments, configuring an optical waveguide structure on the first surface of the glass substrate includes: a. forming an optical waveguide network on the first surface of the glass substrate using wafer-level nanoimprint lithography; b. depositing a coating material over the optical waveguide.

In some embodiments, the manufacturing method of the adapter plate further includes: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to one or more conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and disposing a conductive material layer on the inner surface of the one or more vias to form the one or more conductive vias.

In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

The fifth aspect of this disclosure provides another method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming a three-dimensional waveguide network within the glass substrate for optical interconnection of multiple optical chips packaged on the adapter board; forming one or more conductive vias in the glass substrate; disposing a coupling optical waveguide on a first surface of the glass substrate to cover the optical input and output ports of the three-dimensional waveguide network; covering the coupling optical waveguide with a cladding layer; and forming one or more first conductive structures penetrating the cladding layer in the cladding layer and electrically connecting them to the one or more conductive vias respectively.

In some embodiments, the refractive index of the coupled optical waveguide is lower than that of the three-dimensional waveguide network but higher than that of the cladding layer.

In some embodiments, the aforementioned coupling optical waveguide is a silicon nitride optical waveguide, and the aforementioned cladding layer is made of silicon dioxide.

In some embodiments, the manufacturing method of the adapter plate further includes: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to one or more conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and disposing a conductive material layer on the inner surface of the one or more vias to form the one or more conductive vias.

In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

In some embodiments, forming a three-dimensional waveguide network within the glass substrate includes: irradiating a predetermined position of the glass substrate with a femtosecond laser to increase the refractive index of the predetermined position of the glass substrate, wherein the predetermined position is the location where the three-dimensional waveguide network structure is formed.

The sixth aspect of this disclosure provides another method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming one or more first conductive vias in the glass substrate; disposing an electrical interconnection structure on a first surface of the glass substrate, wherein the electrical interconnection structure includes one or more wiring layers and a coating layer covering the one or more wiring layers, the coating layer being a dielectric material, the one or more wiring layers being used for electrically interconnecting multiple electronic chips packaged above the adapter board; and forming one or more first conductive structures penetrating the electrical interconnection structure, which are electrically connected to the one or more first conductive vias respectively.

In some embodiments, configuring an electrical interconnection structure on the first surface of the glass substrate includes: configuring a first wiring layer on the first surface of the glass substrate; forming a first silicon nitride layer around the first wiring layer; and covering the first silicon nitride layer with a first silicon oxide layer.

In some embodiments, the provision of an electrical interconnection structure on the first surface of the glass substrate further includes: providing a second wiring layer on the first surface of the first silicon oxide layer; forming a second silicon nitride layer around the second wiring layer; and covering the second silicon nitride layer with a second silicon oxide layer.

In some embodiments, configuring the electrical interconnection structure on the first surface of the glass substrate further includes forming a second conductive structure between the first and second wiring layers to electrically connect the first and second wiring layers.

In some embodiments, the manufacturing method of the aforementioned adapter board further includes: disposing an optical waveguide structure on the surface of the electrical interconnection structure away from the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and an cladding layer surrounding the one or more optical waveguides, the one or more optical waveguides being used to optically interconnect multiple optical chips packaged on the adapter board, and having a refractive index greater than that of the cladding layer; and forming one or more third conductive structures penetrating the optical waveguide structure in the optical waveguide structure, and electrically connecting them to the one or more first conductive structures respectively.

In some embodiments, the aforementioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the aforementioned cladding layer is silicon dioxide.

In some embodiments, the manufacturing method of the adapter plate further includes: disposing a dielectric layer on the second surface of the glass substrate; forming one or more fourth conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to the one or more first conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.

In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and disposing a conductive material layer on the inner surface of the one or more vias to form the one or more conductive vias.

In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

The seventh aspect of this disclosure provides an optical chip packaging structure, which includes a converter board as described above, and a plurality of optical chips disposed on the converter board, the converter board being used for optical interconnection of the plurality of optical chips disposed on the converter board.

In some embodiments, the aforementioned optical chip packaging structure further includes: one or more electrical chips disposed on the plurality of optical chips; the optical chips include one or more interconnection structures, the interconnection structures including vias penetrating the optical chips and conductive materials filling the vias; the one or more interconnection structures are respectively electrically connected to the one or more first conductive structures or electrical interconnection structures on the aforementioned adapter board.

The eighth aspect of this disclosure provides an optical chip packaging structure, comprising: an adapter plate including one or more first optical waveguides embedded therein; and a plurality of optical chips, each optical chip including one or more second optical waveguides embedded therein, wherein the plurality of optical chips are attached to different positions on the upper surface of the adapter plate and are optically interconnected through the one or more first optical waveguides, each of the first optical waveguides including a first optical coupling portion, each of the second optical waveguides including a second optical coupling portion, and the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally insulating optical coupling.

In some embodiments, the first optical coupling part and the second optical coupling part are respectively tapered.

In some embodiments, the first optical coupling part and the second optical coupling part are respectively formed by two tapered shapes of different sizes connected in series.

In some embodiments, the predetermined distance is less than or equal to 600 nm.

In some embodiments, this optical chip package structure further includes: a plurality of electrical chips disposed on a plurality of first optical chips, wherein each first optical chip has one or more first electrical connectors on its upper surface and one or more second electrical connectors on its lower surface, and the one or more first electrical connectors are respectively electrically connected to the one or more second electrical connectors.

In some embodiments, the first optical chip further includes one or more second conductive vias passing through it, and the one or more second conductive vias are electrically connected to one or more conductive structures in the adapter board.

In some embodiments, the first optical chip is directly bonded to the electrical chip; or the first optical chip and the electrical chip are bonded together via flip-chip bonding.

In some embodiments, the plurality of optical chips are discrete optical chips obtained after slicing photonic wafers. They are spaced apart from each other on the upper surface of the adapter plate, and the gaps between them are filled with a molding material. A dielectric layer for blocking the outward transmission of light in the adapter plate is disposed between the molding material and the upper surface of the adapter plate.

In some embodiments, the aforementioned multiple optical chips are multiple undivided optical chips within the same photonic wafer.

In some embodiments, the plurality of optical chips are undivided optical chips in the same photonic wafer, the plurality of optical chips have a plurality of first optical chips, each first optical chip is disposed on an electrical chip, the plurality of electrical chips on the plurality of first optical chips are a plurality of undivided electrical chips in the same electronic wafer, and the photonic wafer is directly bonded to the electronic wafer.

In some embodiments, all of the aforementioned optical chips are provided with corresponding electrical chips, and the corresponding electrical chips on all the optical chips are multiple undivided electrical chips in the same electronic wafer, wherein the aforementioned optical chips have the same structure, and the aforementioned electrical chips also have the same structure.

In some embodiments, the aforementioned adapter board is an adapter board as described above, and the aforementioned one or more first optical waveguides are one or more layers of optical waveguides in the optical waveguide structure of the aforementioned adapter board.

In some embodiments, the aforementioned adapter board is an adapter board as described above, and the one or more first optical waveguides are a three-dimensional waveguide network in the aforementioned adapter board and a coupling optical waveguide covering the optical input and output of the aforementioned three-dimensional waveguide network.

The ninth aspect of this disclosure provides a computing accelerator, comprising: one or more light sources disposed on a first surface of the adapter plate in the aforementioned optical chip package structure and configured to provide light waves to the computing accelerator; one or more computing units implemented by the optical chips in the aforementioned optical chip package structure, or by the optical chips and electronic chips in the aforementioned optical chip package structure, or by electronic chips in the aforementioned optical chip package structure, and configured to perform computing functions; and one or more memory units implemented by electronic chips in the aforementioned optical chip package structure and configured to perform memory functions.

In some embodiments, the adapter board is the same as described above.

The ninth aspect of this disclosure provides a computing accelerator, comprising: one or more edge optical couplers configured to optically interconnect the computing accelerator with other devices; one or more light sources configured to provide light waves to the computing accelerator, the light waves being coupled to the one or more edge optical couplers through a light guide structure; one or more computing units implemented by optical chips in the aforementioned optical chip package structure, or by optical chips and electrical chips in the aforementioned optical chip package structure, or by electrical chips in the aforementioned optical chip package structure, and configured to perform computing functions; and one or more memory units implemented by electrical chips in the aforementioned optical chip package structure, and configured to perform memory functions.

In some embodiments, each computing unit and corresponding memory unit are implemented by each optical chip and corresponding electrical chip in the optical chip package structure as described above, serving as a computing-memory unit.

In some embodiments, the adapter board in the aforementioned optical chip packaging structure is the adapter board described above.

In some embodiments, the computing accelerator further includes multiple high bandwidth memory (HBM) chips stacked on the optical chip in the aforementioned optical chip package structure, which are configured to perform memory computing functions.

The tenth aspect of this disclosure provides a method for manufacturing an optical chip package structure, comprising: providing an adapter plate including one or more first optical waveguides embedded therein, each of the first optical waveguides including a first optical coupling portion; and attaching a plurality of optical chips to different positions on the upper surface of the adapter plate, each optical chip including one or more second optical waveguides embedded therein, each of the second optical waveguides including a second optical coupling portion, wherein the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally adiabatic optical coupling, and the plurality of optical chips are optically interconnected through the one or more first optical waveguides.

In some embodiments, the first optical coupling part and the second optical coupling part are respectively tapered.

In some embodiments, the first optical coupling part and the second optical coupling part are respectively formed by two tapered shapes of different sizes connected in series.

In some embodiments, the predetermined distance is less than or equal to 600 nm.

In some embodiments, before attaching the plurality of optical chips to different positions on the upper surface of the adapter plate, the method further includes: disposing an electronic chip on a first optical chip among the plurality of optical chips, such that the first optical chip and the electronic chip thereon form an electron-photon hybrid chip, wherein the upper surface of the first optical chip has one or more first electrical connections, the lower surface of the electronic chip has one or more second electrical connections, and the one or more first electrical connections are respectively electrically connected to the one or more second electrical connections.

In some embodiments, configuring electronic chips on a first optical chip among the plurality of optical chips includes: fabricating a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical chips and the electronic wafer includes a plurality of electronic chips; directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical chips are bonded to the plurality of electronic chips to obtain an electronic-photonic hybrid wafer; removing the substrate of the photonic wafer; and dicing the electronic-photonic hybrid wafer into a plurality of electronic-photonic hybrid chips.

In some embodiments, configuring an electronic chip on a first optical chip among the plurality of optical chips includes: fabricating a photonic wafer and an electronic wafer, wherein the photonic wafer includes the plurality of optical chips and the electronic wafer includes a plurality of electronic chips; dicing the electronic wafer into the plurality of electronic chips; directly bonding or flip-chip bonding one or more of the plurality of electronic chips to the first optical chip in the photonic wafer to obtain an electronic-photonic hybrid wafer; filling the gaps on the photonic wafer not occupied by the electronic chips with a molding material; removing the substrate of the photonic wafer; and dicing the electronic-photonic hybrid wafer into the electronic-photonic hybrid chips.

In some embodiments, the method further includes: after removing the substrate of the photonic wafer and before dicing the electron-photonic hybrid wafer into the electron-photonic hybrid chip, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness.

In some embodiments, the method further includes: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, forming a connecting waveguide on the surface of the photonic wafer away from the electronic chip, wherein the connecting waveguide, the second optical coupling portion of the second optical waveguide, and the first optical coupling portion of the first waveguide are stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer; and covering the connecting waveguide with a dielectric material to coat the connecting waveguide. In some embodiments, the method further includes: after fabricating the photonic wafer, forming one or more second conductive vias in the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, so that the one or more second conductive vias are vertically connected to form one or more second conductive vias.

In some embodiments, attaching the plurality of optical chips to different positions on the upper surface of the adapter plate further includes: electrically connecting one or more second conductive vias to one or more conductive structures in the adapter plate respectively.

In some embodiments, the plurality of electron-photon hybrid chips are spaced apart from each other on the upper surface of the adapter plate, and the method further includes: forming a dielectric layer on the upper surface of the adapter plate and in the gaps between the plurality of electron-photon hybrid chips to block the outward transmission of light in the adapter plate; and filling the dielectric layer and the gaps between the electron-photon chips with a molding material.

In some embodiments, configuring electronic wafers on a first optical chip among the plurality of optical chips includes: fabricating a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical chips and the electronic wafer includes a plurality of electronic wafers; and directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical chips and the plurality of electronic wafers are bonded to obtain an electronic-photonic hybrid wafer; and attaching the plurality of optical chips to different positions on the upper surface of the adapter plate includes: directly bonding the electronic-photonic hybrid wafer to the upper surface of the adapter plate.

In some embodiments, the aforementioned adapter board is an adapter board manufactured by the method described above, and the aforementioned one or more first optical waveguides are one or more layers of optical waveguides in the optical waveguide structure of the adapter board manufactured by the method described above.

In some embodiments, the aforementioned adapter board is an adapter board manufactured by the method described above, and the aforementioned one or more first optical waveguides are a three-dimensional waveguide network in the adapter board manufactured by the method described above and a coupling optical waveguide covering the optical input and output of the aforementioned three-dimensional waveguide network.

Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. Although some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure should not be construed as limited to the embodiments described herein; rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

It should be understood that the steps described in the method embodiments disclosed herein may be performed in different orders and/or concurrently. Furthermore, method embodiments may include other steps and/or omit certain steps.

This disclosure provides an adapter board for optical chip packaging. Figure 1 shows a cross-sectional view of the adapter board 100 for optical chip packaging according to this disclosure. Figure 5 shows a process flow diagram of the manufacturing method of the adapter board 100 according to this disclosure. To describe this disclosure more clearly, the specific structure and manufacturing method of the adapter board 100 will be described below with reference to Figures 1 and 5.

As shown in Figure 1, the adapter plate 100 can be divided into three layers in its overall structure, from bottom to top: dielectric layer 103, glass substrate 101, and optical waveguide structure 102.

The glass substrate 101 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 101-1 is shown in Figure 1. As shown in the figure, the conductive via 101-1 includes a via penetrating the glass substrate 101 and a conductive material filled within the via (shown as a horizontal shadow in the figure).

An optical waveguide structure 102 is disposed on a first surface (the upper surface as shown in the figure) of a glass substrate 101. Typically, the optical waveguide structure 102 includes one or more optical waveguides and a coating layer covering one or more of the optical waveguides. In Figure 1, for ease of description, only one optical waveguide 102-1 and the coating layer 102-2 covering this optical waveguide are shown. When multiple optical chips are packaged on the adapter board 100, the one or more optical waveguides in the optical waveguide structure 102 can be used to optically interconnect the multiple optical chips packaged thereon. The refractive index of one or more optical waveguides in the optical waveguide structure 102 is greater than the refractive index of the cladding layer 102-2 and the glass substrate 101. For example, the one or more optical waveguides can be silicon nitride optical waveguides with a higher refractive index, and the materials of the cladding layer 102-2 and the glass substrate 101 can be silicon dioxide with a relatively low refractive index.

As shown in Figure 1, the optical waveguide structure 102 further includes one or more first conductive structures 102-3 penetrating the optical waveguide structure, which are electrically connected to one or more conductive vias 101-1 in the glass substrate. The one or more first conductive structures 102-3 shown in the figure can be used for vertical electrical connections to optical or electronic chips packaged on an adapter board. The first conductive structure 102-3 can be a plug structure, such as a copper plug, and may also include other metallic or conductive materials.

A dielectric layer 103 is disposed on a second surface (the lower surface as shown in the figure) of the glass substrate 101, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 104 are disposed on the surface of the dielectric layer 103 away from the glass substrate 101 (i.e., the lower surface as shown in the figure), and are electrically connected to the one or more second conductive structures. For example, depending on the electrical connection requirements, the second conductive structure may include a redistribution layer 103-3 as shown in the figure and a lower via structure 103-2. The conductive bumps 104 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, etc. The conductive bump 104 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive bump 104 may be formed by first forming a solder layer using common methods such as evaporation, electroplating, or printing. In some embodiments, the conductive bump 104 is a metal pillar, such as a copper pillar, formed by sputtering, electroplating, or chemical plating.

It should be noted that the adapter board 100 may also exclude the dielectric layer 103 and the conductive bumps 104.

The above, together with Figure 1, depicts the specific structure of the adapter board 100 for optical chip packaging. The manufacturing method of the adapter board 100 will be explained in detail below with reference to Figure 5.

As shown in Figure 5, in step (a), a glass substrate 101 is first provided, and one or more conductive vias 101-1 are formed in the glass substrate 101. In some embodiments, the conductive vias 101-1 can be formed in the glass substrate 101 by etching and electroplating. For example, one or more vias can be formed in the glass substrate first by laser drilling, and then a conductive material layer can be formed on the inner surface of one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with a conductive metal to form conductive vias.

After forming a conductive via 101-1 in the glass substrate 101, in steps (b)-(c), an optical waveguide structure can be disposed on the first surface of the glass substrate 101 (the upper surface as shown in the figure). For example, as shown in (b)-(c), the optical waveguide structure includes one or more optical waveguides 102-1 and a coating layer 102-2 covering the one or more optical waveguides. For ease of description, only an example of a single-layer optical waveguide is shown in Figure 5.

Specifically, in step (b), for example, wafer-level nanoimprint optical lithography can be used to form an optical waveguide 102-1 on the first surface of the glass substrate 101.

It should be noted that, compared to prior art nanoimprinting techniques, the wafer-level nanoimprinting optical lithography technique disclosed herein offers the following improvements. To achieve wafer-level waveguide routing without the line size limitations of typical step-and-paste optical lithography, this disclosure utilizes wafer-level maskless optical lithography techniques, such as electron beam or laser writing. For example, an imprint master can first be fabricated using an oxide or nitride overlay, which is patterned using electron beam optical lithography. Then, by using this imprint master, a step-and-repeat operation is performed to generate a polymer-based nanoimprint (e.g., PDMS, polydimethylsiloxane) on a polymer. It should be noted that this nano-imprint is wafer-level, meaning that through the step-repeating operation described above, the entire optical waveguide pattern is formed completely and coherently within a single nano-imprint. Compared to traditional non-wafer-level imprints, when using the generated wafer-level nano-imprint on a nitride-deposited glass wafer for nano-imprinting, the photoresist pattern is transferred to the glass wafer in one step, facilitating the formation of a monolithic nitride waveguide. Traditional non-wafer-level imprints require multiple imprinting processes for waveguide splicing, which can easily lead to misalignment issues, affecting the quality of the optical waveguide and consequently causing optical signal loss.

Using the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing and minimizing optical signal loss.

Then, in step (c), a coating material is deposited over the optical waveguide 102-1 to form a coating layer 102-2. Depending on the specific needs, steps (b)-(c) can be repeated to form an optical waveguide structure with multiple layers. In addition, in step (c), one or more first conductive structures 102-3 penetrating the optical waveguide structure can be formed in the coating layer 102-2, and they can be electrically connected to one or more conductive vias 101-1 in the glass substrate 101 respectively.

As described above, the refractive index of the optical waveguide 102-1 is greater than that of the cladding layer 102-2 and the glass substrate 101. For example, the optical waveguide 102-1 can be a silicon nitride optical waveguide with a higher refractive index, and the materials of the cladding layer 102-2 and the glass substrate 101 can be silicon dioxide with a relatively lower refractive index.

Alternatively, the manufacturing method of the adapter plate 100 may further include: disposing a dielectric layer 103 on a second surface of a glass substrate 101, forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer 103 and electrically connecting them to one or more conductive vias 101-1 respectively, and disposing one or more conductive bumps 104 on the surface of the dielectric layer 103 away from the glass substrate.

Steps (d)-(f) in Figure 5 show exemplary detailed steps of the above processing flow.

For example, in step (d), a redistribution layer 103-3 can be formed on the bottom surface of the glass substrate 101 for electrical connection. Next, in step (e), a dielectric layer 103 is disposed on the bottom surface of the glass substrate 101, covering a portion of the redistribution layer 103-3 formed in (d). At the same time, a notch 103-4 corresponding to the redistribution layer 103-3 and the conductive via 101-1 needs to be formed in the dielectric layer 103. In step (f), a conductive via structure 103-2 is formed by filling the notch 103-4 with conductive material, so that the conductive via structure 103-2 is electrically connected to the redistribution layer 103-3 and the conductive via 101-1 in the glass substrate. In this case, the conductive via structure 103-2 and the redistribution layer 103-3 together constitute the aforementioned second conductive structure, which penetrates the dielectric layer 103 and is electrically connected to the conductive via 101-1 in the glass substrate 101.

In step (f), one or more conductive bumps 104 are disposed on the surface of the dielectric layer 103 away from the glass substrate, and the conductive bumps 104 are electrically connected to the second conductive structure (i.e., the conductive via structure 103-2 and the redistribution layer 103-3).

Thus far, the specific structure and manufacturing method of the adapter board 100 used in the first example of optical chip packaging have been described in conjunction with Figures 1 and 5. By configuring an optical waveguide structure on the surface of the glass substrate, optical interconnection can be achieved between optical chips packaged on this adapter board, thus avoiding the cost and process difficulty issues associated with manufacturing silicon adapter boards for embedded TSVs. Furthermore, since the optical waveguide is formed in the glass substrate using the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing in the middle and minimizing optical signal loss.

The specific structure and manufacturing method of another example of an adapter board for optical chip packaging will be described below with reference to Figures 2 and 6. Figure 2 shows a cross-sectional view of the adapter board 200 for optical chip packaging according to the embodiment of this disclosure. Figure 6 shows a process flow diagram of the manufacturing method of the adapter board 200 according to the embodiment of this disclosure.

As shown in Figure 2, the adapter plate 200 can be similarly divided into three layers in its overall structure, from bottom to top: dielectric layer 203, glass substrate 201, and optical coupling structure 202.

The glass substrate 201 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 201-1 is shown in Figure 2. As shown in the figure, the conductive via 201-1 includes a via penetrating the glass substrate 201 and a conductive material filling the via (shown as a horizontal shadow in the figure).

Furthermore, the glass substrate 201 also includes a three-dimensional waveguide network 201-2 (as shown in the figure), used for optical interconnection of multiple optical chips packaged on the adapter board 200. The three-dimensional waveguide network 201-2 is constructed by inducing local glass within the glass substrate 201 to increase the refractive index of the local glass, and it has a three-dimensional network structure formed by multiple channels distributed throughout the entire glass substrate 201. For example, an embedded three-dimensional waveguide network can be created within the glass substrate using an ultrafast (e.g., femtosecond) laser writing process.

An optical coupling structure 202 is disposed on a first surface (e.g., the upper surface) of a glass substrate 201. As shown in the figure, the optical coupling structure 202 includes a coupling optical waveguide 202-1 covering the optical input and output ports of a three-dimensional waveguide network 201-2, and a cladding layer 202-2 covering the coupling optical waveguide 202-1. Furthermore, the optical coupling structure 202 also includes one or more first conductive structures 202-3 penetrating the optical coupling structure, which are electrically connected to one or more conductive vias 201-1 in the glass substrate 201.

It should be noted that the refractive index of the coupling optical waveguide 202-1 can be lower than that of the three-dimensional waveguide network 201-2, but higher than that of the cladding layer 202-2. For example, the coupling optical waveguide 202-1 can be a silicon nitride optical waveguide, and the material of the cladding layer 202-2 can be silicon dioxide. Furthermore, it should be noted that although the adapter plate 200 includes an embedded optical waveguide 202-1 similar to that in the adapter plate 100 shown in Figure 1, their functions are different. In the adapter plate 100 shown in Figure 1, the optical waveguide 102-1 in the optical waveguide structure 102 is used for optical interconnection between different optical chips. However, in the adapter plate 200 shown in Figure 2, the coupling optical waveguide 202-1 in the optical coupling structure 202 is used for optical "coupling," which can improve the optical coupling efficiency between the three-dimensional waveguide network and the optical chip.

Similar to the adapter plate 100, the dielectric layer 203 in the adapter plate 200 is disposed on the second surface (lower surface as shown in the figure) of the glass substrate 201, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 204 are disposed on the surface of the dielectric layer 203 away from the glass substrate 201 (i.e., the lower surface as shown in the figure), which are electrically connected to the one or more second conductive structures. Depending on the electrical connection requirements, the second conductive structure may include a redistribution layer 203-3 as shown in the figure and a lower conductive via structure 203-2. The conductive bump 204 can be a controlled collapse chip connection (C4) bump, a ball grid array (BGA) connector, a solder ball, a metal pillar, a microbump, etc., which is similar to the conductive bump 104 shown in Figure 1, and will not be described in detail here.

It should be noted that the adapter board 200 may also exclude the dielectric layer 203 and the conductive bumps 204.

The above, together with Figure 2, depicts the specific structure of the adapter board 200 used for optical chip packaging. The manufacturing method of the adapter board 200 will be explained in detail below with reference to Figure 6.

As shown in Figure 6, in step (a), a glass substrate 201 is first provided, and a three-dimensional waveguide network 201-2 is formed within the glass substrate 201 for optical interconnection of multiple optical chips packaged on an adapter board. In some examples, an ultrafast (e.g., femtosecond) laser writing process can be used to create an embedded three-dimensional waveguide network within the glass substrate. For example, a femtosecond laser can be used to irradiate a predetermined location on the glass substrate 201 to increase the refractive index of the predetermined location, thereby forming the three-dimensional waveguide network 201-2. For example, the predetermined location could be the location where the three-dimensional waveguide network structure is formed.

Then, in step (b), one or more conductive vias 201-1 are formed in the glass substrate 201. In some embodiments, the conductive vias 201-1 can be formed in the glass substrate 201 by etching and electroplating. For example, one or more vias can be formed in the glass substrate first by laser drilling etching, and then a conductive material layer can be formed on the inner surface of one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with a conductive metal to form conductive vias.

After forming a conductive via 201-1 in the glass substrate 201, in steps (c)-(d), an optical coupling structure can be configured on the first surface of the glass substrate 201 (the upper surface as shown in the figure). For example, as shown in the figure, the optical coupling structure includes a coupling optical waveguide 202-1 and a coating layer 202-2 covering the coupling optical waveguide. Specifically, in step (c), optical lithography can be used to form the coupling optical waveguide 202-1 on the first surface of the glass substrate 201, so that it covers the light input and output ports of the three-dimensional waveguide network 201-2. Then, in step (d), a coating layer material is deposited over the coupling optical waveguide 202-1 to form the coating layer 202-2. In addition, in step (d), one or more first conductive structures 202-3 penetrating the optical coupling structure can be formed in the cladding layer 202-2, and electrically connected to one or more conductive vias 201-1 in the glass substrate 201 respectively.

It should be noted that the refractive index of the coupling optical waveguide 202-1 can be greater than the refractive index of the cladding layer 202-2 and the glass substrate 201. For example, the coupling optical waveguide 202-1 can be a silicon nitride optical waveguide with a higher refractive index, and the materials of the cladding layer 202-2 and the glass substrate 201 can be silicon dioxide with a relatively low refractive index.

Alternatively, the manufacturing method of the adapter plate 200 may further include: disposing a dielectric layer 203 on a second surface of a glass substrate 201, forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer 203 and electrically connecting them to one or more conductive vias 201-1 respectively, and disposing one or more conductive bumps 204 on the surface of the dielectric layer 203 away from the glass substrate.

Steps (e)-(g) in Figure 6 show example detailed steps of the above processing flow.

For example, in step (e), a redistribution layer 203-3 can be formed on the bottom surface of the glass substrate 201 for electrical connection. Next, in step (f), a dielectric layer 203 is disposed on the bottom surface of the glass substrate 201, covering a portion of the redistribution layer 203-3 formed in (e). At the same time, a notch 203-4 corresponding to the redistribution layer 203-3 and the conductive via 201-1 needs to be formed in the dielectric layer 203. In step (g), a conductive via structure 203-2 is formed by filling the notch 203-4 with conductive material, so that the conductive via structure 203-2 is electrically connected to the redistribution layer 203-3 and the conductive via 201-1 in the glass substrate. In this case, the conductive via structure 203-2 and the redistribution layer 203-3 together constitute the aforementioned second conductive structure, which penetrates the dielectric layer 203 and is electrically connected to the conductive via 201-1 in the glass substrate 201.

In step (g), one or more conductive bumps 204 are disposed on the surface of the dielectric layer 203 on the side away from the glass substrate, and the conductive bumps 204 are electrically connected to the second conductive structure (i.e., the conductive via structure 203-2 and the redistribution layer 203-3).

Thus far, the specific structure and manufacturing method of the adapter board 200 used in the second example of optical chip packaging have been described with reference to Figures 2 and 6. The adapter board 200 interconnects multiple optical chips packaged on top of it by forming a three-dimensional optical waveguide network inside the glass substrate. Therefore, a richer and more efficient three-dimensional optical waveguide path can be formed without increasing the thickness of the adapter board, effectively compressing the volume of the optical chip package. Furthermore, since silicon nitride coupled optical waveguides as described above are also configured at the light input and output of the three-dimensional optical waveguide network, the optical coupling efficiency between the optical chip and the adapter board can be greatly improved.

The specific structure and manufacturing method of another example of an adapter board for optical chip packaging will be described below with reference to Figures 3 and 7A. Figure 3 shows a cross-sectional view of the adapter board 300 for optical chip packaging according to the embodiment of this disclosure. Figure 7A shows a process flow diagram of the manufacturing method of the adapter board 300 according to the embodiment of this disclosure.

As shown in Figure 3, the adapter plate 300 can be divided into three layers in its overall structure, from bottom to top: dielectric layer 303, glass substrate 301, and electrical interconnection structure 302.

Similarly, the glass substrate 301 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 301-1 is shown in Figure 3. As shown in the figure, the conductive via 301-1 includes a via penetrating the glass substrate 301 and a conductive material filled within the via (shown as a horizontal shadow in the figure).

An electrical interconnection structure 302 is disposed on a first surface (the upper surface as shown in the figure) of a glass substrate 301. In some examples, the electrical interconnection structure 302 may include one or more wiring layers 302-1a, 302-1b, 302-1c and a coating layer 302-2 covering one or more wiring layers. For example, the coating layer 302-2 may be a dielectric material, and the one or more wiring layers 302-1a, 302-1b, 302-1c are used to electrically interconnect multiple electronic chips on an optical chip packaged on an adapter board. The electronic chips may be vertically packaged with the optical chip, i.e., the electronic chips are packaged on the optical chip, and the electronic chips may be electrically connected to the aforementioned wiring layers through conductive vias in the optical chip to achieve electrical interconnection of the electronic chips. Furthermore, the optical chips configured on the adapter board can be active optical chips, and the active optical chips can also be electrically connected to each other through the aforementioned electrical interconnection structure 302.

Figure 3 shows an example of an electrical interconnect structure 302 with three wiring layers (302-1a, 302-1b, 302-1c). As shown in the figure, each wiring layer is covered by its own coating layer. For example, wiring layer 302-1a is covered by a multilayer structure formed by alternating stacks of silicon nitride layer 302-2a and silicon dioxide layer 302-2b. Wiring layers 302-1b and 302-1c are similarly covered by a multilayer structure formed by alternating stacks of silicon nitride layer and silicon dioxide layer. It should be understood that the three wiring layers shown in Figure 3 are merely exemplary, and more (e.g., four or more) or fewer (e.g., two or one) wiring layers can be selected as needed.

In addition, as shown in the figure, the electrical interconnection structure 302 also includes one or more first conductive structures 302-3 that penetrate the electrical interconnection structure, which are electrically connected to one or more conductive vias 301-1 in the glass substrate.

Figure 3 also shows a second conductive structure 302-4 for electrically connecting at least two of the multilayer wiring layers. The second conductive structure 302-4 may be formed using methods or materials similar to those used for the first conductive structure 302-3, for example, it may be a conductive via or a copper plug, or it may include other metallic or conductive materials.

A dielectric layer 303 is disposed on the second surface (lower surface as shown in the figure) of the glass substrate 301, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 away from the glass substrate 301 (i.e., the lower surface as shown in the figure), which are electrically connected to the one or more second conductive structures. Depending on the electrical connection requirements, the second conductive structure may include a redistribution layer 303-3 as shown in the figure and a lower conductive via structure 303-2. The conductive bumps 305 may be controlled-collapse chip interconnect (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, etc. The conductive bump 305 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive bump 305 may be formed by first forming a solder layer using common methods such as evaporation, electroplating, or printing. In some embodiments, the conductive bump 305 is a metal pillar, such as a copper pillar, formed by sputtering, electroplating, or chemical plating.

It should be noted that the adapter board 300 may also exclude the dielectric layer 303 and the conductive bump 305.

The above, together with Figure 3, depicts the specific structure of the adapter board 300 used for optical chip packaging. The manufacturing method of the adapter board 300 will be explained in detail below with reference to Figure 7A.

As shown in Figure 7A, in step (a), a glass substrate 301 is first provided, and one or more conductive vias 301-1 are formed in the glass substrate 301. In some embodiments, the conductive vias 301-1 can be formed in the glass substrate 301 by etching and electroplating. For example, one or more vias can be formed in the glass substrate first by laser drilling, and then a conductive material layer can be formed on the inner surface of one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with a conductive metal to form conductive vias.

In step (e), an electrical interconnection structure 302 is disposed on a first surface of the glass substrate 301 (i.e., the upper surface as shown in the figure). As shown in the figure, the electrical interconnection structure 302 includes one or more wiring layers (302-1a, 302-1b, 302-1c) and a coating layer covering one or more wiring layers. For example, the coating layer may be a dielectric material, and the one or more wiring layers (302-1a, 302-1b, 302-1c) are used to electrically interconnect multiple electrical chips above the optical chip packaged on the adapter board.

Figure 7A shows an example of an electrical interconnect structure 302 with three wiring layers (302-1a, 302-1b, 302-1c). As shown in the figure, each wiring layer is covered by its own coating layer. For example, wiring layer 302-1a is covered by a multilayer structure formed by alternating stacks of silicon nitride layer 302-2a and silicon dioxide layer 302-2b. Wiring layers 302-1b and 302-1c are similarly covered by a multilayer structure formed by alternating stacks of silicon nitride layer and silicon dioxide layer. It should be understood that the three wiring layers shown in Figure 3 are merely exemplary, and more (e.g., four or more) or fewer (e.g., two or one) wiring layers can be selected as needed.

Specifically, taking Figure 7A(e) as an example, configuring the electrical interconnection structure 302 on the first surface of the glass substrate 301 may include the following specific steps: First, a first wiring layer (wiring layer 302-1a) is configured on the upper surface of the glass substrate 301; then, a first silicon nitride layer (silicon nitride layer 302-2a) is formed around the first wiring layer (wiring layer 302-1a). The thickness of the first silicon nitride layer (302-2a) is less than the thickness of the first wiring layer (302-1a); then, a first silicon dioxide layer (302-2b) is covered on the first silicon nitride layer (302-2a), such that the total thickness of the first silicon nitride layer (302-2a) plus the first silicon dioxide layer (302-2b) is equal to the thickness of the first wiring layer (302-1a). Subsequently, depending on specific needs, the above steps can be repeated to sequentially arrange the second wiring layer (wiring layer 302-1b) on the first silicon oxide layer (silicon dioxide layer 302-2b), form the second silicon nitride layer around the second wiring layer (wiring layer 302-1b), cover the second silicon oxide layer on the second silicon nitride layer, and so on, to form an electrical interconnection structure with multiple wiring layers.

Furthermore, configuring the electrical interconnection structure 302 on the first surface of the glass substrate 301 may also include forming a second conductive structure 302-4 between the first wiring layer (wiring layer 302-1a) and the second wiring layer (wiring layer 302-1b) to electrically connect the first wiring layer (wiring layer 302-1a) and the second wiring layer (wiring layer 302-1b). For example, one or more vias may first be formed by laser drilling at the locations of the wiring layers in the electrical interconnection structure 302, and then a conductive material layer may be disposed on the inner surface of one or more vias to form one or more second conductive structures 302-4. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with conductive metal to form a second conductive structure 302-4. Furthermore, as shown in the figure, in the case where the electrical interconnection structure 302 includes three wiring layers (302-1a, 302-1b, 302-1c), the second conductive structure 302-4 also exists between the second wiring layer (wiring layer 302-1b) and the third wiring layer (wiring layer 302-1c), and electrically connects the second wiring layer (wiring layer 302-1b) and the third wiring layer (wiring layer 302-1c).

Furthermore, the arrangement of the electrical interconnection structure 302 on the first surface of the glass substrate 301 may also include: forming one or more first conductive structures 302-3 that penetrate the electrical interconnection structure in the electrical interconnection structure 302, which are electrically connected to one or more first conductive vias 301-1 in the glass substrate 301 respectively.

Alternatively, in some embodiments, the manufacturing method of the adapter plate 300 may further include: disposing a dielectric layer 303 on the second surface of the glass substrate 301, forming one or more fourth conductive structures penetrating the dielectric layer in the dielectric layer 303 and electrically connecting them to one or more conductive vias 301-1 respectively, and disposing one or more conductive bumps 305 on the surface of the dielectric layer 303 away from the glass substrate.

Steps (b)-(d) in Figure 7A show the detailed steps of the above processing procedure.

For example, in step (b), a redistribution layer 303-3 can be formed on the second surface of the glass substrate 301 for electrical connection. Next, in step (c), a dielectric layer 303 is disposed on the bottom surface of the glass substrate 301, covering a portion of the redistribution layer 303-3 formed in (b). At the same time, a notch 303-4 corresponding to the redistribution layer 303-3 and the conductive via 301-1 needs to be formed in the dielectric layer 303. In step (d), a conductive via structure 303-2 is formed by filling the notch 303-4 with conductive material, so that the conductive via structure 303-2 is electrically connected to the redistribution layer 303-3 and the conductive via 301-1 in the glass substrate. In this case, the conductive via structure 303-2 and the redistribution layer 303-3 together constitute the aforementioned fourth conductive structure, which penetrates the dielectric layer 303 and is electrically connected to the conductive via 301-1 in the glass substrate 301.

In step (d), one or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 on the side away from the glass substrate, and the conductive bumps 305 are electrically connected to the fourth conductive structure (i.e., the conductive via structure 303-2 and the redistribution layer 303-3).

Thus far, the specific structure and manufacturing method of the adapter board 300 for the first example of optical chip packaging have been described in conjunction with Figures 3 and 7A. By configuring an electrical interconnection structure on the surface of the glass substrate, electrical interconnection can be achieved between the electronic chips above the optical chip packaged on this adapter board.

The specific structure and manufacturing method of another example of an adapter board for optical chip packaging will be described below with reference to Figure 4 and Figures 7A-7B. Figure 4 shows a cross-sectional view of an adapter board 400 for optical chip packaging according to an embodiment of the present disclosure. Figures 7A-7B show process flow diagrams of the manufacturing method of the adapter board 400 according to an embodiment of the present disclosure.

As shown in Figure 4, the adapter board 400 can be divided into four layers in its overall structure, from bottom to top: dielectric layer 303, glass substrate 301, electrical interconnection layer 302, and optical waveguide structure 304. The configuration and function of dielectric layer 303, glass substrate 301, and electrical interconnection layer 302 are similar to those of the adapter board 300 shown in Figure 3, and will not be described in detail here.

Compared to the adapter plate 300 shown in Figure 3, the adapter plate 400 shown in Figure 4 additionally includes an optical waveguide structure 304. As shown, the optical waveguide structure 304 is disposed on the surface (i.e., the upper surface) of the electrical interconnection structure 302 on the side away from the glass substrate 301. In some examples, the optical waveguide structure 304 may include one or more layers of optical waveguides 304-1 and a surrounding layer 304-2 surrounding the one or more layers of optical waveguides 304-1. It should be noted that, for the sake of simplicity, only an example of an optical waveguide structure with one layer of optical waveguide 304-1 is shown in Figure 4, but this is merely exemplary, and two, three, or more layers of optical waveguides may be configured as needed. As shown in the figure, the optical waveguide 304-1 is used to optically interconnect multiple optical chips packaged on the adapter board 400, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the cladding layer 304-2.

In addition, as shown in the figure, the optical waveguide structure 304 also includes one or more third conductive structures 304-3 that penetrate the optical waveguide structure and are electrically connected to one or more first conductive structures in the electrical interconnection structure 302.

The manufacturing method of the adapter plate 400 shown in Figure 4 includes steps (a)-(e) as shown in Figure 7A, as well as step (f) as shown in Figure 7B. Steps (a)-(e) have been described in detail in the manufacturing method of the adapter plate 300, and will not be repeated here.

After forming the adapter plate 400, which includes the electrical interconnection structure 302 as shown in Figure 7A(e), the method of manufacturing the adapter plate 400 further includes, in step (f), disposing an optical waveguide structure 304 on the surface of the electrical interconnection structure 302 away from the glass substrate 301. As described above with respect to Figure 4, the optical waveguide structure 304 may include one or more optical waveguides 304-1 and a surrounding layer 304-2 surrounding the one or more optical waveguides 304-1. The optical waveguide structure 304 can be formed using a similar technique as described with respect to Figure 5. For example, a cladding layer material can be deposited first on the electrical interconnect structure 302, and then an optical waveguide 304-1 can be formed on the deposited cladding layer material using wafer-level nanoimprint lithography. Then, a cladding layer material can be deposited again on the optical waveguide 304-1 to completely surround it, forming a cladding layer 304-2. For simplicity, only an example of an optical waveguide structure with a single optical waveguide 304-1 is shown in Figure 7B, but this is merely exemplary, and two, three, or more optical waveguides can be configured as needed. The aforementioned one- or multi-layer optical waveguide 304-1 is used to optically interconnect multiple optical chips packaged on an adapter board, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the cladding layer 304-2. For example, the one- or multi-layer optical waveguide 304-1 can be a silicon nitride optical waveguide, and the material of the cladding layer 304-2 is silicon dioxide.

Similarly, it should be noted that the method for forming the optical waveguide 304-1, compared to the nanoimprinting techniques in the prior art, employs a wafer-level nanoimprinting optical lithography technique with the following improvements. To achieve wafer-level waveguide wiring without the line size limitations of typical step-and-paste optical lithography, this disclosure uses wafer-level maskless optical lithography techniques, such as electron beam or laser writing. For example, an imprint master can first be fabricated using an oxide or nitride overlay, which is patterned using electron beam optical lithography. Then, by using this imprint master, a step-and-repeat operation is performed to generate a polymer-based nanoimprint (e.g., PDMS, polydimethylsiloxane) on a polymer. It should be noted that this nano-imprint is wafer-level, meaning that through the step-repeat operation described above, the entire optical waveguide pattern is formed completely and coherently within a single nano-imprint. Compared to traditional non-wafer-level imprints, when using the generated wafer-level nano-imprint on a nitride-deposited glass wafer for nano-imprinting, the photoresist pattern is transferred to the glass wafer in one step, facilitating the formation of a monolithic nitride waveguide. Traditional non-wafer-level imprints require multiple imprinting processes for waveguide splicing, which can easily lead to misalignment issues, affecting the quality of the optical waveguide and consequently causing optical signal loss.

Using the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing and minimizing optical signal loss.

In addition, the manufacturing method of the adapter board 400 may also include: in step (f), forming one or more third conductive structures 304-3 that penetrate the optical waveguide structure 304, and electrically connecting them to one or more first conductive structures in the electrical interconnection structure 302 respectively.

Thus far, the specific structure and manufacturing method of the adapter board 400 used in the first example of optical chip packaging have been described in conjunction with Figures 4 and 7A-7B. By arranging an electrical interconnection structure on the surface of a glass substrate and arranging an optical waveguide structure on the electrical interconnection structure, electrical interconnection can be achieved between electronic chips packaged on this adapter board, and optical interconnection can be achieved between optical chips packaged on this adapter board. Furthermore, through the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing in the middle, and minimizing optical signal loss.

It should be understood that the various steps described in the method embodiments and diagrams disclosed herein may be performed in different sequences and/or concurrently as needed. Furthermore, method embodiments may include other steps and/or omit certain steps.

It should be noted that, in the above description of the adapter board, although the corresponding conductive structure and its manufacturing method are described for each layer of the adapter board (e.g., the optical waveguide structure 102 and the dielectric layer 103 in Figure 1), such as the first conductive structure 102-3 in the optical waveguide structure 102 and the second conductive structure 103-2 in the dielectric layer 103 in Figure 1, in some embodiments, these conductive structures do not need to be separate and can be integrally formed. For example, the first conductive structure 102-3 and the second conductive structure 103-2 in the dielectric layer 103 can be integrally formed copper plugs that run through the entire adapter board 100. Such integrally formed copper plugs are also applicable to other adapter boards as shown in Figures 2-4.

The above describes some embodiments of the structure and manufacturing method of the glass wafer-based interposer disclosed herein. Compared with silicon interposers with embedded TSVs, the glass wafer-based interposer has a simpler structure, lower manufacturing cost, and is easier to implement. It can also be effectively used for optical interconnection of optoelectronic chips and electrical interconnection of electrical chips, providing a good platform for the integration of optoelectronic chips.

By using the adapter boards in the various embodiments described above, a compact, three-dimensional package structure including optical chips and electronic chips can be realized. Figures 8-11 show cross-sectional views of various optical chip package structures incorporating the adapter boards in the embodiments disclosed herein.

As shown in Figure 8, the package structure 800 includes an adapter board 100 and an optical chip 500. For example, the adapter board 100 can be an adapter board 100 with embedded optical waveguides as shown in Figure 1. This adapter board 100 can be used to optically interconnect optical chips in multiple photonic-electronic hybrid chips disposed thereon, and to electrically interconnect electrical chips in multiple photonic-electronic hybrid chips. Preferably, the optical chip is fabricated on an SOI (silicon on insulator) substrate. After the front-end fabrication process of the optical chip is completed, the bottom silicon substrate in the SOI substrate is removed, and the thickness of the buried oxide layer is controlled. The optical chip is then bonded to the adapter board 100. Optical signals are thermally coupled to the optical waveguides on the optical chip through the embedded optical waveguides on the adapter board 100, and vice versa, thereby realizing on-chip optical network communication. It should be understood that, for the sake of simplicity, only one optical chip 500 is shown in Figure 8. In actual applications, two or more optical chips can be configured on the adapter board 100, and they are optically interconnected through embedded optical waveguides in the adapter board 100. Furthermore, as shown in the figure, the optical chip 500 also includes one or more interconnection structures 501, each including vias penetrating the optical chip and conductive material filling the vias. As shown in the figure, the interconnection structure 501 is electrically connected to one or more first conductive structures 102-3 on the adapter board 100 as described above.

In some examples, the package structure 800 may also include one or more optical wafers, each with one or more electronic chips (EICs in Figures 8-11). Typically, one or more electronic chips (EICs) are positioned above the optical wafer 500 and are vertically electrically connected to the conductive structures in the adapter board via conductive structures in the electronic chips (such as UBM (under bump metallization) or other connection structures, such as direct bonding).

Figures 9 through 11 show example structures of the adapter boards corresponding to Figures 2 through 4 applied to the packaging of optical chips. The optical chip 500 is similar to the optical chip in Figure 8 and will not be described further here. It should be noted that, as shown in Figure 10, when the adapter board 300 with the electrical interconnection structure shown in Figure 3 is applied to the packaging structure 1000, the interconnection structure 501 in the optical chip 500 can be electrically connected to the conductive structures 302-3 in the electrical interconnection layer of the adapter board 300.

Furthermore, as mentioned above, the conductive structures in each layer of the adapter board are not necessarily separate, but can be integrally formed. For example, the conductive structures in each layer can be integrally formed copper plugs that run through the entire adapter board, which facilitates electrical connection between the adapter board and the electronic chip.

It should be noted that in the adapter boards described above in conjunction with Figures 1-2 and 4, optical waveguides are configured for optically interconnecting multiple optical chips disposed on the adapter board. Examples include optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, and optical waveguide 304-1 in Figure 4. Optical coupling between the optical waveguides and optical chips in the adapter board can be achieved, for example, by using external optical fibers; however, this method occupies a large space, which is detrimental to the miniaturization of the package structure. The embodiments disclosed herein propose using thermally adiabatic coupling to couple the optical chips to the optical waveguides in the adapter board, thereby achieving product miniaturization. Various embodiments of optical chip package structures and manufacturing methods employing this thermally adiabatic coupling technology for optical waveguides will be described in detail below. It should be noted that, in this disclosure, the adapter board used for thermal coupling is not limited to the adapter board mentioned above, but can be any adapter board capable of realizing optical interconnection of optical chips.

Figures 12A and 12B show a cross-sectional view and a top view of the optical chip package structure 1200 of the embodiment disclosed herein, respectively.

As shown in Figure 12A, the optical chip package structure 1200 includes a transition board 1210 and multiple optical chips (PICs) disposed on the transition board 1210. Typically, the optical chips are fabricated using an SOI substrate, and the optical waveguides in the optical chips are disposed on the buried oxide layer of the SOI substrate. For example, since Figure 12A shows a cross-sectional view cut from a specific location, only two optical chips, PIC 1 and PIC 2, are visible in Figure 12A. However, in reality, as shown in the top view of Figure 12B, the optical chip package structure 1200 may include six optical chips, PIC 1 through PIC 6. It should be understood that the above six optical chips are merely exemplary and not limiting; in actual applications, the optical chip package structure 1200 may include more or fewer optical chips.

As shown in Figure 12A, the optical chip package structure 1200 includes one or more first optical waveguides embedded therein, such as optical waveguides WG1-1 and WG1-2 shown in Figure 12A. Optical waveguides WG1-1 and WG1-2 can be a waveguide network formed by an array of multiple optical waveguides. Optical waveguides WG1-1 and WG1-2 can be optical waveguides in the aforementioned adapter board, such as optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, or optical waveguide 304-1 in Figure 4. Furthermore, the material of optical waveguides WG1-1 and WG1-2 can be silicon nitride as described above, with a silicon oxide cladding layer covering the silicon nitride.

Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity, only a single optical waveguide is shown for each PIC in Figure 12A), namely optical waveguide WG2-1 and optical waveguide WG2-2. In some examples, the material of optical waveguide WG2-1 and optical waveguide WG2-2 may be silicon. As shown in Figure 12B, multiple optical chips (PIC 1, ..., PIC 6) are attached to different locations on the upper surface of the adapter plate 1210. As shown, PIC 1-PIC 6 are attached to different locations in the square region R1 on the adapter plate 1210 and are spaced apart from each other.

Optical interconnects can be established between any two of the optical chips PIC 1 and PIC 2, or any two of the plurality of optical chips (PIC 1, ..., PIC 6) as shown in Figure 12B, via one or more first optical waveguides in the adapter board 1210. For example, as shown by the dashed arrow in Figure 12A, light can originate from PIC 1, then be coupled through optical waveguide WG2-1 to optical waveguide WG1-1 in the adapter board 1210, then be transmitted via another optical waveguide network (not shown) to optical waveguide WG1-2, and then be coupled again to optical waveguide WG2-1 in PIC 2. Specifically, each first optical waveguide may include a first optical coupling portion, and each second optical waveguide may include a second optical coupling portion (not shown in the figure). For simplicity, the ends of, for example, optical waveguides WG2-1 and WG1-1 can be considered as their respective optical coupling portions. For example, the optical coupling sections of optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and spaced apart by a predetermined distance (e.g., less than 600 nm), enabling thermally adiabatic coupling between the optical coupling sections of optical waveguides WG2-1 and WG1-1. Of course, optical chips PIC1 and PIC2 can also be optically interconnected through a first optical waveguide; for example, optical waveguides WG1-1 and WG1-2 in Figure 12A can be different parts of a single first optical waveguide. In the case of multiple first optical waveguides, different first optical waveguides can achieve optical interconnection between different optical chips. For example, one first optical waveguide can be used to connect PIC1 and PIC2, and another first optical waveguide can be used to connect PIC1 and PIC3 or PIC3 and PIC4.

Figures 13 and 14 show schematic side and top views of the optical coupling portion in the optical chip package structure 1200 of the present disclosure, respectively, and corresponding diagrams of the optical mode field.

As shown in Figure 13, the coupling part of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling part of the optical waveguide WG1-1 in the adapter board are stacked one on top of the other and spaced apart by a predetermined distance H.

Furthermore, to achieve high coupling efficiency, as shown in Figure 14, the coupling portions of optical waveguide WG2-1 in the optical chip PIC 1 and optical waveguide WG1-1 in the adapter board can have tapered shapes. Ideally, the coupling portions of optical waveguide WG2-1 in the optical chip PIC 1 and optical waveguide WG1-1 in the adapter board (i.e., the two tapered shapes shown in Figure 14) should be aligned in both the horizontal and vertical directions to obtain maximum coupling efficiency. However, in actual manufacturing, due to process limitations, it is not possible to achieve perfect alignment of the coupling portions of optical waveguide WG2-1 in the optical chip PIC 1 and optical waveguide WG1-1 in the adapter board in both the horizontal and vertical directions. Typically, there will be horizontal misalignment LM and vertical misalignment TM as shown in Figure 14.

Taking an optical chip substrate of SOI and an optical waveguide on a transition plate of SiN as an example, the main parameters that have a significant impact on the coupling efficiency between the optical chip and the transition plate are as follows: the width W4 of the optical waveguide WG1-1 in the transition plate, the length L of the coupling part of the optical waveguide WG2-1 and the coupling part of the optical waveguide WG1-1, the predetermined distance H, and the thickness tSiN of the optical waveguide WG1-1.

For the width W4 of the optical waveguide WG1-1 in the adapter board, the wider W4 is, the better the coupling effect, while ensuring that the optical waveguide WG1-1 is a single-mode waveguide. Preferably, W4 < 1μm can be selected, because if it is greater than 1μm, it is easy to become a multimode waveguide.

For the length L of the coupling part, the longer L is, the better the coupling effect. Figure 15 shows the relationship between the coupling efficiency and lateral misalignment for different L values when W4 = 1 μm and H = 200 nm. When L = 200 μm, the coupling loss can be controlled within 1 dB when the lateral misalignment is 1 μm. When L = 1800 μm, the coupling loss can also be controlled within 1 dB when the lateral misalignment is 1.5 μm.

For the predetermined distance H between the coupling parts of optical waveguide WG2-1 and optical waveguide WG1-1, the smaller H is, the better the coupling effect. However, H includes the thickness of the buried oxide layer in the SOI of the optical chip after thinning, plus the thickness of the silicon oxide covering the silicon nitride waveguide in the adapter plate. If H is set too small, the buried oxide layer in the SOI needs to be thinner. Due to the limitations of the thinning process, the thickness of the buried oxide layer will be uneven, which will affect the coupling efficiency. Therefore, preferably, H = 100nm-600nm. Figure 16 shows the relationship between coupling efficiency and lateral misalignment for different H values when W4 = 1μm, L = 200μm, and tSiN = 200nm. It can be seen that the coupling effect is best at around H=200nm. When the spacing is greater than 200nm, the larger the spacing, the greater the decrease in coupling efficiency under the same lateral misalignment.

For the thickness tSiN of the optical waveguide WG1-1, too small a tSiN thickness will lead to uneven waveguide thickness, while too large a thickness will cause cracking due to internal stress. Therefore, tSiN = 100nm-300nm is preferable. Figure 17 shows the relationship between coupling efficiency and lateral misalignment for different tSiN thicknesses when W4 = 1μm, L = 200μm, and H = 200nm. The figure shows that the coupling effect is optimal when tSiN = 200nm.

In addition to the tapered coupling portion as described above, in some embodiments, the coupling portion of the optical waveguide of the optical chip and the coupling portion of the optical waveguide of the adapter plate can have a shape formed by two tapered shapes of different sizes connected in series. Figures 18 and 19 show schematic diagrams of such coupling portions having a shape formed by two tapered shapes of different sizes (S1-1, S1-2, S2-1, S2-2) connected in series, and diagrams of the corresponding optical mode fields, respectively.

As shown in Figure 19, compared with the previous tapered structure, the coupling part of the optical waveguide of the optical chip and the coupling part of the optical waveguide of the adapter plate have an additional tapered transition structure with a length of L_taper. That is, the optical coupling part has evolved from a single tapered structure to a structure formed by two tapered structures connected in series. The reason for adding the aforementioned tapered transition structure is that there is an overlap point between the silicon waveguide (optical waveguide WG2-1) and the silicon nitride waveguide (optical waveguide WG1-1) at a length of approximately 700 nm for the silicon waveguide (optical waveguide WG2-1) and approximately 300 nm for the silicon nitride waveguide (optical waveguide WG1-1), for example, at the position indicated by the dashed line in Figure 19. The dielectric constants (n _{eff_Si} , n _{eff_SiN} ) are also present. At this overlap point, the two can couple quickly. Furthermore, the coupling length L_trans of this structure can be significantly reduced compared to the previous tapered structure, and optical coupling can be completed with approximately 10 μm. Furthermore, under the same conditions, silicon waveguides (optical waveguide WG2-1) and silicon nitride waveguides (optical waveguide WG1-1) can also allow for larger angular longitudinal alignment misalignment (the previous tapered structure required the two waveguides to have a very small angular alignment error in the parallel direction) and lateral alignment misalignment.

The above description, in conjunction with Figures 12A-19, illustrates an embodiment of the optical chip packaging structure disclosed herein. In this embodiment, by controlling the spacing between the optical waveguides in the optical chip and the optical waveguides on the adapter board, and by changing the structure of the coupling portion of the two waveguides, multiple optical chips can be optically connected to the adapter board via thermal coupling, and further, optical interconnection between multiple optical chips can be achieved through the optical waveguide network on the adapter board. Compared to external interconnection methods such as fiber arrays, this packaging structure using thermal coupling technology to optically interconnect multiple optical chips can significantly reduce the volume of the packaging structure.

Alternatively, an electronic chip can be configured in the packaging structure described above to form an optical chip packaging structure capable of realizing electrical operations (such as logical calculations, memory, etc.).

Figures 20 and 21 show a cross-sectional view and a top view, respectively, of an optical chip package structure 2000 containing an electronic chip according to an embodiment of the present disclosure.

As shown in Figure 20, in addition to the adapter board 1210 and optical chips PIC 1 and PIC 2, which are similar to those in Figures 12A-12B, the optical chip package structure 2000 also includes multiple electronic chips disposed on multiple first optical chips among multiple optical chips, for example, EIC 1 and EIC 2 disposed on PIC 1 and PIC 2 respectively. Alternatively, as shown in Figure 21, EIC 1, EIC 2, EIC 5, and EIC 6 disposed on PIC 1, PIC 2, PIC 5, and PIC 6 respectively. It should be noted that Figure 20 can be regarded as a cross-sectional view taken from the location of the optical chip package structure 2000 shown in Figure 21, penetrating EIC 1 and EIC 2. In Figure 21, PIC 1, PIC 2, PIC 5, and PIC 6 are already covered by their corresponding EICs 1, 2, 5, and 6, respectively, and therefore are not displayed. Furthermore, as shown in Figure 21, it is not necessary to set a corresponding EIC for each PIC; for example, EICs may not be configured above PIC 3 and PIC 4 if needed.

Specifically, each first optical chip (e.g., PIC 1 and PIC 2 as shown in Figure 20) may have one or more first electrical connectors on its upper surface, and each electronic chip (e.g., EIC 1 and EIC 2 as shown in Figure 20) may have one or more second electrical connectors on its lower surface, and one or more first electrical connectors are electrically connected to one or more second electrical connectors respectively, thereby realizing the connection between PIC and EIC.

Figures 22 and 23 show cross-sectional views of the optical chip and electronic chip in the optical chip package structure of the embodiments disclosed herein.

As shown in Figure 22(a), the upper surface of the PIC has a plurality of first electrical connectors C1, and the lower surface of the EIC has a plurality of second electrical connectors C2. The PIC and the EIC are directly connected through the first electrical connectors C1 and the second electrical connectors C2.

In some examples, the first optical chip (i.e., the PIC on which the EIC is configured) also includes one or more second conductive vias, such as through dielectric vias (TDVs) as shown in Figure 22(a), through which electrical connections between the EIC and the adapter board can be realized, for example, by connecting the TDV shown to the conductive structure of the adapter board as previously shown, which will be described in detail later in the introduction of Figures 24-25.

Figure 22(a) shows a schematic diagram of a single EIC configured on a PIC. In other embodiments, multiple EICs can be configured on a PIC. For example, as shown in Figure 22(b), analog chip A-EIC and digital chip D-EIC can be configured on a PIC simultaneously. Depending on the needs, multiple analog chip A-EICs, multiple digital chip D-EICs, or multiple analog chip A-EICs and multiple digital chip D-EICs can also be configured on a PIC. In the case where multiple EICs are configured on the same PIC, each EIC is connected to the conductive structure of the adapter board via TDV as described above to achieve electrical connection between the two.

In addition to direct bonding as described above, optical ICs and electronic ICs can also be bonded using a flip-chip method. Figure 23 shows an optical IC and an electronic IC bonded using a flip-chip method. In this example, instead of direct bonding, a traditional flip-chip process is used, connecting the EIC and PIC via copper pillars, and using underfill for curing between the EIC and PIC. Figure 23(a) shows an example of a PIC with only one flip-chip EIC, and (b) shows an example of a PIC with one D-EIC and one A-EIC flip-chip. Similarly, multiple analog circuit chips (A-EICs) can be flip-chipped onto a single PIC, multiple digital circuit chips (D-EICs) can be flip-chipped onto a single PIC, or multiple analog circuit chips (A-EICs) and multiple digital circuit chips (D-EICs) can be flip-chipped onto a single PIC. When multiple EICs are flip-chipped onto the same PIC, each EIC is connected to the conductive structure of the adapter board via TDV as described above to achieve electrical connection between the two.

To more clearly reveal the optical chip packaging structure of this disclosure, Figures 24 and 25 show cross-sectional views of the optical chip packaging structure of the embodiments disclosed herein. However, it should be noted that, for further detail, only one PIC and one EIC are shown in Figures 24 and 25. Specifically, Figure 24 shows a cross-sectional view of an optical chip packaging structure using an adapter board as shown in Figure 1. Figure 25 shows a cross-sectional view of an optical chip packaging structure using an adapter board as shown in Figure 4.

As shown in Figure 24, when using the adapter board as shown in Figure 1, the entire package structure can be divided into three layers from bottom to top: the layer containing the adapter board 1210, the layer containing the PIC, and the layer containing the EIC. For example, in Figure 24, the entire package structure is divided into three layers by two parallel dashed lines. The dashed line between the EIC and the PIC defines the connection interface IF1 between the EIC and the PIC, and the dashed line between the PIC and the adapter board 1210 defines the connection interface IF2 between the PIC and the adapter board 1210. It should be understood that the above division is only for the purpose of more clearly describing the invention, and not for limiting the invention to the three-layer structure described above.

Assuming the optical chip PIC shown in Figure 24 is PIC 1 as shown in Figure 20, then the EIC disposed on it corresponds to EIC 1 as shown in Figure 20. In this case, the optical waveguide WG2-1 in the optical chip PIC can be seen located near the lower surface of the optical chip PIC and covered by a transparent dielectric layer (e.g., a buried silicon oxide layer). The optical waveguide WG1-1 in the adapter 1210 is located on the upper surface of the adapter 1210 and is also covered by a coating layer (e.g., a silicon oxide layer). The optical chip PIC has a through-hole conductive via TDV, and this conductive via TDV in the optical chip PIC is electrically connected to the conductive structure CC in the adapter 1210. For example, in the case where the adapter plate 1210 in Figure 24 is similar to the adapter plate 100 shown in Figure 1, the optical waveguide WG1-1 can correspond to the optical waveguide 102-1 in the adapter plate 100 shown in Figure 1, and the conductive structure CC can correspond to the first conductive structure 102-3 in the adapter plate 100 shown in Figure 1.

Similarly, as shown in Figure 25, when using the adapter board as shown in Figure 4, the entire package structure can also be divided into three layers from bottom to top: the layer containing the adapter board 1210, the layer containing the PIC, and the layer containing the EIC. For example, in Figure 25, the entire package structure is also divided into three layers using two parallel dashed lines. The dashed line between the EIC and the PIC defines the connection interface IF1 between the EIC and the PIC, and the dashed line between the PIC and the adapter board 1210 defines the connection interface IF2 between the PIC and the adapter board 1210. It should also be understood that the above division is only for the purpose of more clearly describing the invention, and not for limiting the invention to the three-layer structure described above.

Similarly, assuming the optical chip PIC shown in Figure 25 is PIC 1 as shown in Figure 20, then the EIC disposed on it corresponds to EIC 1 as shown in Figure 20. In this case, the optical waveguide WG2-1 in the optical chip PIC can be seen located near the lower surface of the optical chip PIC and covered by a dielectric layer (e.g., silicon oxide layer). The optical waveguide WG1-1 in the adapter 1210 is located on the upper surface of the adapter 1210 and is also covered by a coating layer (e.g., silicon oxide layer). The optical chip PIC has a through-hole TDV, and this through-hole TDV in the optical chip PIC is electrically connected to the conductive structure CC in the adapter 1210. For example, in the case where the adapter plate 1210 in Figure 25 is similar to the adapter plate 400 shown in Figure 4, the optical waveguide WG1-1 can correspond to the optical waveguide 304-1 in the adapter plate 400 shown in Figure 4, and the conductive structure CC can correspond to the third conductive structure 304-3 in the adapter plate 400 shown in Figure 4.

In the example described in Figures 12A-25, the multiple optical chips shown are separate optical chips obtained after slicing photonic wafers and are attached to different positions on the upper surface of the adapter plate and are spaced apart from each other (as shown in Figures 12A-12B and Figures 20-21). Therefore, after the optical chips are attached to the adapter plate, in order to further encapsulate and enhance the stability and strength of the structure, it is necessary to fill the gaps between different optical chips and different electronic chips on the upper surface of the adapter plate with molding material.

Alternatively, before filling the molding material, a dielectric layer for blocking the outward transmission of light from the adapter board can be first disposed on the interface between the optical chip and the adapter board, and then molding can be performed on this dielectric layer to form a molding material layer. The reason for disposing such a dielectric layer between the adapter board and the optical chip is that the dielectric layer (e.g., silicon oxide layer) covering the waveguide (e.g., optical waveguide WG1-1 as shown in Figure 24 or Figure 25) in the adapter board is very thin. When the optical signal is transmitted in the waveguide between different optical chips, the very thin silicon oxide layer will cause light to leak out during the transmission process, resulting in light loss. Therefore, before molding, a dielectric layer can be fabricated in the gaps between the unattached optical chips on the adapter plate. This dielectric layer preferably uses the same material and fabrication process as the dielectric layer covering the waveguide; for example, it can also be made of silicon oxide, ensuring that the light transmitted in the waveguide between the different optical chips does not leak out. Alternatively, for example, a dielectric layer with a thickness of about a few micrometers can be fabricated.

The packaging structures shown in Figures 24 and 25 both display the molded material layer and the dielectric layer used to block light as described above. For example, the molded material layer MLD and the dielectric layer SHD in Figure 24 or 25. The dielectric layer SHD is located between the interposer and the molded material layer MLD, and has a greater thickness than the thin silicon oxide layer above the optical waveguide WG1-1, ensuring that the light transmitted between different optical chips is confined to the interposer to the greatest extent.

It should be understood that although examples of optical wafer packaging structures using the adapter plates shown in Figures 1 and 4 are shown in Figures 24 and 25 respectively, these are merely exemplary and do not imply that the optical wafer packaging structures disclosed herein can only use the adapter plates shown in Figures 1 and 4. For example, the optical wafer packaging structures disclosed herein can also use an adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2. In the case of using an adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2, the optical waveguides (e.g., optical waveguide WG1-1) in the adapter plate as described above can correspond to the three-dimensional waveguide network 201-2 and the coupling optical waveguides 202-1 covering the optical input and output ports of this three-dimensional waveguide network in the adapter plate 200 as shown in Figure 2. Alternatively, various variations or modifications of the adapters discussed in this disclosure can be used, which will not be listed here.

The above description, in conjunction with Figures 12A-25, illustrates the situation where multiple optical chips bonded to an adapter board are separated optical chips obtained after slicing a photonic wafer. It should be noted that the multiple optical chips bonded to the adapter board can also be multiple unsliced optical chips from the same photonic wafer.

Figures 26 and 27 show schematic diagrams of an optical chip package structure 2600 in which multiple optical chips are mounted on the adapter board and located on the same photonic wafer.

As shown in Figure 26, the optical chip package structure 2600 includes an adapter board 1210 and multiple optical chips (PICs) disposed on the adapter board 1210. For example, since Figure 26 shows a cross-sectional view cut from a specific location, only two optical chips, PIC 1 and PIC 2, are visible in Figure 26. However, in reality, as shown in the top view of Figure 27, the optical chip package structure 2600 may include six optical chips, PIC 1 through PIC 6. It should be understood that the above six optical chips are merely exemplary and not limiting; in actual applications, the optical chip package structure 2600 may include more optical chips.

As shown in Figure 26, the optical chip package structure 2600 includes multiple first optical waveguides embedded therein, such as optical waveguide WG1-1 and optical waveguide WG1-2 shown in Figure 26. Optical waveguide WG1-1 and optical waveguide WG1-2 can be optical waveguides in the aforementioned adapter board, such as optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, or optical waveguide 304-1 in Figure 4. Furthermore, the material of optical waveguide WG1-1 and optical waveguide WG1-2 can be silicon nitride as described above.

Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity, only a single optical waveguide is shown for each PIC in Figure 26), namely optical waveguide WG2-1 and optical waveguide WG2-2. In some examples, the material of optical waveguide WG2-1 and optical waveguide WG2-2 may be silicon. As shown in Figure 27, a photonic wafer PWF comprising multiple optical chips (PIC 1, ..., PIC 6) is bonded to the upper surface of the adapter plate 1210, and the multiple optical chips (PIC 1, ..., PIC 6) are located at different positions on the adapter plate 1210 and are spaced apart from each other.

Optical interconnections can be made between any two of the optical chips PIC 1 and PIC 2 shown in Figure 26, or between any two of the multiple optical chips (PIC 1, ..., PIC 6) shown in Figure 27, via first optical waveguides in multiple adapter boards 1210. For example, as shown by the dashed arrow in Figure 26, light can originate from PIC 1, then be coupled through WG2-1 to optical waveguide WG1-1 in adapter board 1210, then be transmitted through a series of optical waveguide networks (not shown) to optical waveguide WG1-2, and then be coupled again to optical waveguide WG2-1 in PIC 2. Specifically, each first optical waveguide may include a first optical coupling portion, and each second optical waveguide may include a second optical coupling portion (not shown in the figure). For simplicity, the ends of, for example, optical waveguides WG2-1 and WG1-1 can be considered as their respective optical coupling portions. For example, the optical coupling parts of optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and spaced apart by a predetermined distance (e.g., less than 600 nm), so that thermally adiabatic coupling of light can be achieved between the optical coupling parts of optical waveguides WG2-1 and WG1-1.

For the design of the optical coupling section of the first optical waveguide in the interposer and the optical coupling section of the second optical waveguide in the optical wafer, please refer to Figures 13 to 19 and their descriptions. The design of the optical coupling section of the optical waveguide applicable to the case of a separated optical wafer is also applicable to the case of an undivided photonic wafer, unless otherwise stated or clearly unsuitable. For example, the optical coupling section of the first optical waveguide (e.g., WG1-1 or WG1-2) in the interposer and the optical coupling section of the second optical waveguide (e.g., WG2-1 or WG2-2) in the optical wafer can have a tapered shape as shown in Figure 14, or it can be a shape formed by two tapered shapes of different sizes connected in series, as shown in Figure 19.

It should be noted that, in order to distinguish it from the optical wafer package structure 1200 in Figure 12A, the gap between PIC 1 and PIC 2 in the optical wafer package structure 2600 shown in Figure 26 is shown as not filled with a shadow line, thereby indicating that PIC 1 and PIC 2 are located in the same uncut wafer, rather than being filled with casting material between PIC 1 and PIC 2 as shown in Figure 12A.

Similar to the case of using separate optical chips, in the case of using undivided photonic wafers, electrical chips can also be correspondingly arranged on specific optical chips or all optical chips in the photonic wafer.

Figures 28 and 29 show schematic diagrams of an optical wafer package structure 2800 in which electronic chips are simultaneously configured using an undivided photonic wafer.

As shown in Figure 28, in addition to the adapter board 1210 similar to those in Figures 26-27 and the photonic wafer PWF including optical chips PIC 1 and PIC 2, the optical chip package structure 2800 also includes multiple electrical chips disposed on multiple first optical chips (e.g., PIC 1 and PIC 2) among multiple optical chips, such as EIC 1 and EIC 2 disposed on PIC 1 and PIC 2 respectively. Alternatively, as shown in Figure 29A, the optical chip package structure 2800 may include EIC 1, EIC 2, EIC 5, and EIC 6 disposed on PIC 1, PIC 2, PIC 5, and PIC 6 respectively. It should be noted that Figure 28 can be regarded as a cross-sectional view taken from the location of the optical chip package structure 2000 shown in Figure 29A that penetrates EIC 1 and EIC 2. In Figure 29A, PIC 1, PIC 2, PIC 5, and PIC 6 are already covered by their corresponding EICs 1, 2, 5, and 6, and therefore are not shown. Furthermore, as shown in Figure 29A, it is not necessary to set a corresponding EIC for each PIC. For example, EICs may not be configured above PIC 3 and PIC 4 if needed. It should be noted that the absence of EICs above PIC 3 and PIC 4 does not mean that PIC 3 and PIC 4 are not covered by electronic wafers. Rather, it can be understood that the corresponding positions of the electronic wafers covering PIC 3 and PIC 4 are "dummy chips" without a concrete structure, rather than the chips or dies with a concrete structure capable of performing specific functions, as indicated by EIC 1, EIC 2, EIC 5, and EIC 6.

Alternatively, in some examples, an EIC can be configured above each PIC. For example, Figure 29B shows a schematic diagram of an EIC (as shown in EIC 1-EIC 6) configured on each optical chip PIC. In this case, for example, the corresponding electrical chips on all optical chips can be multiple undivided electrical chips in the same electronic wafer, and the multiple optical chips can have the same structure, and the multiple electrical chips (e.g., EIC 1-EIC 6 as shown in the figure) can also have the same structure, such that each PIC-EIC pair stacked vertically forms the same PIC-EIC hybrid wafer. In this case, the multiple first optical chips are equivalent to all optical chips.

It should be noted that, in the case of using undivided photonic wafers, the multiple electronic wafers on the multiple first photonic wafers (e.g., EIC 1, EIC 2, EIC 3, EIC 4, EIC 5, EIC 6 in Figure 29B) are multiple undivided electronic wafers in the same electronic wafer EWF. In this case, the photonic wafer PWF and the electronic wafer EWF, as shown in Figures 29A-29B, are directly bonded together and then jointly disposed on the adapter board 1210. In this case, the flip-chip bonding method shown in Figure 23 is no longer applicable to the connection between the photonic wafer and the electronic wafer.

Additionally, it should be noted that, in order to distinguish it from the optical chip package structure 2000 in Figure 20, the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 in the optical chip package structure 2800 shown in Figure 28 are shown as not filled with shadow lines, thereby indicating that PIC 1 and PIC 2 are located in the same photonic wafer and EIC 1 and EIC 2 are located in the same electronic wafer, instead of the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 being filled with casting material as shown in Figure 20.

Similarly, for the embodiments shown in Figures 28-29, the design of the optical coupling portion of the first optical waveguide in the adapter plate and the optical coupling portion of the second optical waveguide in the optical wafer can also be referred to Figures 13 to 19 and their descriptions. The design of the optical coupling portion of the optical waveguide applicable to the case of a separated optical wafer is also applicable to the case of an undivided photonic wafer, unless otherwise stated or clearly unsuitable. For example, the optical coupling portion of the first optical waveguide (e.g., WG1-1 or WG1-2) in the adapter plate as shown in Figure 28 and the optical coupling portion of the second optical waveguide (e.g., WG2-1 or WG2-2) in the optical wafer can have a tapered shape as shown in Figure 14, or it can be a shape formed by two tapered shapes of different sizes connected in series as shown in Figure 19, which will not be elaborated here.

Additionally, it should be noted that when using an undivided photonic wafer, the optical wafer packaging structure shown in Figures 26-29 can also use the adapter boards 100 and 400 previously described with respect to Figures 1 and 4, or the adapter board 200 with a three-dimensional waveguide network shown in Figure 2. Furthermore, when using the adapter board 200 with a three-dimensional waveguide network as shown in Figure 2, the optical waveguides (e.g., optical waveguide WG1-1) in the adapter board described in Figures 26 or 28 can correspond to the three-dimensional waveguide network 201-2 and the coupling optical waveguides 202-1 covering the optical input and output ports of this three-dimensional waveguide network in the adapter board 200 shown in Figure 2. Alternatively, various variations or modifications of the adapters discussed in this disclosure can be used, which will not be listed here.

The various embodiments of the optical chip packaging disclosed herein have been described above. In summary, the optical chip packaging structures described in Figures 12A-12B and 20-21 employ separate optical chips, with the waveguides of the optical chips and the waveguides of the adapter plate thermally coupled. This packaging structure offers extremely high freedom in chip configuration, significantly reducing the size of the packaging structure. In contrast, the optical chip packaging structures shown in Figures 26-29 employ non-separated optical chips on the same photonic wafer. Although the layout flexibility is not as good as the separate optical chip approach, the direct wafer-to-glass adapter plate bonding process simplifies the process and provides higher alignment accuracy, resulting in higher coupling efficiency between the optical chip and the optical waveguides of the adapter plate. Those skilled in the art to which this invention pertains may choose appropriate embodiments according to actual needs, or combine various embodiments with each other, and such combinations also fall within the protection scope of this disclosure.

By employing various optical chip packaging structures as described above, various computing accelerators can be implemented, such as those used for matrix multiplication in neural networks. Figure 30 shows a schematic diagram of the computing accelerator 3000 of the embodiment disclosed herein. Figure 31A shows a schematic diagram of another computing accelerator 3100A of the embodiment disclosed herein. Figure 31B shows a schematic diagram of yet another computing accelerator 3100B of the embodiment disclosed herein.

The computing accelerator 3000 shown in Figure 30 can be implemented using a discrete optical wafer package structure as shown in Figures 12A-12B or Figures 20-21. For example, as shown in Figure 30, the computing accelerator 3000 may include one or more light sources LS, one or more computing units CL, and one or more memory units MO. For clarity, different fill patterns are used to distinguish different functional units; for example, solid white filled units (squares as shown in the figure) represent memory units MO, grid filled units represent computing units CL, and scatter filled units represent light sources LS.

Some units in the computing accelerator 3000 can be implemented in an optical wafer package as shown in Figures 12A-12B and/or Figures 20-21. For example, one or more computing units CL are configured to perform computational functions, which can be implemented by an optical wafer in the optical wafer package structure 1200 described above in Figures 12A-12B. For example, matrix multiplication can be implemented using a Mach-Zehnder interferometer or similar device within the optical wafer. Alternatively, one or more computing units CL can be implemented by electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21. For example, the optical chip in the optical chip package structure 1200 mainly performs communication functions, and the electronic chip performs calculation functions. Or, one or more computing units CL can be jointly implemented by the optical chip and electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21. For example, the optical chip in the optical chip package structure 1200 simultaneously performs communication functions and some calculation functions, and the electronic chip performs other calculation functions. One or more memory units MO are configured to perform memory functions and can be implemented by electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21.

Furthermore, preferably, in the case of implementing the computing accelerator 3000 using the optical wafer package as shown above with respect to Figures 12A-12B and/or Figures 20-21, one or more light sources LS can be integrated into the aforementioned wafer package structure. For example, one or more light sources LS can be attached to the first surface of the adapter plate 1210 in a manner similar to PIC 1 or PIC 2 in the optical wafer package structure 1200 or 2000 as described above, and are configured to provide light waves to the computing accelerator 3000 through the waveguide WG in the adapter plate, more specifically, to provide light waves to each optical wafer in the computing accelerator 3000.

For example, a method similar to thermal coupling between an optical chip and a converter plate can be used to thermally couple light from the light source LS to the corresponding optical waveguide in the converter plate, thus avoiding the additional interface required for coupling light through other intermediate links (e.g., optical fibers). This light source configuration method also helps to further compress the size of the computing accelerator.

Alternatively, the computing accelerator 3000 may also include one or more edge optical couplers, i.e., edge optical couplers CP located around the perimeter of a square as shown in Figure 30, which are configured to optically interconnect the computing accelerator with other devices. For example, if the light source LS is not mounted on the adapter plate as described above, but is used as an external light source, the edge optical couplers CP in the computing accelerator 3000 can be used to connect the light source.

Figure 30 shows that the adapter board 1210 in the computing accelerator can be one of the various types of adapter boards described above. For example, it can be adapter boards 100 and 200 as described in Figures 1 and 2, or adapter board 400 as described in Figure 4. In addition, various variations or modifications of the adapter boards discussed in this disclosure can also be used, which will not be listed here.

Furthermore, it should be noted that although the computing accelerator is shown in Figure 30 as being implemented in different chips within the same optical chip package structure, this is merely illustrative. In practical applications, multiple different optical chip packages can be interconnected via edge optical couplers (CP) as described above, and various computing units, memory units, or light sources can be implemented or configured within multiple optical chip packages to form large or ultra-large computing accelerators.

Compared to the computing accelerator 3000 shown in Figure 30, the computing accelerator 3100A shown in Figure 31A can be implemented using a photonic wafer-level package structure as shown in Figures 26-29B. For example, as shown in Figure 31A, the computing accelerator 3100A may include one or more light sources LS, one or more computing units CL, and one or more memory units MO. For clarity, different fill patterns are used to distinguish different functional units; for example, solid white filled units (such as the squares shown in the figure) represent memory units MO, and grid-filled units represent computing units CL.

Some units in the computation accelerator 3100A can be implemented in the optical wafer package structure shown above with respect to Figures 26-29B. For example, one or more computation units CL are configured to perform computational functions, which can be implemented by an optical wafer in the optical wafer package structure 2600 described above with respect to Figures 26-27. For example, matrix multiplication operations can be implemented using a Mach-Zehnder MZI interferometer or the like in the optical wafer. Alternatively, one or more computing units or memory units can be implemented by optical chips or electronic chips in the optical chip package structure 2800 as described above with respect to Figures 28-29A. For example, the optical chip in the optical chip package structure 2800 mainly performs communication functions, and the electronic chip performs calculation and memory functions. Alternatively, one or more computing units CL can be jointly implemented by optical chips and electronic chips in the optical chip package structure 2800 as described above with respect to Figures 28-29A. For example, the optical chip in the optical chip package structure 2800 simultaneously performs communication functions and some calculation and memory functions, and the electronic chip performs other calculation and memory functions.

Unlike Figure 30, Figure 31A uses a photonic wafer packaging structure. In addition to the square area shown in Figure 30, there are redundant photonic chips. Before bonding the photonic wafer to the adapter board, the redundant photonic chips need to be cut off.

Alternatively, the aforementioned computing unit and memory unit can also be implemented using a packaging structure as shown in Figure 29B. For example, when the computing unit and memory unit in the computing accelerator are implemented using the optical chip package structure 2900 shown in Figure 29B, since each EIC in the optical chip package structure 2900 is identical, and each PIC is also identical, each PIC and its corresponding EIC (e.g., PIC 1 and EIC 1) can be used together to implement each computing unit and its corresponding memory unit, and it can be regarded as a computing-memory unit.

Figure 31B shows an example of a computing accelerator 3100B in which each computing unit and its corresponding memory unit are implemented as a corresponding compute-memory unit. For example, each computing unit and its corresponding memory unit can be implemented by each optical chip and its corresponding electrical chip in the optical chip package structure 2900 as shown in Figure 29B, and each computing unit and its corresponding memory unit can be regarded as a compute-memory unit CL-MO.

In this case, as shown in Figure 31B, the combination of the computing unit and the corresponding memory unit can be regarded as a single compute-memory unit (CL-MO). For ease of understanding, each compute-memory unit (CL-MO) in Figure 31B is displayed as being filled with a checkerboard pattern, indicating that each compute-memory unit (CL-MO) can have the same hardware resources, that is, the same memory resources, computing resources, communication resources, etc. For example, in the case where the multiple computation-memory units (CL-MOs) shown in the figure are implemented by the optical chip package structure 2900 described above with reference to Figure 29B, the optical chip in the optical chip package structure 2900 can mainly perform communication functions, and the corresponding electronic chip can perform computation and memory functions; or, the optical chip can simultaneously perform communication functions and some computation and memory functions, and the corresponding electronic chip can perform other computation and memory functions.

Furthermore, it should be understood that the terms "computing unit," "memory unit," and "computation-memory unit" as described above are intended to describe functional units within a computing accelerator, and not to limit the individual optical chips, electronic chips, or combinations of optical and electronic chips in an optical chip package to computation, memory, or computation-memory only. For example, the individual optical chips, electronic chips, or combinations of optical and electronic chips in an optical chip package can also be used to perform functions other than computation, memory, or computation-memory, such as data transmission.

Furthermore, it should be noted that, since the computing accelerator 3100A or 3100B is a direct bonding of electronic wafer to photonic wafer, the light source LS (e.g., laser chip) cannot be directly bonded to the adapter board. It needs to couple light into the computing accelerator through an optical fiber array or other light guide structure. The light source LS is configured to provide light waves to the computing accelerator 3100A or 3100B through the waveguide WG in the adapter board, or more precisely, to provide light waves to each optical chip in the computing accelerator 3100A or 3100B.

Additionally, the computing accelerator 3100A or 3100B may also include one or more edge optical couplers, i.e., edge optical couplers CP located around the perimeter of a square, as shown in Figure 31A or 31B, which are configured to optically interconnect the computing accelerator with other devices. For example, the edge optical couplers CP in the computing accelerator 3100A or 3100B can be used to connect a light source LS.

The adapter board 1210 shown in Figure 31A or Figure 31B in the computing accelerator can be of various types of adapter boards as described above. For example, it can be adapter boards 100 and 200 as described in Figures 1-2, or adapter board 400 as described in Figure 4. In addition, various variations or modifications of the adapter boards discussed in this disclosure can also be used, which will not be listed here.

Furthermore, it should be noted that although the computing accelerator is shown in Figures 31A or 31B as being implemented in different chips within the same optical chip package structure, this is merely illustrative. In practical applications, multiple different optical chip packages can be interconnected via edge optical couplers (CP) as described above, and various computing units, memory units, or light sources can be implemented or configured within multiple optical chip packages to form large or ultra-large computing accelerators.

Alternatively, the computing accelerator described above with respect to Figures 30-31 may also include multiple high-bandwidth memory (HBM) chips stacked on the optical chip in the optical chip package structure described above, which are configured to perform memory computing functions.

The foregoing describes various embodiments of optical chip packaging structures and computational accelerators implemented using these structures. In summary, the optical chip packaging structures described in Figures 12A-12B and Figures 20-21, due to their use of discrete optical chips and the thermally coupled coupling of the waveguides of the optical chips and the adapter board, offer extremely high freedom in chip configuration, significantly reducing the size of the packaging structure. Furthermore, computational accelerators implemented using this packaging structure can further integrate the light source within the optical chip packaging structure, facilitating further reduction in product size.

In contrast, the optical chip packaging structure shown in Figures 26-29B uses unseparated optical chips on the same photonic wafer. Although it is less flexible in layout than the separated optical chip scheme, the direct wafer-to-glass interposer bonding process is simpler and has higher alignment accuracy, resulting in higher coupling efficiency between the optical chip and the optical waveguide of the interposer. Those skilled in the art can choose appropriate embodiments according to actual needs, or combine various embodiments, and such combinations also fall within the protection scope of this disclosure.

The specific manufacturing methods of the various optical chip package structures described above will be described below with reference to Figures 32-36. Figures 32-36 show flowcharts of the manufacturing methods of the optical chip package structures of the embodiments disclosed herein.

It should be noted that the structures and features mentioned in the manufacturing methods described below, such as those of adapter boards, optical chips, and electronic chips, are similar to the various structures or features described in the embodiments of various optical chip packaging structures above. For the sake of simplicity, repeated descriptions of these structures or features may be omitted in some cases. In such cases, the various structures or features involved in the manufacturing methods described below should not be interpreted narrowly as such.

Furthermore, in the following description of the manufacturing method of the optical chip package structure, in order to avoid repetition, some process steps shown in other diagrams will be referenced in certain processes. In this case, the various steps involved in the manufacturing method described above should not be interpreted narrowly.

Figure 32 shows a flowchart of a method 3200 corresponding to the optical chip package structure 1200 shown in Figures 12A-12B.

As shown in Figure 32, method 3200 includes: providing an adapter board (step S3210) and attaching a plurality of optical chips to different positions on the upper surface of the adapter board (step S3220). For example, the adapter board may be adapter board 1210 as shown in Figure 12A, and the plurality of optical chips may be PIC 1 to PIC 6 as shown in Figure 12B.

For example, an adapter board may include one or more first optical waveguides (such as optical waveguides WG1-1 and WG1-2 shown in Figure 12A), and each first optical waveguide includes a first optical coupling portion. Each optical chip may include one or more second optical waveguides (such as optical waveguides WG2-1 and WG2-2 shown in Figure 12A), and each of the aforementioned second optical waveguides includes a second optical coupling portion.

For example, the first optical coupling part and the second optical coupling part are respectively tapered shapes as shown in Figure 14 above. Alternatively, the first optical coupling part and the second optical coupling part may also have shapes formed by connecting two tapered shapes of different sizes in series, as shown in Figure 19 above.

As mentioned above with respect to Figure 13, the first optical coupling part and the second optical coupling part are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance (e.g., less than or equal to 600 nm), so that the first optical coupling part and the second optical coupling part achieve thermally adiabatic coupling of light, and multiple optical chips are optically interconnected through multiple first optical waveguides.

Figures 33-35 show flowcharts of the manufacturing method corresponding to the optical chip package structure 2000 shown in Figures 20-21.

As shown in Figure 33, method 3300 includes: providing an adapter board (step S3310), configuring an electronic chip on a first optical chip among a plurality of optical chips, such that the first optical chip and the electronic chip thereon form an electron-photon hybrid chip (step S3320), and attaching the plurality of optical chips to different positions on the upper surface of the adapter board (step S3330).

Compared to the manufacturing method shown in Figure 32, the method 3300 shown in Figure 33 adds a step S3320 for forming an electron-photon hybrid chip. It should be noted that the term "electron-photon hybrid chip" here does not mean using chips other than the aforementioned optical and electrical chips, but rather can correspond to the overall structure formed by interconnecting PIC 1 and EIC 1 as shown in Figure 20, or the overall structure formed by interconnecting PIC 1 and EIC 1. More precisely, the term "electron-photon hybrid chip" can correspond to the various chip structures shown in Figures 22 and 23.

For example, as shown in Figure 22(a), the PIC together with the EIC disposed thereon can be referred to as an electronic-photonic hybrid chiplet. As shown in Figure 22(a), the upper surface of the PIC has multiple first electrical connections C1, and the lower surface of the EIC has multiple second electrical connections C2. The PIC and the EIC are directly connected through the first electrical connections C1 and the second electrical connections C2.

In addition, the electronic-photonic hybrid chip can also be an integral structure as shown in Figure 22(b), which includes a PIC and two EICs (D-EIC and A-EIC), and the D-EIC, A-EIC and PIC are directly connected to each other through the first electrical connector C1 and the second electrical connector C2.

Similarly, the overall structure of the EIC and PIC connected by flip-chip as shown in Figure 23 can also be regarded as an electron-photon hybrid chip as described above, and will not be repeated here.

Figures 34 and 35 show two different methods for configuring electrical wafers on a first optical wafer among the aforementioned plurality of optical wafers to form an electron-photon hybrid wafer. The process steps in Figures 34 and 35 can be regarded as subdivisions of step S3320 in Figure 33.

As shown in Figure 34, configuring an electronic wafer on the first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer (step S3410), directly bonding the electronic wafer to the photonic wafer (step S3420), removing the substrate of the photonic wafer (step S3430), and dicing the electronic-photonic hybrid wafer into a plurality of electronic-photonic hybrid wafers (step S3440).

In some examples, the photonic wafer fabricated in step S3410 may be similar to the photonic wafer PWF described with respect to Figure 29A, which includes multiple optical wafers PIC 1-PIC 6, and the multiple optical wafers PIC 1-PIC 6 include multiple first optical wafers for configuring corresponding electrical wafers thereon. Similarly, the electronic wafer fabricated in step S3410 may be similar to the electronic wafer EWF described with respect to Figure 29A, which includes multiple electrical wafers (e.g., EIC 1, EIC 2, EIC 5, EIC 6).

In some examples, for instance, an electron-photonic hybrid wafer can be obtained by bonding the plurality of first optical wafers with the plurality of electrical wafers (e.g., by direct bonding), and then the electron-photonic hybrid wafer is diced into a plurality of electron-photonic hybrid wafers in step S3440.

It should be noted that although the specific structures of photonic and electronic wafers are illustrated above in conjunction with Figure 29A, this is merely for ease of description. In reality, Figure 29A shows that the PWF and EWF do not need to be divided into separate electronic-photonic hybrid wafers; they are directly bonded and configured as a whole on the adapter board. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into independent electronic-photonic hybrid wafers, redundant wafers at the edges need to be removed for packaging purposes, for example, by cutting them into internal square shapes as shown in Figures 31A or 31B.

Figure 35 illustrates another method for forming an electronic-photonic hybrid wafer. As shown in Figure 35, configuring an electronic chip on a first optical chip among a plurality of optical chips may specifically include: fabricating a photonic wafer and an electronic wafer (step S3510), dicing the electronic wafer into the plurality of electronic chips (step S3520), directly bonding or flip-chip bonding one or more of the plurality of electronic chips to the first optical chip in the photonic wafer to obtain an electronic-photonic hybrid wafer (step S3530), filling the gaps on the photonic wafer not occupied by the electronic chips with a molding material (step S3540), removing the substrate of the photonic wafer (step S3550), and dicing the electronic-photonic hybrid wafer into the electronic-photonic hybrid wafer (step S3560).

Similarly, the photonic wafer fabricated in step S3510 can be similar to the photonic wafer PWF described with respect to Figure 29A, which includes multiple optical wafers PIC 1-PIC 6, and the multiple optical wafers PIC 1-PIC 6 include multiple first optical wafers for mounting corresponding electrical wafers thereon. Similarly, the electronic wafer fabricated in step S3510 can be similar to the electronic wafer EWF described with respect to Figure 29A, which includes multiple electrical wafers (e.g., EIC 1, EIC 2, EIC 5, EIC 6).

Unlike method 3400, in method 3500, the electronic wafer comprising multiple electronic chips is not integrally bonded to the photonic wafer. Instead, it is first diced into multiple separate electronic chips in step S3520, and then in step S3530, the diced electronic chips are directly bonded or flip-chip bonded to the first photonic chip in the photonic wafer to obtain an electronic-photonic hybrid wafer.

Since the individual electronic chips are separate electronic chips, rather than located on the same electronic wafer as described in method 3400, it is necessary to fill the gaps on the photonic wafer that are not occupied by the electronic chips with casting material after the corresponding electronic chips are disposed on the first photonic wafer, thereby enhancing the mechanical strength and stability of the photonic wafer.

It should also be noted that although the specific structures of photonic and electronic wafers are illustrated above in conjunction with Figure 29A, this is merely for ease of description. In reality, Figure 29A shows that the PWF and EWF do not need to be divided into separate electronic-photonic hybrid wafers; they are directly bonded together and configured as a whole on the adapter board. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into independent electronic-photonic hybrid wafers, it is necessary to remove excess wafers at the edges for packaging purposes, for example, by cutting them into internal square shapes as shown in Figures 31A or 31B.

Furthermore, the above method 3400 or 3500 may also include: after removing the substrate of the photonic wafer and before dicing the electron-photonic hybrid wafer into the electron-photonic hybrid wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness (not shown in the figure). When an optical waveguide has already been fabricated in the photonic wafer, the thinning operation described above is to reduce the thickness of the buried oxide layer on the bottom surface of the optical waveguide in the optical wafer, thereby allowing the optical waveguide in the optical wafer to be as close as possible to the optical waveguide in the adapter plate, thus increasing the coupling efficiency.

The thinning operation described above can be used to make the spacing between the optical waveguide in the optical chip and the optical waveguide in the adapter plate less than or equal to 600 nm, as shown in Figure 13.

Additionally, the above method 3400 or 3500 may further include: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, and forming a connection waveguide on the surface of the photonic wafer away from the electronic chip; and covering the connection waveguide with a dielectric material, wherein the connection waveguide and the second optical coupling portion of the second optical waveguide in the optical chip and the first optical coupling portion of the first optical waveguide in the adapter plate are stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer (not shown in the figure), and the first optical waveguide, the connection waveguide, and the second connection waveguide perform optical communication through thermally adiabatic coupling of light. A connection waveguide is formed in the photonic wafer in the above manner, and then a dielectric material is covered on the connection waveguide to cover it. The purpose is the same: to add a connecting waveguide between the optical waveguide in the optical chip and the optical waveguide in the adapter board, thereby increasing the coupling efficiency.

In some examples, the above method 3400 or 3500 may further include: after fabricating the photonic wafer, forming one or more second conductive vias in the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, so that the one or more second conductive vias are vertically connected to form one or more second conductive vias (not shown in the figures). For example, the second conductive vias formed by the above method may be a TDV on the PIC as shown in Figure 22 or Figure 23, which is used to electrically connect the EIC chip to the adapter board.

For example, in some examples, attaching multiple optical wafers to different locations on the upper surface of the adapter plate further includes electrically connecting one or more second conductive vias to one or more conductive structures in the adapter plate. The one or more conductive structures in the adapter plate can be the first conductive structure 102-3 in the adapter plate 100 as shown in Figure 1, the first conductive structure 202-3 in the adapter plate 200 as shown in Figure 2, or the third conductive structure 304-3 in the adapter plate 400 as shown in Figure 4. Specific details regarding the electrical connection of one or more second conductive vias in the optical wafers to one or more conductive structures in the adapter plate can be found in Figures 24 or 25, showing the connection between TDV and conductive structure CC, and will not be elaborated further here.

Returning to method 3300, after attaching multiple optical chips to different positions on the upper surface of the adapter plate, multiple electron-photon hybrid chips are spaced apart from each other on the upper surface of the adapter plate. Since there are still gaps between the different electron-photon hybrid chips at this time, it is necessary to fill these gaps with molding material to enhance the stability and mechanical strength of the package.

However, because the dielectric layer (e.g., silicon oxide layer) covering the waveguides (e.g., WG1-1 as shown in Figure 24 or 25) in the adapter board is very thin, the thin silicon oxide layer can cause light to leak out during transmission, resulting in light loss. Therefore, a dielectric layer can be fabricated in the gaps between the non-attached optical chips on the adapter board before molding to block the outward transmission of light from the adapter board. Preferably, the material of this dielectric layer is the same as that of the dielectric layer covering the waveguides in the adapter board, and the same process is used.

Therefore, method 3300 may further include: before filling the gaps between the optical wafers with a molding material, forming a dielectric layer (not shown in the figure) on the upper surface of the adapter plate and in the gaps between the plurality of electron-photon hybrid wafers to block the outward transmission of light in the adapter plate. The dielectric layer may also be made of silicon oxide and may have a predetermined thickness, such as several micrometers, to ensure that light transmitted in the waveguides between the different optical wafers does not leak out.

The above figures, in conjunction with Figures 33-35, illustrate a method for manufacturing the optical chip package structure corresponding to Figures 12A-12B and Figures 20-21, wherein the packaged multiple optical chips and multiple electronic chips are separate from each other, i.e., not on the same wafer. The following figures will describe a method for manufacturing the optical chip package structure corresponding to Figures 26-29, in which multiple optical chips or multiple electronic chips are located on the same photonic wafer or the same electronic wafer.

The method shown in Figure 36 corresponds to the manufacturing method of the optical chip package structure 2600 shown in Figures 26-27.

As shown in Figure 36, method 3600 includes: providing an adapter board (step S3610), fabricating a photonic wafer (step S3620), and directly bonding the photonic wafer to the upper surface of the adapter board (step S3630). The adapter board may be similar to any of the adapter boards described above, and will not be described in detail here. The fabricated photonic wafer includes multiple optical chips, and the photonic wafer is connected to the adapter board by a direct bonding method.

The method shown in Figure 37 corresponds to the manufacturing method of the optical chip package structure 2800 shown in Figures 28-29.

As shown in Figure 37, method 3700 includes: providing an adapter board (step S3710), fabricating a photonic wafer and an electronic wafer (step S3720), directly bonding the electronic wafer to the photonic wafer such that a plurality of first optical chips are bonded to a plurality of electronic chips to obtain an electronic-photonic hybrid wafer (step S3730), and directly bonding the photonic wafer to the upper surface of the adapter board (step S3740). Similarly, the adapter board can be similar to any of the adapter boards described above. The fabricated photonic wafer includes a plurality of optical chips, and the fabricated electronic wafer may include a plurality of electronic chips. The electronic wafer is directly bonded to the photonic wafer such that a specific optical chip in the photonic wafer (i.e., the first optical chip as described above) is bonded to a plurality of electronic chips to obtain an electronic-photonic hybrid wafer. Furthermore, the photonic wafer is connected to the adapter board by a direct bonding method.

The steps described above regarding Figures 32-35—removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, configuring and covering the interconnecting waveguide in the photonic wafer, and forming one or more second vias in the photonic wafer—are equally applicable to the methods described regarding Figures 36-37, unless otherwise stated or clearly inapplicable.

The above describes various methods for manufacturing optical chip packaging structures in the embodiments disclosed herein. It should be noted that the steps in the manufacturing methods described above in conjunction with the flowcharts are merely exemplary, and the order of the steps shown in the flowcharts is not necessarily fixed. Those skilled in the art to which this invention pertains can adjust the order of the steps, and may also omit or add additional steps based on their knowledge of the design concept of this application. Methods obtained through such adjustments, omissions, or additions of steps also fall within the protection scope of this application.

In the foregoing description, embodiments of this disclosure have been described in conjunction with the drawings. It should be understood that the above embodiments are merely illustrative, and those skilled in the art to which this invention pertains should understand that the constituent elements and processing combinations of this embodiment can be modified in various ways, and such modifications also fall within the scope of this disclosure.

100: Adapter plate; 101: Glass substrate; 101-1: Conductive via; 102: Optical waveguide structure; 102-1: Optical waveguide; 102-2: Coating layer; 102-3: First conductive structure; 103: Dielectric layer; 103-2: Conductive via structure; 103-3: Redistribution layer; 103-4: Notch; 104: Conductive bump; 200: Adapter plate; 201: Glass substrate; 201-1: Conductive via; 201-2: Three-dimensional waveguide network; 202: Optical coupling structure; 202-1: Coupled optical waveguide; 202-2: Coating layer. 202-3: First conductive structure; 203: Dielectric layer; 203-2: Conductive via structure; 203-3: Redistribution layer; 203-4: Notch; 204: Conductive bump; 300: Adapter plate; 301: Glass substrate; 301-1: Conductive via; 302: Electrical interconnection structure; 302-1a, 302-1b, 302-1c: Layout layer; 302-2: Coating layer; 302-2a: Silicon nitride layer; 302-2b: Silicon dioxide layer; 302-3: First conductive structure; 302-4: Second conductive structure. 303: Dielectric layer; 303-2: Conductive via structure; 303-3: Redistribution layer; 303-4: Notch; 304: Optical waveguide structure; 304-1: Optical waveguide; 304-2: Enclosure layer; 304-3: Third conductive structure; 305: Conductive bump; 400: Adapter board; 500: Optical chip; 501: Interconnect structure; 800: Package structure; 1000: Package structure; 1200: Optical chip package structure; 1210: Adapter board; 2000: Optical chip package structure; 2600: Optical chip package structure; 2800: Optical... Chip package structure 2900: Optical chip package structure 3000: Package structure 3100A: Package structure 3100B: Package structure 3200: Method 3300: Method 3400: Method 3500: Method 3600: Method 3700: Method A-EIC: Analog IC C1: First electrical connector C2: Second electrical connector CC: Conductive structure CL: Calculation unit CL-MO: Calculation-memory unit CP: Edge optocoupler D-EIC: Digital IC EIC, EIC 1, EIC 2, EIC 3, EIC 4, EIC 5, EIC 6: Electronic Chip; EWF: Electronic Wafer; H: Predetermined Distance; IF1: Interface; IF2: Interface; L: Length; LM: Lateral Misalignment; LS: Source; L_taper: Length; L_trans: Coupling Length; MLD: Molding Material Layer; MO: Memory Cell; _{neff_si} , _{neff_SiN} : Dielectric Coefficient; PIC, PIC 1, PIC 2, PIC 3, PIC 4, PIC 5, PIC 6: Photonic wafer PWF: Photonic wafer R1: Regions S1-1, S1-2, S2-1, S2-2: Dimensions S3210, S3220: Steps S3310, S3320, S3330: Steps S3410, S3420, S3430, S3440: Steps S3510, S3520, S3530, S3540, S 3550, S3560: Step S3610, S3620, S3630: Step S3710, S3720, S3730, S3740: Step SHD: Dielectric layer tSiN: Thickness TDV: Conductive via TM: Longitudinal misalignment W4: Width WG: Waveguide WG1-1, WG1-2, WG2-1, WG2-2: Optical waveguide

Figure 1 shows a cross-sectional view of a first example of an adapter board for optical chip packaging according to an embodiment of the present disclosure. Figure 2 shows a cross-sectional view of a second example of an adapter board for optical chip packaging according to an embodiment of the present disclosure. Figure 3 shows a cross-sectional view of a third example of an adapter board for optical chip packaging according to an embodiment of the present disclosure. Figure 4 shows a cross-sectional view of a fourth example of an adapter board for optical chip packaging according to an embodiment of the present disclosure. Figure 5 shows a process flow diagram of the manufacturing method of the adapter board in the first example of the present disclosure. Figure 6 shows a process flow diagram of the manufacturing method of the adapter board in the second example of the present disclosure. Figure 7A shows a process flow diagram of the manufacturing method of the adapter board in the third example of the present disclosure. Figure 7B shows a process flow diagram of the manufacturing method of the adapter board in the fourth example of the present disclosure. Figure 8 shows a cross-sectional view of the optical chip package structure of the adapter board in the first embodiment of the present disclosure. Figure 9 shows a cross-sectional view of the optical chip package structure of the adapter board in the second embodiment of the present disclosure. Figure 10 shows a cross-sectional view of the optical chip package structure of the adapter board in the third embodiment of the present disclosure. Figure 11 shows a cross-sectional view of the optical chip package structure of the adapter board in the fourth embodiment of the present disclosure. Figures 12A and 12B show a cross-sectional view and a top view of the optical chip package structure of the present disclosure, respectively. Figures 13 and 14 show a schematic side view and a top view of the optical coupling portion in the optical chip package structure of the present disclosure, respectively, and a corresponding optical mode field diagram. Figure 15 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the present disclosure at different lengths. Figure 16 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the present disclosure at different pitches. Figure 17 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the present disclosure at different thicknesses. Figures 18 and 19 show another schematic side view and top view of the optical coupling portion in the optical chip package structure of the present disclosure, respectively, and corresponding optical mode field diagrams. Figures 20 and 21 show a cross-sectional view and a top view of the optical chip package structure of the present disclosure, respectively. Figure 22 shows a cross-sectional view of the optical chip and electronic chip in the optical chip package structure of the present disclosure. Figure 23 shows a cross-sectional view of the optical chip and electronic chip in the optical chip package structure of the present disclosure. Figure 24 shows a cross-sectional view of the optical chip package structure of the present disclosure. Figure 25 shows a cross-sectional view of the optical chip package structure of the embodiment disclosed herein. Figures 26 and 27 show a cross-sectional view and a top view of the optical chip package structure of the embodiment disclosed herein, respectively. Figures 28 and 29A-29B show a cross-sectional view and a top view of the optical chip package structure of the embodiment disclosed herein, respectively. Figure 30 shows a schematic diagram of a computing accelerator of the embodiment disclosed herein. Figure 31A shows a schematic diagram of another computing accelerator of the embodiment disclosed herein. Figure 31B shows a schematic diagram of yet another computing accelerator of the embodiment disclosed herein. Figures 32-37 show flowcharts of the manufacturing method of the optical chip package structure of the embodiment disclosed herein.

100: Adapter board

101: Glass substrate

101-1: Conductive vias

102: Optical waveguide structure

102-1: Optical waveguide

102-2: Overlying layer

102-3: First Conducting Structure

103: Dielectric layer

103-2: Conductive hole structure

103-3: Layering

104: Conductive bumps

Claims (14)

An adapter board for optical chip packaging includes: a glass substrate including one or more conductive vias, the conductive vias including through-holes penetrating the glass substrate and conductive material filling the through-holes; and an optical coupling structure disposed on a first surface of the glass substrate, wherein the glass substrate further includes a three-dimensional waveguide network for optically interconnecting multiple optical chips packaged on the adapter board, the optical coupling structure including a coupling optical waveguide covering the optical input and output ports of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide, and the optical coupling structure further includes one or more first conductive structures penetrating the optical coupling structure, which are electrically connected to the one or more conductive vias respectively. The adapter board as described in claim 1, wherein the refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer. The adapter board described in claim 2, wherein the coupling optical waveguide is a silicon nitride optical waveguide and the cladding layer is made of silicon dioxide. The adapter plate as described in claim 1 further comprises: a dielectric layer disposed on a second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively. The adapter board as described in claim 1, wherein: the three-dimensional waveguide network is a network structure formed by inducing local glass inside the glass substrate to increase the refractive index of the local glass. A method for manufacturing an adapter board for optical chip packaging includes: providing a glass substrate and forming a three-dimensional waveguide network within the glass substrate for optical interconnection of multiple optical chips packaged on the adapter board; forming one or more conductive vias in the glass substrate; disposing a coupling optical waveguide on a first surface of the glass substrate to cover the optical input and output ports of the three-dimensional waveguide network; covering the coupling optical waveguide with a cladding layer; and forming one or more first conductive structures penetrating the cladding layer in the cladding layer and electrically connecting them to the one or more conductive vias respectively. The method for manufacturing the adapter plate as described in claim 6, wherein the refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer. The method for manufacturing the adapter board as described in claim 7, wherein the aforementioned coupling optical waveguide is a silicon nitride optical waveguide, and the material of the aforementioned cladding layer is silicon dioxide. The method of manufacturing the adapter plate as described in claim 6 further includes: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to the one or more conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively. The method for manufacturing an adapter plate as described in claim 6, wherein forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and disposing a conductive material layer on the inner surface of the one or more vias to form the one or more conductive vias. The method of manufacturing the adapter plate as described in claim 10, wherein the conductive material layer is disposed on the inner surface of the one or more vias to form the one or more conductive vias, comprises: filling the inner surface of the one or more vias with conductive metal by electroplating. The method for manufacturing the adapter plate as described in claim 6, wherein forming the three-dimensional waveguide network in the glass substrate includes: irradiating a predetermined position of the glass substrate with a femtosecond laser to increase the refractive index of the predetermined position of the glass substrate, wherein the predetermined position is the location where the three-dimensional waveguide network structure is formed. An optical chip packaging structure includes an adapter board as described in any one of claims 1-5, and the plurality of optical chips disposed on the adapter board, wherein the adapter board is used to perform optical interconnection and/or electrical interconnection of the plurality of optical chips disposed on the adapter board. The optical chip packaging structure as described in claim 13 further includes: one or more electrical chips disposed on the plurality of optical chips; the optical chips include one or more interconnection structures, the interconnection structures including vias penetrating the optical chips and conductive materials filling the vias; the one or more interconnection structures are electrically connected to the one or more first conductive structures and/or the one or more electrical interconnection structures on the adapter board, respectively.