TW202526570A - Integrated circuit having microvault memories - Google Patents

Abstract

An integrated circuit is disclosed herein that may comprise a plurality of microvaults, with each of the microvaults disposed in a spaced relation relative to one another and adjacent to a first surface. The plurality of microvaults includes a first microvault. Additionally, the integrated circuit may comprise a plurality of bonding areas, with each bonding area disposed on the first surface and adjacent to a respective one of the plurality of microvaults. The plurality of bonding areas includes a first bonding area in operative communication with the first microvault.

Description

Integrated circuit with micro-bank memory

The present invention relates to an integrated circuit. More particularly, the present invention relates to an integrated circuit having a plurality of modules including a micro-bank memory.

Chiplets are small chips designed to function as a single entity while utilizing advanced packaging technologies. These miniaturized chips are created by breaking a larger chip into several smaller chips, each with its own unique function or capability. The concept stems from the semiconductor industry's need to overcome the physical limitations of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.

Chiplets can be based on different architectures (such as CPU, GPU, memory, or I/O) and can be assembled and stacked in various ways depending on specific application requirements. One advantage of the chiplet approach is the ability to mix and match different chiplets from different manufacturers to create customized solutions that meet specific computing needs. This approach also allows for faster time to market, lower development costs, and increased flexibility, as chiplets can be upgraded or replaced without requiring a complete system redesign.

Chiplets are used in a variety of industries, including consumer electronics, cloud computing, and data centers, where high-performance computing and energy efficiency are crucial. Chiplets are expected to play a significant role in future computing and unlock new possibilities for creating more powerful and/or advanced electronic devices.

Disclosed herein is an integrated circuit that can be part of a semiconductor device. Disclosed herein is a method of manufacturing or a method of writing and reading data to a module and can be used with all examples, embodiments, and aspects disclosed herein.

The integrated circuit may include a plurality of micro-storage banks, wherein each of the micro-storage banks is disposed in a spaced relationship relative to one another and adjacent to a first surface. The plurality of micro-storage banks includes a first micro-storage bank. Furthermore, the integrated circuit may include a plurality of bonding regions, wherein each bonding region is disposed on the first surface and adjacent to a respective one of the plurality of micro-storage banks. The plurality of bonding regions includes a first bonding region in operative communication with the first micro-storage bank.

In some embodiments, the integrated circuit may include a first bonding region disposed on the first surface and adjacent to the first micro-bank. The first bonding region may optionally include a plurality of bondings, wherein each bonding is in operative communication with the first micro-bank.

In some embodiments, the first bonding region may include a plurality of bondings each in operative communication with the first micro-bank. Optionally, the plurality of bondings may be bumpless bondings.

In some embodiments, the integrated circuit may have a first micro-storage bank having a capacity between 4 kilobytes and 1 million bytes.

In some embodiments, the first micro-storage has a capacity between 4 kilobytes and 128 kilobytes.

In some embodiments, the micro-repositories may have a storage capacity ranging from 4 kilobytes to 16 kilobytes.

In some embodiments, the first micro-repository may have dimensions less than 256 microns by less than 256 microns and extend a predetermined distance in a vertical dimension.

In some embodiments, the first micro-repository has dimensions of 32 microns x 32 microns and extends vertically a predetermined distance.

In some embodiments, the integrated circuit may involve the first micro-bank having a vertical dimension corresponding to at least eight memory layers. Specifically, in one embodiment, the first micro-bank has dimensions of 32 microns by 32 microns and extends a predetermined distance in a vertical dimension. In some embodiments, the vertical dimension corresponds to at least eight memory layers.

In some embodiments, the first micro-storage bank may have a bit density greater than 0.2 Gbit/mm2 for each layer of the micro-storage bank.

In some embodiments, the plurality of micro-banks including the first micro-bank may be disposed on a back-end-of-line portion of a die.

Optionally, the integrated circuit embodiment may include an SRAM memory bank disposed adjacent to the first micro memory bank.

The integrated circuit may include an SRAM bank disposed adjacent to the first microbank, wherein the first bonding region is in operative communication with the SRAM bank. In some embodiments, the integrated circuit may include a second bonding region disposed on the first surface in operative communication with the SRAM bank.

In some embodiments, the integrated circuit may further include a second bonding area disposed on the first surface and in operative communication with the SRAM bank. The second bonding area enables connection and data transfer between the SRAM bank component and other components in the system.

In some embodiments, the integrated circuit may involve the plurality of micro-banks formed on a first die and the SRAM bank formed on a second die, wherein the first and second dies are bonded together.

In some embodiments, the integrated circuit may further include a DRAM (dynamic random access memory) bank positioned adjacent to the microbank. The DRAM bank provides an additional memory storage area that can be utilized in conjunction with the microbank memory.

In some embodiments, the integrated circuit may include a DRAM bank positioned adjacent to the plurality of micro banks. The first bonding region may be in operative communication with the DRAM bank to facilitate data transfer between the first micro bank and the DRAM bank.

In some embodiments, the integrated circuit further includes a second bonding region disposed on the first surface. The second bonding region is in operative communication with the DRAM bank. The operative communication allows data and signals to be exchanged between the second bonding region and the DRAM bank.

In some embodiments, the integrated circuit may include a plurality of micro-memory banks formed on a first die and a DRAM memory bank formed on a third die. The first and third dies may be rigidly fixed together.

In some embodiments, the integrated circuit further includes a read address register operatively coupled to the first bonding region. The read address register can be configured to store a read address and transmit it to the first micro-storage bank.

In some embodiments, the integrated circuit further includes a read data register operatively coupled to the first micro-storage bank to receive and store read data from the first micro-storage bank.

In some embodiments, the integrated circuit further includes a read data register operatively coupled to the first micro-storage bank to receive and store read data from the first micro-storage bank. The read data register is operatively coupled to the first bonding region to transfer the stored read data to the first bonding region.

The integrated circuit may include a read data register operatively coupled to a second bonding region of the plurality of bonding regions to transfer read data to the second bonding region. In some embodiments, the read data register receives and stores read data from the first micro-storage and then transfers the read data to the second bonding region.

In some embodiments, the integrated circuit may further include a second read data register in operative communication with the first read data register. The second read data register may be configured to receive and store read data from the first read data register.

The integrated circuit may include a second read data register disposed on a die having a second side, wherein the second side includes a read data bonding region operatively coupled to the first bonding region of the first surface.

In some embodiments, the integrated circuit may further include a second read data register disposed on a die having a second side. The second read data register is configured to receive and store read data from the first read data register. Optionally, the second side of the die includes a read data bonding region operatively coupled to the second bonding region of the first surface to facilitate data transfer between the dies. Through this bonding, data can be transferred from the first read data register on the first die to the second read data register on the second die.

In some embodiments, the integrated circuit may further include a second read data register disposed on a die different from the die having the plurality of micro-banks.

In some embodiments, the integrated circuit further includes a second read address register located on a different die than the die containing the plurality of micro-repositories. This additional read address register on a separate die can be used for various purposes, such as increasing the storage capacity or bandwidth used to read data from the micro-repositories. By distributing multiple read address registers across discrete dies, a flexible architecture can be implemented to meet performance requirements while minimizing device footprint and power consumption.

In some embodiments, the integrated circuit further includes a second read address register configured to receive and store a read address. Optionally, the second read address register transmits the read address to the first micro-storage bank.

In addition to the read address register and the second read address register, the integrated circuit may further include a second bonding region disposed on a second surface. The second bonding region provides an interface on the second surface to facilitate communication and data transfer associated with read addressing functions. With this second bonding region, the integrated circuit can interface the read addressing architecture across multiple surfaces and dies.

In some embodiments, the integrated circuit may further include a second read address register. The second read address register may be disposed on a second die having a second surface. The second read address register may be configured to receive and store the read address. Furthermore, the second read address register may transmit the read address to the read address register of the first die via the second surface, wherein the second surface of the second die and the first surface of the first die may be bonded together.

In some embodiments, the integrated circuit further includes a second surface on which a second read address register is disposed. The second read address register is configured to receive and store the read address and transmit the read address to the read address register on the first surface. Optionally, the second surface and the first surface can be bonded together to facilitate communication of the read address between the two surfaces.

In some embodiments, the integrated circuit further includes a through-silicon via (TSV) operatively coupled to a third surface at a first end of the TSV, wherein the third surface is located on an opposite side of the first surface.

In some embodiments, the integrated circuit further includes an interconnect coupled to the first surface in which the plurality of micro-banks are disposed. The interconnect is also coupled to a second end of a through-silicon via (TSV) for facilitating communication between the dies. The TSV has a first end coupled to a third surface on the opposite side of the first surface.

In some embodiments, the integrated circuit further includes a second micro-storage bank in operative communication with the first bonding region.

In some embodiments, the integrated circuit may further include a multiplexer operatively coupled to the first micro-storage bank to receive first read data from the first micro-storage bank. The multiplexer may also be operatively coupled to the second micro-storage bank to receive second read data from the second micro-storage bank. The multiplexer may be configured to select between the first read data from the first micro-storage bank and the second read data from the second micro-storage bank for output.

In some embodiments, the integrated circuit further includes a counter operatively coupled to the multiplexer, the counter being configured to control the multiplexer to serially read out the first read data from the first micro-storage bank and the second read data from the second micro-storage bank.

In some embodiments, the integrated circuit further includes a read data register configured to receive the first read data from the first micro-storage bank or the second read data from the second micro-storage bank selected by the multiplexer. The read data register stores the received first read data or the second read data.

In some embodiments, the integrated circuit further includes a second bonding region on the first surface. The read data register is coupled to the second bonding region to transfer the stored first read data or second read data from the multiplexer to the second bonding region.

In some embodiments, the integrated circuit further includes an assembly comprising a first die having the plurality of micro-banks.

In some embodiments, the integrated circuit further includes an assembly comprising a first die having the plurality of micro-storage banks. The plurality of micro-storage banks on the first die include the first micro-storage bank and a second micro-storage bank.

In some embodiments, the integrated circuit further includes an assembly comprising: a first die having the plurality of micro-storage banks including a first micro-storage bank and a second micro-storage bank; and a second die including a read address register and a read data register. In this assembly, the first die may be bonded to the second die.

In some embodiments, the integrated circuit may involve an assembly having a first die and a second die bonded together. The first die may have a plurality of micro-storage banks including a first micro-storage bank and a second micro-storage bank, while the second die may have a read address register and a read data register. In addition to the first bonding area previously described, the first die may also include a second bonding area on the first surface. Furthermore, the second die may include a third bonding area and a fourth bonding area. The various bonding areas may be connected such that the first bonding area of the first die is coupled to the third bonding area of the second die, while the second bonding area of the first die is coupled to the fourth bonding area of the second die.

In some embodiments, the integrated circuit further includes a read address register operatively coupled to the third bonding region of the second die to transfer a read address to the third bonding region. The read address register is configured to store read addresses and transfer the read addresses to the first micro-bank on the first die via the third bonding region coupled to the first bonding region of the first die.

In some embodiments, the integrated circuit further includes a read data register operatively coupled to a fourth bonding region of the second die to receive read data from the fourth bonding region. The read data register is configured to receive and store read data transmitted from the fourth bonding region of the second die bonded to the first die having the plurality of micro-banks.

In some embodiments, the integrated circuit may include an assembly comprising a first die having a plurality of micro-storage banks, such as a first micro-storage bank and a second micro-storage bank. The first die may also include a second read address register configured to receive and store a read address. The second read address register may be configured to transmit a read address to the first micro-storage bank and the second micro-storage bank.

In some embodiments, the assembly may include a first die having a plurality of micro-banks including a first micro-bank and a second micro-bank. The first die may further include a multiplexer configured to select between an output of the first micro-bank and an output of the second micro-bank.

In some embodiments, the integrated circuit may further include a second bonding region on a second surface of the first die having the plurality of micro-banks. An interconnect may connect the second bonding region to an input of a multiplexer configured to select between the output of the first micro-bank, the output of the second micro-bank, and communications received from the second bonding region.

In some embodiments, the integrated circuit may further include a phase counter configured to control the multiplexer that selects between the outputs from the first micro-bank and the second micro-bank. The phase counter facilitates sequentially reading data from the plurality of micro-banks using the multiplexer.

In some embodiments, the integrated circuit may further include a third address register configured to receive and store an output of the multiplexer. The multiplexer may be configured to select between one of the plurality of micro-banks, and a phase counter may be configured to control the selection of the multiplexer. The third address register may receive and store the output selected by the multiplexer.

The integrated circuit may include an assembly comprising: a first die having a plurality of micro-banks including a first micro-bank and a second micro-bank; and a second die having a read address register and a read data register, wherein the first die is bonded to the second die. In some embodiments, the first die may further include: a multiplexer configured to select between an output of the first micro-bank and an output of the second micro-bank; and a third address register configured to receive and store an output of the multiplexer. Optionally, the third address register may be operatively coupled to a second bonding region of the first die.

The integrated circuit may further include a through-silicon via (TSV) coupled to the read address register and a second surface of the die on which the read address register is disposed. In some embodiments, the TSV facilitates the transfer of data, such as a read address, between the read address register and components on an opposite side of the die.

In some embodiments, the integrated circuit further includes a second through-silicon via (TSV) coupled to a second bonding region of the first die on the second surface and a second read data register. The second TSV facilitates data transfer between the second bonding region on the second surface of the first die and the second read data register on another die. This configuration enables efficient transfer of read data between multiple dies that are stacked and bonded together.

In some embodiments, the integrated circuit may include a multiplexer configured to select between one of the plurality of micro-storage banks. The multiplexer can access data from different micro-storage banks in a selective manner.

In some embodiments, the integrated circuit may further include a phase counter configured to control a selection operation of the multiplexer that selects one of the plurality of micro-banks. The phase counter provides a control signal to the multiplexer to facilitate sequential access of data from the plurality of micro-banks.

In some embodiments, the integrated circuit further includes a through-silicon via (TSV) operatively coupled to a first surface and a second surface of a die having the plurality of micro-banks. The TSV facilitates communication between the first surface having the plurality of micro-banks and bonding areas and an opposing second surface of the die.

In some embodiments, the integrated circuit further includes a through-silicon via (TSV) configured to facilitate communication between a first die and a second die coupled to the plurality of micro-banks. The TSV enables inter-die communication and integration between the micro-bank die and additional dies in a multi-die assembly.

In some embodiments, the integrated circuit may include the first micro-bank comprising at least one row of 3D-NOR transistors formed from a plurality of transistors. Each transistor in the 3D-NOR row may include a gate coupled to a read-write enable line, a source coupled to a bit line, and a drain coupled to a select line.

In some embodiments, the integrated circuit may include a first micro-bank comprising a row of 3D-NAND transistors formed from a plurality of transistors. Each transistor in the row may have a gate terminal coupled to a read/write enable line, a source terminal coupled to a bit line, and a drain terminal coupled to a source terminal of an adjacent second transistor in the row. The 3D-NAND row configuration in the first micro-bank may facilitate dense vertical stacking of the transistors while allowing independent control of read and write operations via separate enable lines.

In some embodiments, the integrated circuit may include a first micro-bank comprising a row of 3D-NAND transistors having a transfer gate formed from a plurality of transistors. Each transistor in the row of 3D-NAND transistors may have a gate coupled to a read/write enable line, a source coupled to a bit line, and a drain coupled to a source of a second transistor. Furthermore, a transfer gate may be coupled to all of the plurality of transistors in the row of 3D-NAND transistors.

In some embodiments, the integrated circuit may include a first micro-bank comprising a row of 3D-NOR (three-dimensional NOR) gates formed from a plurality of transistors with independent read and write enable lines. Each transistor within the 3D-NOR gates may have a source terminal coupled to a bit line, a drain terminal coupled to a read enable line, and a gate terminal coupled to a write enable line. The independent read and write enable lines allow for independent control of reading from and writing to the micro-bank.

In some embodiments, the plurality of micro-banks may include a thermal management layer configured to dissipate heat generated by the micro-banks during operation. The thermal management layer may optionally include a material with high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene to facilitate heat dissipation.

In some embodiments, the integrated circuit further includes a thermal management layer configured to dissipate heat generated by the micro-storage banks during operation. The thermal management layer may optionally include a material with high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene.

In some embodiments, the integrated circuit further includes a hardware-based encryption module operatively coupled to at least one micro-storage. The encryption module is configured to secure data written to or read from the micro-storage. By incorporating hardware-based encryption into the integrated circuit, data stored in the micro-storages can be protected.

In some embodiments, the integrated circuit further includes a power management circuit configured to regulate the voltage and current supplied to the plurality of micro-banks. The power management circuit may regulate the voltage and current based on the operating state of the micro-banks. For example, the power management circuit may include a low-power mode that reduces the power supplied to the micro-banks during periods of inactivity.

The integrated circuit may include a power management circuit configured to adjust the voltage and current supplied to the plurality of micro-storage banks based on the operating status of the plurality of micro-storage banks. In some embodiments, the power management circuit includes a low-power mode that reduces the power supply to the micro-storage banks during inactive periods.

In some embodiments, the integrated circuit may further include a signal conditioning circuit operatively coupled to the plurality of micro-banks. The signal conditioning circuit may be configured to enhance the signal integrity of data transmitted to and from the micro-banks. Optional components of the signal conditioning circuit may include filters, amplifiers, or error correction encoders.

In some embodiments, the integrated circuit further includes a signal conditioning circuit operatively coupled to the plurality of micro-banks to enhance signal integrity of data transmission. The signal conditioning circuit may include a filter, an amplifier, or an error correction encoder for enhancing signal integrity.

In some embodiments, the integrated circuit further includes a diagnostic module configured to monitor the health and performance of the micro-storage banks and report metrics to an external controller. The diagnostic module can perform self-tests on the micro-storage banks and generate alerts when a fault is detected.

In some embodiments, the integrated circuit further includes a diagnostic module configured to monitor the health and performance of the micro-storage banks and report metrics to an external controller. Optionally, the diagnostic module can perform self-tests on the micro-storage banks and generate alerts when a fault is detected.

In some embodiments, each micro-repository may include a built-in self-repair mechanism capable of isolating and bypassing failed memory cells. The self-repair mechanism may optionally utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace the failed cells.

In some embodiments, each micro-repository may include a built-in self-repair mechanism capable of isolating and bypassing failed memory cells. This self-repair mechanism may utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace any detected failed cells.

In some embodiments, the micro-repositories can be arranged in a matrix configuration to enable parallel processing and data retrieval.

In some embodiments, the micro-repositories may be arranged in a matrix configuration to enable parallel processing and data retrieval. The matrix configuration may optionally include row and column decoders to facilitate access to individual micro-repositories.

In some embodiments, the integrated circuit further includes a flexible substrate. The flexible substrate enables the integrated circuit to conform to non-planar surfaces.

In some embodiments, the integrated circuit further includes a flexible substrate that enables the circuit to conform to non-planar surfaces. The flexible substrate may include materials such as polyimide, PEEK (polyetheretherketone), liquid crystal polymer, flexible glass, or combinations thereof. Due to the use of a flexible substrate, embodiments are applicable and work well on curved or irregular surfaces.

In some embodiments, the integrated circuit may involve the first micro-bank being configured to operate as a cache memory of a processor. The cache memory may function in one or more modes such as write-through, write-back, write-bypass, or a combination thereof.

In some embodiments, the first micro-repository can be configured to operate as a cache memory of a processor. The cache memory can operate according to one or more cache modes such as write-through, write-back, write-bypass, or a combination thereof.

In some embodiments, the plurality of micro-banks may form a redundant array of independent memory elements. This redundant array of independent memory elements enables error correction and facilitates data recovery in the event of memory failures. Specifically, the first micro-bank may be configured as a component of a redundant array of independent memory blocks, allowing data errors or failures in one block to be reconstructed from other independent blocks. This redundant array architecture provides fault tolerance and reliability to help ensure operational continuity.

In some embodiments, the first micro-storage bank may include a crossbar switch architecture for facilitating data routing between memory cells. The crossbar switch architecture may enable uninterrupted data transfer within the integrated circuit.

The integrated circuit may include a crossbar switch architecture associated with the first micro-storage bank for facilitating data routing between memory cells. In some embodiments, the crossbar switch architecture is configured to enable non-blocking data transfer within the integrated circuit.

In some embodiments, the integrated circuit may include a dedicated read peripheral device in the first micro-storage. Specifically, the first micro-storage may optionally include its own read peripheral device, separate from other components, for facilitating data reading. This dedicated read peripheral device in the first micro-storage achieves optimized read performance.

In some embodiments, the integrated circuit may include a dedicated read port operatively coupled to the first micro-bank. This allows read operations to be performed independently of write operations on the first micro-bank, enabling simultaneous read and write access. The dedicated read port improves overall data throughput by eliminating contention between read and write data.

In some embodiments, the integrated circuit may include a dedicated write peripheral associated with the first micro-storage. This allows write operations to the first micro-storage to be handled by dedicated write circuitry adapted for efficient writes. The dedicated write peripheral facilitates fast and reliable data storage within the micro-storage by optimizing the write path.

In some embodiments, the integrated circuit may include a dedicated write port operatively coupled to the first micro-storage bank. This dedicated write port facilitates writing data to the first micro-storage bank independently of read operations to enable simultaneous read and write access. The dedicated write port can increase the overall data throughput to and from the micro-storage bank.

The integrated circuit may include a first transistor having a channel layer formed using a semiconductor material and a ferroelectric layer rigidly coupled to the channel layer. The first transistor may further include a source terminal fixed to the channel layer, a drain terminal fixed to the channel layer, and a gate terminal fixed to the ferroelectric layer.

In some embodiments, the channel layer of the first transistor may be formed of polysilicon. Using polysilicon for the channel layer provides known electrical properties that allow the transistor to operate properly.

In some embodiments, the channel layer of the transistor can be formed from an amorphous oxide semiconductor. Such amorphous oxide semiconductor materials can provide desirable properties, such as high carrier mobility and low off-state current when used as the channel layer, while also being compatible with deposition on top of standard CMOS materials during back-end processing. Examples of usable amorphous oxide semiconductors include indium oxide, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), cadmium oxide, indium zinc oxide (HIZO), tin oxide, and indium tin zinc oxide (ITZO). The amorphous oxide semiconductor channel layer may also be doped with elements such as gallium, indium, zinc, tin, cobalt, silicon, aluminum, and others to optimize carrier concentration and mobility.

In some embodiments, the amorphous oxide semiconductor forming the channel layer of the first transistor may include at least one of the following: indium oxide, indium gallium zinc oxide, zinc tin oxide, indium zinc oxide, gallium zinc oxide, aluminum zinc oxide, cadmium oxide, cadmium indium zinc oxide, tin oxide, stannous oxide, tin dioxide, indium tin zinc oxide, indium tungsten oxide, indium gallium zinc tin oxide, indium gallium zinc oxynitride, aluminum indium gallium zinc oxide, and zinc indium oxide.

In some embodiments, the amorphous oxide semiconductor channel layer may be doped with at least one dopant selected from the group consisting of gallium (Ga), indium (In), zinc (Zn), tin (Sn), niobium (Hf), silicon (Si), aluminum (Al), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), zirconium (Zr), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), and copper (Cu). , silver (Ag), gold (Au), cerium (Ce), lumber (La), neodymium (Nd), sulphurium (Sm), cerium (Eu), gadolinium (Gd), terbium (Tb), diopside (Dy), thallium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y), succinyl (Sc), bismuth (Bi), lead (Pb), tantalum (Tl), antimony (Sb), arsenic (As), phosphorus (P), boron (B), nitrogen (N), fluorine (F), chlorine (Cl), bromine (Br), and iodine (I). Doping of the channel layer can enhance certain properties of the transistor, such as carrier mobility, threshold voltage, subthreshold swing, on-state current, and off-state current.

In some embodiments, the channel layer of the first transistor is formed from a two-dimensional material comprising a transition metal dichalcogenide. The transition metal dichalcogenides may be in a monovalent or divalent form. In certain embodiments, the chalcogenide element in the transition metal dichalcogenide is sulfur, selenium, or tellurium.

These transition metal dichalcogenides (TMDs) can be written as MX ₂ , where M is a transition metal atom such as molybdenum (Mo), tungsten (W), platinum (Pt), and palladium (Pd), and X is a chalcogen atom such as sulfur (S), selenium (Se), or tellurium (Te). These TMDs exhibit a wide range of electronic properties, ranging from semiconductors [molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ) and tungsten diselenide (WSe ₂ )] to semimetals [molybdenum ditelluride (MoTe ₂ ), tungsten ditelluride (WTe ₂ ) and titanium diselenide (TiSe ₂ )] to metallic niobium disulfide (NbS ₂ ), titanium disulfide (TiS ₂ ), nickel disulfide (NiS ₂ ) and vanadium diselenide (VSe ₂ )] and to superconductors [niobium diselenide (NbSe ₂ ) and tungsten disulfide (TaS ₂ )].

In some embodiments, the channel layer of the integrated circuit is formed of a two-dimensional material comprising a transition metal dichalcogenide. In these embodiments, the transition metal dichalcogenides can be monovalent.

In some embodiments, the channel layer of the integrated circuit embodiments may be formed from a two-dimensional transition metal dichalcogenide material. Specifically, these transition metal dichalcogenides may have a divalent transition metal composition. The divalent transition metal dichalcogenide is used in the channel layer to achieve electrical properties that are beneficial for the operation of a transistor formed from the integrated circuit component.

In some embodiments, the transition metal dichalcogenides forming the channel layer may have a chalcogenide element, ie, sulfur.

In some embodiments, the integrated circuit may include a transition metal dichalcogenide in which the channel layer is formed. The transition metal dichalcogenides may be monovalent or divalent. Optionally, the chalcogenide element in the transition metal dichalcogenides may be selenium.

In some embodiments, the integrated circuit may involve the channel layer being formed of a two-dimensional material including a transition metal dichalcogenide. The transition metal dichalcogenide may have a chalcogenide element, such as tellurium.

In some embodiments, the channel layer of the transistor can be formed from indium tungsten oxide (IWO). This material can provide desirable properties for the channel layer, such as high charge carrier mobility. Using IWO allows for the fabrication of high-performance transistors suitable for a variety of integrated circuit applications.

In some embodiments, the channel layer of the transistor can be formed of indium gallium zinc oxide (IGZO). When deposited as a thin film, IGZO material provides the channel layer with desirable properties (such as high electron mobility and stability) to allow the transistors to operate efficiently within the integrated circuit.

In some embodiments, the channel layer can be a thin film.

An embodiment may involve the ferroelectric layer being composed of zirconia (Hf _0.5 Zr _0.5 O ₂ ) having an equal molar ratio of zirconia to ferroelectricity.

In some embodiments, the integrated circuit including the ferroelectric FET can be implemented in the back-end-of-the-line (BEOL) portion of the semiconductor device fabrication process. More specifically, this involves fabricating the integrated circuit, including the ferroelectric and channel layers of the FET, at a higher level above the transistor level after completing the front-end-of-the-line (FEOL) processing. Placing the integrated circuit in the BEOL allows integration with the underlying transistor structures and metal interconnect layers already fabricated on the chip.

In some embodiments, the ferroelectric layer in the integrated circuit is made of transition metal oxide, calcium titanium, or a two-dimensional material.

In some embodiments, the integrated circuit further includes a metal layer disposed between the channel layer and the ferroelectric layer.

In some embodiments, the integrated circuit further includes an insulating layer disposed between the metal layer and the channel layer. Specifically, a metal layer may be disposed between the channel layer and the ferroelectric layer. Alternatively, an insulating layer may be disposed between the metal layer and the underlying channel layer.

In some embodiments, the integrated circuit further includes a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer.

In some embodiments, the integrated circuit further includes a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer. Additionally, in some embodiments, an insulating layer is disposed on the channel layer, and the ferroelectric layer is also disposed on the insulating layer.

Embodiments may further include a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer. This additional metal layer on top of the ferroelectric material can be used for various purposes, such as providing an improved electrical contact or acting as a barrier layer. Its integration on top of the ferroelectric and channel layers optimizes the electrical performance and reliability of the ferroelectric field-effect transistor.

In some embodiments, the channel layer of the integrated circuit can have a thickness of less than 30 nm. Making the channel layer so thin allows the transistors formed using the channel layer to be reduced in size and potentially improve performance.

In some embodiments, the channel layer can have a thickness between 1 nm and 30 nm. Configuring the channel layer to be less than 30 nm thick enables effective charge modulation of the adjacent ferroelectric layer within this ultra-small dimension. Maintaining dimensions at the lower end of this range (e.g., between 1 nm and 10 nm) allows the integrated circuit to take advantage of improved channel controllability and reduced short-channel effects. Consequently, relatively thin channel layer dimensions facilitate low-voltage operation and high-efficiency switching.

In some embodiments, the channel layer of the transistor can be formed using physical vapor deposition or chemical vapor deposition. These deposition techniques can be used to deposit the very thin films required for the channel layer. The channel layer formed in this manner can be less than 30 nm thick or have a thickness between 1 nm and 30 nm.

In some embodiments, the channel layer of the integrated circuit is formed using atomic layer deposition (ALD). This process enables precise thickness control and uniform coverage during deposition of thin channel layers. By building up the channel layer one atomic layer at a time through sequential, self-limiting surface reactions, ALD allows for sub-nanometer thickness control.

Embodiments may involve forming the channel layer by adding a dopant comprising at least one of tungsten, gallium (Ga), and zinc (Zn). In some embodiments, the channel layer is formed using physical vapor deposition or chemical vapor deposition, and the dopant facilitates deposition of the thin channel layer.

Embodiments may involve forming the ferroelectric layer using atomic layer deposition.

In some embodiments, the ferroelectric layers of the integrated circuit may be formed using vapor deposition.

In some embodiments, the ferroelectric layer in the integrated circuit is formed by adding a dopant comprising at least one of lumber, niobium, manganese, zirconium, tin, strontium, calcium, yttrium, or magnesium. The doped ferroelectric layer can be formed using atomic layer deposition or vapor phase deposition methods. Doping ferroelectric materials can potentially enhance properties such as crystallization temperature, residual polarization, and leakage current.

In some embodiments, the channel layer can be configured to have a carrier concentration in a range from 10^17/cm3 to 10^20/cm3.

In some embodiments, the channel layer comprises a two-dimensional material. When the thickness of the channel layer is less than 30 nm, the two-dimensional material can maintain an electron mobility of at least 0.1 cm ² /volt·second. In certain embodiments, the channel layer comprises fewer than 5 monolayers of the two-dimensional material.

In some embodiments, the channel layer comprises a two-dimensional material. When the thickness of the channel layer is less than 30 nm, the two-dimensional material can be configured to maintain an electron mobility of at least 0.1 cm ² /volt·second.

In some embodiments, the channel layer may comprise a two-dimensional material that maintains high electron mobility even when the channel layer thickness is less than 30 nm. Optionally, the channel layer may comprise fewer than five monolayers of the two-dimensional material. Using only a few monolayers can help minimize thickness while maintaining the beneficial properties of the two-dimensional material.

In some embodiments, the ferroelectric layer used in the integrated circuit is epsilon-zirconium oxide.

In some embodiments, the integrated circuit has a ferroelectric layer with a threshold voltage between -3 volts and 3 volts. This defines the voltage range over which the polarization of the ferroelectric material within the layer can be switched. By tuning the composition and thickness of the ferroelectric layer, it can exhibit a threshold voltage within this range, enabling switching at low voltages compatible with transistor operation. Keeping the threshold voltage relatively low can help reduce the operating voltage and power consumption of devices incorporating the ferroelectric layer.

In some embodiments, the integrated circuit may have a ferroelectric layer having an off-state current of less than 10^-7 amperes per cubic centimeter.

In some embodiments, the integrated circuit may involve a ferroelectric layer having an on-state current greater than 10^-7 amperes per cubic centimeter.

In some embodiments, the integrated circuit has a ferroelectric layer having a crystallization annealing temperature less than or equal to 500 degrees Celsius.

In some embodiments, the integrated circuit may involve a ferroelectric layer having a remnant polarization greater than 10 microcoulombs/cm2.

In some embodiments, the integrated circuit may involve annealing a channel layer at a temperature less than 450 degrees Celsius. Specifically, the channel layer forming part of the transistor structure in the integrated circuit may undergo an annealing process below 450 degrees Celsius. Maintaining a sufficiently low annealing temperature for the channel layer promotes integration of ferroelectric materials while preserving the integrity of the channel layer itself during device fabrication.

In some embodiments, the embodiments include a channel layer having a channel mobility less than 100 ^cm² /volt-second. Specifically, the channel layer as part of the integrated circuit having a transistor including a channel layer, a ferroelectric layer, a source terminal, a drain terminal, and a gate terminal has a channel mobility configured to be less than 100 cm²/Vs.

In some embodiments, the integrated circuit includes a channel layer with a subthreshold swing of less than 0.3 volts per decade. Subthreshold swing refers to the change in gate voltage required to reduce the current in the transistor by a factor of 10, and a lower subthreshold swing enables faster switching speeds and lower power consumption. This ultra-low subthreshold swing is achieved in the channel layer by using novel materials and optimizing interfaces between layers.

In some embodiments, the channel layer in the integrated circuit can be configured to have an off-state current of less than 10^-7 amperes/micrometer.

In some embodiments, embodiments include a channel layer configured to have a channel bandgap greater than 2.5 electron volts.

In some embodiments, the channel layer can be configured to have a post-annealing threshold voltage between -1.5 volts and 1.5 volts.

In some embodiments, the integrated circuit may involve a first transistor having a width less than 200 nm and a length of 50 nm.

The first transistor may have a device area that is less than 30 times the square of the characteristic size.

In some embodiments, the integrated circuit may have a first transistor having a low voltage threshold (LVT) level greater than -2.5V.

In some embodiments, the integrated circuit may have a first transistor having a high voltage threshold (HVT) level greater than -2 V.

In some embodiments, a memory cell incorporating the first transistor has a read voltage between 0 V and 1 V. Operating the memory cell with the first transistor at a read voltage within this range can promote low power consumption during read operations. Configuring transistor characteristics to achieve a low read voltage can also help minimize the overall power requirements of the integrated circuit.

In some embodiments, a memory cell incorporating the first transistor can have a low read energy consumption of less than 10 picojoules. Specifically, a memory cell containing the ferroelectric field-effect transistors described in detail above can be designed and configured to achieve a read operation that dissipates less than 10 picojoules of energy. This extremely low read energy allows for the fabrication of low-power, non-volatile memories that are well-suited for battery-powered, energy-constrained applications.

In some embodiments, a memory cell incorporating the first transistor may have a read pulse width of less than 20 nanoseconds.

In some embodiments, a memory cell having the first transistor may have a read endurance greater than or equal to 10^9 cycles. This indicates that the memory cell can reliably withstand at least 1 billion read operations without failure, contributing to high reliability and long operating life.

In some embodiments, a memory cell incorporating the first transistor can have a read disturbance tolerance greater than 10^9 cycles. This indicates that the memory cell can withstand at least 10^9 read cycles without disturbing or corrupting stored data, enabling reliable long-term data storage. This high read disturbance tolerance is achieved in part due to the properties and configuration of the ferroelectric layer, channel layer, and other components in the first transistor.

In some embodiments, a memory cell incorporating the first transistor can have a read-after-write latency of less than or equal to 10 microseconds. This indicates that the time delay between completing a write operation to the memory cell and being able to reliably retrieve the stored data is very short. Achieving such fast read access times allows for the construction of high-performance memory systems.

In some embodiments, a memory cell incorporating the first transistor described herein has a write voltage less than or equal to 3.0 volts (V).

In some embodiments, a memory cell incorporating the first transistor may have a write speed less than or equal to 10 microseconds.

In some embodiments, a memory cell having the first transistor described herein has a write energy of less than 10 picojoules.

In some embodiments, a memory cell incorporating the first transistor can have a write endurance greater than 10^8 cycles. This indicates that the memory cell can withstand at least 100 million write cycles without failure, enabling reliable data storage and retrieval over an extended lifespan. By leveraging the performance characteristics of the underlying ferroelectric field-effect transistor, each memory cell can provide improved endurance and lifespan compared to known alternatives. High write endurance further translates into enhanced data integrity and a reduced need for error correction or redundancy.

In some embodiments, a memory cell having the first transistor described herein has an off-state resistance to on-state resistance ratio (Roff/Ron) of approximately 10^3 or greater than 10^2.

In some embodiments, a memory cell incorporating the first transistor can have an on-state current to off-state current ratio (Ion/Off) greater than 100 at Vread from DC measurements. Specifically, the memory cell with ferroelectric field-effect transistors can achieve a high on-state to off-state current ratio during a read operation to indicate good discrimination between logical 0 and logical 1 states stored in the cell. A high Ion/Ioff ratio facilitates reliable read operations at low voltages.

In some embodiments, the memory cell may include a first transistor as described herein and a second transistor having the same configuration as the first transistor. The first transistor and the second transistor may form a bit state for storing a binary value in the memory cell.

In some embodiments, the integrated circuit may include a memory cell having the first transistor, wherein the first transistor is configured to have three or more states. Each of these states corresponds to a stored value in the memory cell. This allows for multi-level data storage within a single memory cell.

In some embodiments, the integrated circuit may involve a first transistor having an on-state current to off-state current ratio (Ion/Ioff) greater than 10^2 at Vread from pulse measurement.

In some embodiments, the integrated circuit includes a first transistor, as described herein. Optionally, the first transistor may have an off-state leakage current (Ioff) of less than 10 to -14 amps/micron to provide very low leakage when the transistor is not conducting in the off state. By keeping the off-state leakage current below this threshold, the transistor exhibits very little leakage through the channel and effectively maintains the off state, allowing for low static power consumption.

In some embodiments, a memory cell having the first transistor can have a reliability endurance greater than or equal to 10^11 cycles. This high reliability endurance allows the memory cell to withstand a very large number of read/write cycles over its lifetime without failure. This robust endurance enables applications that require frequent data access and minimal downtime for repair or replacement.

In some embodiments, a memory cell having the first transistor described herein has a retention time of at least 1 minute when measured at a room temperature of 25°C.

In some embodiments, the channel layer of the first transistor may involve the incorporation of another two-dimensional material configured to enhance the on-state current (ION) through the transistor. The additional two-dimensional material provides increased conductivity to allow for a higher ION when the transistor is on.

In some embodiments, the channel layer in the integrated circuit is configured to maintain high mobility despite the presence of the ferroelectric layer. Specifically, the channel layer and ferroelectric layer are designed so that the ferroelectric layer does not significantly impede electron mobility within the channel layer. This allows the integrated circuit transistor to operate at high channel mobility for improved performance while still taking advantage of the benefits of the ferroelectric layer.

In some embodiments, the integrated circuit can be configured so that the ferroelectric layer does not significantly hinder the electron mobility within the channel layer. The ferroelectric layer and the channel layer can be designed to maintain high mobility despite the presence of the ferroelectric layer on top of the channel layer. For example, the interface between the ferroelectric layer and the channel layer can be optimized to minimize scattering of electrons flowing through the channel.

In some embodiments, the channel layer is configured to directly contact the ferroelectric layer without an interface layer therebetween. Direct contact between the channel layer and the ferroelectric layer can minimize the voltage drop across the interface, thereby enabling low-voltage operation of the transistor. Furthermore, the absence of an interface layer between the channel layer and the ferroelectric layer can enable low-voltage operation and reduce power consumption.

In some embodiments, the integrated circuit may include a first transistor having a channel layer in direct contact with the ferroelectric layer without an interface layer therebetween. This direct contact configuration can help minimize the voltage drop across the interface between the channel layer and the ferroelectric layer. By reducing this parasitic voltage drop, the first transistor can potentially operate at a lower voltage, thereby achieving low-voltage operation and reducing power consumption. The absence of an interface layer can also contribute to faster switching times and improved transient characteristics.

The integrated circuit may include a first transistor characterized by low voltage operation and low power consumption. In some embodiments, this is due to the absence of an interface layer between the channel layer and the ferroelectric layer.

In some embodiments, the integrated circuit may include a first transistor characterized by low-voltage operation and low power consumption. This may be due to the absence of an interface layer between the ferroelectric layer and the gate layer of the first transistor. Reduced voltage operation may help reduce the overall power consumption of the integrated circuit.

In some embodiments, the integrated circuit features low-voltage operation and low power consumption due to the absence of an interface layer between the channel layer and the ferroelectric layer or between the ferroelectric layer and the gate layer. This reduced-voltage operation can help reduce the overall power consumption of the integrated circuit.

In some embodiments, the integrated circuit may include the first transistor and feature improved switching characteristics, such as faster turn-on and turn-off times. This may be due to the absence of an interface layer between the ferroelectric layer and the channel layer, or between the ferroelectric layer and the gate layer. The absence of an interface layer may help reduce parasitic capacitance at these interfaces, thereby enabling faster charging and discharging of the ferroelectric layer during write and erase operations of the transistor.

In some embodiments, the integrated circuit can feature reduced parasitic capacitance at the interface between the channel layer and the ferroelectric layer due to the absence of an interface layer between the channel layer and the ferroelectric layer. The direct contact between the channel layer and the ferroelectric layer minimizes the voltage drop across the interface, enabling low-voltage operation of the transistor. Reducing parasitic capacitance can also help improve the transistor's switching characteristics, including faster turn-on and turn-off times.

In some embodiments, the ferroelectric layer can be configured for a substantially uniform electric field distribution across the ferroelectric layer.

In some embodiments, the integrated circuit may involve the ferroelectric layer being configured for a gradient in electric field distribution across the ferroelectric layer.

In some embodiments, the integrated circuit further includes a micro-storage bank formed from a plurality of transistors including the first transistor described herein. The micro-storage bank can be organized into rows comprising a 3-terminal bit grid. Optionally, the micro-storage bank is formed using a row in one of a 3D-NOR, a 3D-AND, a 3D-NAND, or a 3D-NAND-PG configuration.

In some embodiments, the microbank includes rows of three-terminal bit cells. Specifically, the plurality of transistors comprising each microbank can be arranged in vertical rows, with each row serving as a bit cell having three terminals (corresponding to the source, drain, and gate terminals of the transistors in that row). This three-terminal bit cell configuration in a pillar format facilitates compact integration and routing of microbank memory structures.

In some embodiments, the integrated circuit may include a micro-storage bank formed from a plurality of transistors. The micro-storage bank may be organized into rows of 3-terminal bit cells comprising one of several configurations, including a 3D-NOR, a 3D-AND, a 3D-NAND, or a 3D-NAND with an additional pass gate (3D-NAND-PG).

In some embodiments, the integrated circuit may include a channel material comprising indium gallium zinc oxide (IGZO). The channel material formed of IGZO may be incorporated into the transistors described herein.

Embodiments may include a source terminal affixed to the channel layer. In some embodiments, the source terminal is formed from at least one of tungsten, titanium nitride, nickel, and molybdenum.

In some embodiments, the drain terminal of the first transistor includes at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials can be used to form a drain contact to enable efficient carrier transport and integration within the process flow.

In some embodiments, the gate terminal of the first transistor includes at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials are used in semiconductor manufacturing processes due to their conductivity and integration compatibility. The selection of an appropriate gate terminal material can affect transistor performance and reliability.

In some embodiments, the integrated circuit further includes a memory formed by a plurality of the first transistors. The memory may be formed as a 3D vertical device architecture selected from NAND and NOR configurations.

In some embodiments, the integrated circuit includes a micro-bank array comprising a plurality of transistors. Each of the plurality of transistors in the micro-bank array can be configured similarly to the first transistor described above. The micro-bank array comprising the plurality of identical transistors can be organized into a 3D vertical architecture, such as a 3D-NOR, a 3D-AND, a 3D-NAND, or a 3D-NAND with a pass gate.

In some embodiments, the integrated circuit may include a micro-storage bank row comprising a plurality of transistors, each of which is identical to the first transistor configuration. The micro-storage bank row may be organized in a 3D-NOR configuration.

In some embodiments, the integrated circuit includes a micro-bank comprising a plurality of transistors, each of which is configured according to the first transistor. The micro-bank can be configured as a 3D-AND structure.

In some embodiments, the integrated circuit may include a micro-bank row including a plurality of transistors each having a configuration similar to the first transistor. The micro-bank row may be arranged in a 3D NAND configuration.

In some embodiments, the integrated circuit may include a micro-bank row comprising a plurality of transistors, wherein each of the plurality of transistors is configured according to the first transistor design described previously. The micro-bank row may be organized according to a 3D-NAND architecture, wherein a transfer gate is coupled to all of the plurality of transistors.

In some embodiments, the integrated circuit may include a micro-bank row comprising a plurality of transistors, each of which includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line. This micro-bank row configuration enables independent control of read and write operations via separate read and write enable lines.

In some embodiments, the integrated circuit may include a micro-bank row comprising a plurality of transistors each formed similarly to the first transistor. The micro-bank row may be configured in a 3D-AND architecture, wherein an independent read/write enable line is coupled to each transistor. Specifically, each transistor in the 3D-AND micro-bank may have a source terminal coupled to a bit line, a drain terminal coupled to a select line, and a gate terminal coupled to a read/write enable line independent of the other transistors.

In some embodiments, the ferroelectric layer used in the integrated circuit is formed of various ferroelectric materials, including but not limited to calcium titanium, lead zirconium titanate (PZT), barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), bismuth ferrite (BiFeO ₃ ), potassium niobate (KNbO ₃ ), lithium niobate (LiNbO ₃ ), lithium niobate (LiTaO ₃ ), sodium bismuth titanate (Na _0.5 Bi _0.5 TiO ₃ ), bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ), bismuth zinc niobate (Bi(Zn _1/2 Ti _1/2 )O ₃ ), bismuth titanium oxide (BiLaTiO ₃ ), bismuth nickel titanium oxide (BiNiTiO ₃ ), lead magnesium nibrate-lead titanium oxide (PMN-PT), lead nibrate titanium oxide (PLZT), bismuth titanium oxide doped with neodymium (Bi _4-x Nd _x Ti ₃ O ₁₂ ), nibrous oxides such as nibrous oxide (HfO ₂ ) and doped nibrous oxides such as nibrous oxide (HfZrO ₂ ), tungsten-copper structural materials including barium strontium nibrate (BSN), lead barium nibrate (PBN) and potassium nibrate (KTN), bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ), bismuth-layered ferroelectrics such as strontium bismuth tantalum (SBT) and calcium bismuth niobate (CBN), organic ferroelectrics such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene) and P(VDF-TrFE) copolymers, aurivilius phase oxides, rare earth manganites such as YMnO ₃ and lead zirconium titanate (PLZT) modified with titanium, nickel manganese oxide (NiMnO ₃ ), relaxor ferroelectrics including lead magnesium niobate (PMN), lead niobium titanate (PST), lead indium niobate (PIN), such as zirconium manganite (TbMnO ₃ ) and eutectic titanium oxide (EuTiO ₃ ), SbSI (antimony iodide), GeTe (germanium telluride), SnTe (tin telluride), thin film ferroelectrics such as PZT thin films, SBT thin films, and _HfO2 -based thin films, layered superlattices, and _PbTiO3 / _SrTiO3 . The wide range of ferroelectric materials provides flexibility in designing integrated circuits, depending on the intended application and desired device characteristics.

In some embodiments, the integrated circuit includes a first vertical structure having a dielectric pillar, a channel pillar disposed around the dielectric pillar, and a ferroelectric pillar disposed around the channel pillar along the length of the channel pillar. The integrated circuit further includes a plurality of horizontal gate electrode layers disposed a predetermined distance apart from each other. Each of the horizontal gate electrode layers is disposed adjacent to the ferroelectric pillar along the length of the ferroelectric pillar.

The integrated circuit embodiment may have a dielectric pillar that is substantially cylindrical in shape. Specifically, the dielectric pillar around which the via pillar is disposed may be formed to have a circular or elliptical cross-section along its vertical length. Making the dielectric pillar cylindrical may facilitate conformal deposition of the surrounding via material.

In some embodiments, the dielectric pillar in the first vertical structure is substantially cylindrical. The dielectric pillar may have a first diameter at a first end and a second diameter at a second end. Optionally, the first and second diameters may be the same, or the first diameter may be larger than the second diameter.

In some embodiments, the dielectric pillar of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second, opposite end. Optionally, the first and second diameters of the dielectric pillar can be configured to be the same.

In some embodiments, the dielectric pillar in the first vertical structure has a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

In some embodiments, the integrated circuit includes a first vertical structure having a dielectric pillar. The dielectric pillar can be configured as a solid pillar rather than a hollow pillar. Forming the dielectric pillar as a solid structure can provide mechanical stability and robustness to the entire vertical stack.

In some embodiments, the integrated circuit may involve a hollow dielectric pillar. Specifically, the dielectric pillar disposed around the channel pillar in the first vertical structure may be configured as a hollow pillar rather than a solid pillar, depending on the situation. This hollow configuration of the dielectric pillar may facilitate certain manufacturing processes or enable the integration of additional components within the pillar. However, in other embodiments, the dielectric pillar may instead be implemented as a solid pillar.

In some embodiments, the channel pillar formed around the dielectric pillar in the first vertical structure can be substantially cylindrical in shape. For example, the channel pillar can have a circular or elliptical cross-section along its vertical length. A cylindrical channel pillar configuration can offer certain advantages related to current, capacitance, or ease of manufacturing.

In some embodiments, the channel pillar formed around the dielectric pillar is substantially cylindrical, as described in the invention section. Optionally, the channel pillar has a first diameter at a first end and a second diameter at a second end. In some embodiments, the first and second diameters may be the same. In other embodiments, the first diameter may be larger than the second diameter.

In some embodiments, the channel post of the first vertical structure has a substantially cylindrical shape with a uniform diameter from a first end to a second end.

In some embodiments, the integrated circuit includes a first vertical structure having a dielectric pillar having a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

The ferroelectric post may be substantially cylindrical. In some embodiments, the integrated circuit further includes a first vertical structure having a ferroelectric post disposed around a channel post. Optionally, the ferroelectric post may be formed in a substantially cylindrical shape.

In some embodiments, the integrated circuit may include a substantially cylindrical ferroelectric post, as described with respect to the first vertical structure. The ferroelectric post may have a first diameter at a first end and a second diameter at a second, opposite end. In some cases, the first and second diameters may be the same, or the first diameter may be larger than the second diameter.

In some embodiments, the integrated circuit has a substantially cylindrical ferroelectric post having a first diameter at a first end and a second diameter at a second end, wherein the first and second diameters can be configured to be the same.

In some embodiments, the integrated circuit may include a substantially cylindrical ferroelectric post having a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

In some embodiments, the integrated circuit further includes a dielectric terminal post disposed around one end of the channel post. The dielectric terminal post is adjacent to one end of the length of the channel post and is also positioned adjacent to the ferroelectric post.

In some embodiments, the integrated circuit further includes a drain select layer positioned parallel to the plurality of horizontal gate electrode layers and adjacent to the dielectric terminal post. The drain select layer is adjacent to the dielectric terminal post disposed around one end of the channel pillar. By positioning the drain select layer parallel to the horizontal gate electrode layers and adjacent to the dielectric terminal post, access to the drain side of the vertical structure is achieved.

In some embodiments, the integrated circuit further includes a second dielectric terminal disposed around the other end of the channel pillar. The second dielectric terminal is adjacent to the other end of the length of the channel pillar and is also adjacent to the ferroelectric pillar.

The integrated circuit may further include a source select layer disposed parallel to the plurality of horizontal gate electrode layers. The source select layer is adjacent to the second dielectric terminal disposed around the other end of the channel pillar. In some embodiments, the second dielectric terminal is adjacent to the other end of the length of the channel pillar and adjacent to the ferroelectric pillar.

In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure can be formed substantially the same as the first vertical structure, but is positioned adjacent to the first vertical column at a predetermined horizontal distance.

In some embodiments, the integrated circuit may include a second vertical structure. The second vertical structure may be formed substantially identically to the first vertical structure, but disposed adjacent to the first vertical column at a predetermined horizontal distance.

In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed substantially identically to the first vertical structure but is positioned adjacent to the first vertical column at a predetermined horizontal distance. The first and second vertical structures may be configured to form a single-port 3D NAND structure.

Optionally, in some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure are formed of at least one of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, TiSi ₂ , CoSi ₂ , NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloy, AlCu, TiW, and a conductive polymer.

In some embodiments, the ferroelectric pillar of the first vertical structure is formed of at least one of the following materials: calcium titanium; lead zirconate titanate (PZT); barium titanate (BaTiO ₃ ); strontium titanate (SrTiO ₃ ); bismuth ferrite (BiFeO ₃ ); potassium niobate (KNbO ₃ ); lithium niobate (LiNbO ₃ ); lithium niobate (LiTaO ₃ ); bismuth sodium titanate (Na _0.5 Bi _0.5 TiO ₃ ); bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ); bismuth zinc niobate (Bi(Zn _1/2 Ti _1/2 )O ₃ ); bismuth titanium oxide (BiLaTiO ₃ ); bismuth nickel titanium oxide (BiNiTiO ₃ ); lead magnesium nibrate-lead titanium oxide (PMN-PT); lead nibrate zirconate (PLZT); neodymium titanium oxide (Bi _4-x Nd _x Ti ₃ O ₁₂ ); nibrate-based oxides such as nibrate (HfO ₂ ) and doped nibrate oxides including zirconate (HfZrO ₂ ); tungsten-copper structural materials such as barium strontium nibrate (BSN), lead barium nibrate (PBN), and potassium tantalum nibrate (KTN); bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ), bismuth-layered ferroelectrics such as strontium bismuth tantalum (SBT) and calcium bismuth niobate (CBN); organic ferroelectrics such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene) and P(VDF-TrFE) copolymers; Olivierius phase oxides; rare earth manganites such as YMnO ₃ and lead zirconium titanate modified with titanium (PLZT); relaxor ferroelectrics such as lead magnesium niobate (PMN), lead phosphine tantalum (PST) and lead indium niobate (PIN); zirconium manganite (TbMnO ₃ ) and eutectic titanium oxide (EuTiO ₃ ) multiferroic materials; as well as thin film ferroelectrics, layered superlattices, etc. In various embodiments, the extensive list provides flexibility in selecting ferroelectric materials suitable for vertical structures.

In some embodiments, the channel pillar of the first vertical structure is formed of one of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), indium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Si), crystalline germanium (c-Ge), gallium arsenide (GaAs), indium phosphide (InP), indium sulfide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH ₃ NH ₃ PbX ₃ , X=Cl, Br, I), cesium lead halide (CsPbX ₃ , X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobalt, RP phase, inclusion compound, calcium titanium oxide, or magnetic semiconductor.

In some embodiments, the dielectric pillar of the first vertical structure is formed of at least one of: ferrite (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lumen oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO ₃ ), barium strontium titanate (BST), lead zirconium titanate (PZT), bismuth ferrite (BiFeO ₃ ), magnesium oxide (MgO), cerium oxide (CeO ₂ ), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd ₂ O ₃ ), daphnia (Dy ₂ O ₃ ), sulphur oxide (Sm ₂ O ₃ ), chalcanthus oxide (Eu ₂ O ₃ ), zirconium oxide (Tb ₄ O ₇ ), vanadium oxide (V ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), chromium oxide (Cr ₂ O ₃ ), iron oxide (Fe ₂ O ₃ ), molybdenum oxide (MoO ₃ ), tungsten oxide (WO ₃ ), ruthenium oxide (RuO ₂ ), rhodium oxide (Rh ₂ O ₃ ), palladium oxide (PdO), silver oxide (Ag ₂ O), cadmium oxide (CdO), tin oxide (SnO ₂ ), antimony oxide (Sb ₂ O ₃ ), tellurium oxide (TeO ₂ ), iridium oxide (IrO ₂ ), platinum oxide (PtO ₂ ), gold oxide (Au ₂ O ₃ ), beryllium oxide (BeO), magnesium aluminate (MgAl ₂ O ₄ ), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeO _x ), bismuth oxide (Bi ₂ O ₃ ), bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ), calcium-titanium oxide, layered oxide, or complex transition metal oxide.

In some embodiments, one of the plurality of horizontal gate electrode layers and the first vertical structure can be configured to form a plurality of transistors. These transistors can include the first transistor described herein. The first vertical structure includes a dielectric pillar, a channel pillar disposed around the dielectric pillar, a ferroelectric pillar disposed around the channel pillar, and a plurality of horizontal gate electrode layers disposed adjacent to the ferroelectric pillar.

In some embodiments, the integrated circuit may include a first vertical structure. The first vertical structure may include a transfer gate electrode pillar. A dielectric pillar may be disposed around the transfer gate electrode pillar. Optionally, a channel pillar may be disposed around the dielectric pillar. Additionally, a ferroelectric pillar may be disposed around the channel along a length of the channel pillar. The integrated circuit may further include a plurality of horizontal gate electrode layers, wherein each layer is disposed a predetermined distance from each other. Each of the plurality of horizontal gate electrode layers may be disposed adjacent to the ferroelectric pillar along the length of the ferroelectric pillar.

In some embodiments, the integrated circuit may include a substantially cylindrical transfer gate electrode post. The cylindrical transfer gate electrode post may optionally have a first diameter at one end and a second diameter at the other end, wherein the diameters are the same or the first diameter is larger than the second diameter. In various variations, the transfer gate electrode post may also be configured as a solid post or a hollow post.

According to one embodiment, the integrated circuit may include a substantially cylindrical transfer gate electrode pillar. In some embodiments, the transfer gate electrode pillar has a first diameter at a first end and a second diameter at a second end. In various embodiments, the first and second diameters may be the same or different, and in some cases, the first diameter may be larger than the second diameter.

In some embodiments, the transfer gate electrode pillar of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second, opposite end. Optionally, the integrated circuit can be configured such that the first diameter and the second diameter of the transfer gate electrode pillar are the same.

In some embodiments, the transfer gate electrode post of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter of the transfer gate electrode post may be larger than the second diameter.

In some embodiments, the integrated circuit may include a transfer gate electrode pillar as part of the first vertical structure. The transfer gate electrode pillar may be substantially cylindrical. Optionally, the transfer gate electrode pillar is solid rather than hollow.

In some embodiments, the integrated circuit may have a hollow transfer gate electrode pillar. Specifically, the transfer gate electrode pillar that is part of the first vertical structure and surrounds the dielectric pillar and is disposed within the channel pillar may be hollow rather than solid. Forming the transfer gate electrode pillar in a hollow configuration may offer certain advantages related to material cost or processing simplicity.

In some embodiments, the integrated circuit may include a substantially cylindrical dielectric pillar disposed around a transfer gate electrode pillar that is part of a first vertical structure. The diameter of the dielectric pillar may be uniform along its length or may vary from one end to the other.

In some embodiments, the dielectric pillar of the first vertical structure is substantially cylindrical. Optionally, the dielectric pillar may have a first diameter at a first end and a second diameter at a second end. In various embodiments, the first and second diameters of the dielectric pillar may be configured to be the same or different.

In some embodiments, the dielectric pillar in the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. The first and second diameters of the dielectric pillar can be configured to be the same.

The integrated circuit may include a substantially cylindrical dielectric pillar, wherein the dielectric pillar has a first diameter at a first end and a second diameter at a second end. In some embodiments, the first diameter of the dielectric pillar is larger than the second diameter.

In some embodiments, the integrated circuit may include a substantially cylindrical channel post disposed around a dielectric post, which itself is disposed around a transfer gate electrode post. A ferroelectric post is disposed around the cylindrical channel post along the length of the channel post.

In some embodiments, the channel pillar formed around the dielectric pillar in the first vertical structure is substantially cylindrical in shape. The channel pillar may have a first diameter at a first end and a second diameter at a second, opposite end. The first and second diameters of the channel pillar may be the same, or the first diameter may be larger than the second diameter.

In some embodiments, the channel pillar in the first vertical structure can have a substantially cylindrical shape with a uniform diameter along its entire length. Specifically, the channel pillar has a first diameter at a first end and a second diameter at a second, opposite end, wherein the first and second diameters are the same. This uniform cylindrical channel pillar runs parallel to the ferroelectric pillar and the plurality of horizontal gate electrode layers in the vertical structure.

In some embodiments, the integrated circuit may include a substantially cylindrical channel pillar having a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter of the channel pillar is configured to be larger than the second diameter.

In some embodiments, the integrated circuit may include a substantially cylindrical ferroelectric post disposed around the channel post along its length. The cylindrical ferroelectric post may have a first diameter at a first end and a second diameter at a second end, wherein the diameters may be the same or the first diameter may be larger than the second diameter.

In some embodiments, the integrated circuit may include a substantially cylindrical ferroelectric pillar. The ferroelectric pillar may have a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter and the second diameter may be the same, or the first diameter may be larger than the second diameter.

In some embodiments, the ferroelectric post of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. Optionally, the first and second diameters of the ferroelectric post are configured to be the same.

In some embodiments, the integrated circuit may include a substantially cylindrical ferroelectric post having a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

In some embodiments, the integrated circuit further includes a dielectric terminal disposed around one end of the channel post, the dielectric terminal being adjacent to one end of the length of the channel post and adjacent to the ferroelectric post.

In some embodiments, the integrated circuit further includes a drain select layer disposed parallel to the plurality of horizontal gate electrode layers. The drain select layer is positioned adjacent to the dielectric terminal post surrounding one end of the channel pillar. The dielectric terminal post is adjacent to one end of the length of the channel pillar and adjacent to the ferroelectric post in the first vertical structure.

In some embodiments, the integrated circuit further includes a second dielectric terminal disposed around the other end of the channel pillar. The second dielectric terminal is adjacent to the other end of the length of the channel pillar and is also adjacent to the ferroelectric pillar.

In some embodiments, the integrated circuit further includes a source select layer disposed parallel to the plurality of horizontal gate electrode layers and adjacent to the second dielectric terminal pillar surrounding the other end of the channel pillar. The source select layer is positioned adjacent to the end of the length of the channel pillar and the ferroelectric pillar.

In some embodiments, the integrated circuit further includes a horizontal dielectric layer disposed within the channel pillar and adjacent to one end of the pass gate electrode pillar. Specifically, a dielectric layer can be horizontally incorporated into the cylindrical channel pillar structure and positioned adjacent to the end of the vertical pass gate electrode pillar. This dielectric isolation layer helps delimit the pass gate region within the 3D NAND string.

In addition to the first vertical structure, the integrated circuit may also include a second vertical structure. The first vertical structure includes a transfer gate electrode post, a dielectric post disposed around the transfer gate electrode post, a channel post disposed around the dielectric post, and a ferroelectric post disposed around the channel post along its length. Each of the plurality of horizontal gate electrode layers is disposed a predetermined distance apart from one another and adjacent to the ferroelectric post. The second vertical structure may be formed substantially identically to the first vertical structure, but disposed horizontally adjacent to the first vertical structure at a predetermined distance.

In addition to the first vertical structure described previously, the integrated circuit may include a second vertical structure. In some embodiments, this second vertical structure is formed to have substantially the same composition and dimensions as the first vertical structure. However, the second structure is positioned horizontally adjacent to the first vertical structure with a predetermined distance between them. Configuring two identical vertical structures in this parallel arrangement enables certain circuit configurations, such as forming a dual-port 3D NAND structure with paired vertical structures.

The integrated circuit may include first and second vertical structures, wherein the second vertical structure is formed substantially identically to the first vertical structure but is positioned adjacent to the first vertical column at a predetermined horizontal distance. In some embodiments, the first and second vertical structures are configured to form a dual-port 3D NAND structure.

In some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure may be formed of at least one conductive material selected from the group consisting of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as _TiSi2 , _CoSi2 , and NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

In some embodiments, the transfer gate electrode pillar of the first vertical structure is formed of at least one of the following materials: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as _TiSi2 , _CoSi2 , and NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers. The transfer gate electrode pillar can be constructed using one or more of these conductive materials.

In some embodiments, the ferroelectric pillar of the first vertical structure is formed of at least one of the following ferroelectric materials: calcium titanium; lead zirconate titanate (PZT); barium titanate (BaTiO ₃ ); strontium titanate (SrTiO ₃ ); bismuth ferrite (BiFeO ₃ ); potassium niobate (KNbO ₃ ); lithium niobate (LiNbO ₃ ); lithium niobate (LiTaO ₃ ); bismuth sodium titanate (Na _0.5 Bi _0.5 TiO ₃ ); bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ); bismuth zinc niobate (Bi(Zn _1/2 Ti _1/2 )O ₃ ); bismuth titanium oxide (BiLaTiO ₃ ); bismuth nickel titanium oxide (BiNiTiO ₃ ); lead magnesium nibrate-lead titanium oxide (PMN-PT); lead zirconia titanium oxide (PLZT); bismuth titanium oxide doped with neodymium (Bi _4-x Nd _x Ti ₃ O ₁₂ ); benzimidazole oxide; benzimidazole oxide (HfO ₂ ); doped benzimidazole oxide; zirconium-doped benzimidazole oxide (HfZrO ₂ ); tungsten-bronze structural materials; barium strontium niobate (BSN); lead barium niobate (PBN); potassium niobate (KTN); bismuth-layered ferroelectrics; bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ); strontium bismuth oxide (SBT); calcium bismuth niobate (CBN); organic ferroelectrics; polyvinylidene fluoride (PVDF); TrFE (trifluoroethylene); P(VDF-TrFE) copolymer; oliveris phase oxide; rare earth manganite; YMnO ₃ ; lead zirconium titanate modified with pyrolysis (PLZT); nickel manganese oxide (NiMnO ₃ ); relaxor ferroelectrics; lead magnesium nibrate (PMN); lead tantalum tantalum (PST); lead indium nibrate (PIN); multiferroic materials; titanate manganite (TbMnO ₃ ); titania (EuTiO ₃ ); SbSI (antimony sulfur iodide); GeTe (germanium telluride); SnTe (tin telluride); thin film ferroelectrics; PZT thin film; SBT thin film; HfO ₂ -based thin film; layered superlattice; or PbTiO ₃ /SrTiO ₃ .

In some embodiments, the channel pillar of the first vertical structure is formed of at least one of the following materials: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), indium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Si), crystalline germanium (c-Ge), gallium arsenide (GaAs), indium phosphide (InP), indium sulfide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH ₃ NH ₃ PbX ₃ , X=Cl, Br, I), cesium lead halide (CsPbX ₃ , X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobalt oxide, RP phase, inclusion complex, calcium-titanium oxide, and magnetic semiconductors. The choice of channel pillar material can affect properties such as electron mobility, switching speed, and power consumption.

In some embodiments, the dielectric pillars described herein are formed of at least one of: ferrite (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lumen oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO ₃ ), barium strontium titanate (BST), lead zirconium titanate (PZT), bismuth ferrite (BiFeO ₃ ), magnesium oxide (MgO), cerium oxide (CeO ₂ ), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd ₂ O ₃ ), daphnia (Dy ₂ O ₃ ), sulphur oxide (Sm ₂ O ₃ ), chalcanthus oxide (Eu ₂ O ₃ ), zirconium oxide (Tb ₄ O ₇ ), vanadium oxide (V ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), chromium oxide (Cr ₂ O ₃ ), iron oxide (Fe ₂ O ₃ ), molybdenum oxide (MoO ₃ ), tungsten oxide (WO ₃ ), ruthenium oxide (RuO ₂ ), rhodium oxide (Rh ₂ O ₃ ), palladium oxide (PdO), silver oxide (Ag ₂ O), cadmium oxide (CdO), tin oxide (SnO ₂ ), antimony oxide (Sb ₂ O ₃ ), tellurium oxide (TeO ₂ ), iridium oxide (IrO ₂ ), platinum oxide (PtO ₂ ), gold oxide (Au ₂ O ₃ ), beryllium oxide (BeO), magnesium aluminate (MgAl ₂ O ₄ ), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeO _x ), bismuth oxide (Bi ₂ O ₃ ), bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ), calcium-titanium oxide, layered oxide, or complex transition metal oxide.

In some embodiments, one of the plurality of horizontal gate electrode layers and the first vertical structure can be configured to form a plurality of transistors. These transistors can include the first transistor described herein. Specifically, the first vertical structure includes a transfer gate electrode pillar, a dielectric pillar disposed around the transfer gate electrode pillar, a channel pillar disposed around the dielectric pillar, and a ferroelectric pillar disposed around the channel pillar along its length. The plurality of horizontal gate electrode layers are each disposed a predetermined distance apart from one another and adjacent to the ferroelectric pillar along its length. One of the horizontal gate electrode layers and the first vertical structure together form the plurality of transistors, which may include a first transistor having the configuration described herein.

In some embodiments, the integrated circuit includes a first vertical structure. The vertical structure may include a vertical plug column. A source electrode column and a drain electrode column may be disposed adjacent to the vertical plug column. A channel column may be disposed around the vertical plug column, the source electrode column, and the drain electrode column. Additionally, a ferroelectric column may be disposed around the channel column. The integrated circuit may also include a plurality of horizontal gate electrode layers, each disposed a predetermined distance apart from another. Each of the horizontal gate electrode layers may be disposed adjacent to the ferroelectric column along its length.

In some embodiments, the integrated circuit further includes an oxide/nitride/oxide stack disposed adjacent to each of the plurality of horizontal gate electrode layers. The oxide/nitride/oxide stack can provide electrical isolation between the gate electrode layers while enabling the layers to control channel formation in the vertical channel pillar structure.

In some embodiments, the vertical plug of the integrated circuit has a first diameter at a first end and a second diameter at a second end. The first and second diameters can be the same or different.

In some embodiments, the vertical plug of the first vertical structure has a first diameter at a first end and a second diameter at a second end. The first and second diameters can be configured to be the same.

In some embodiments, the vertical plug in the first vertical structure has a first diameter on a first end and a second diameter on a second end, wherein the first diameter is larger than the second diameter.

In some embodiments, the vertical plug of the first vertical structure is configured as solid rather than hollow. Specifically, the vertical plug has a continuous material fill rather than a hollow conduit. Forming the vertical plug in a solid configuration can provide certain advantages to the overall integrated circuit structure related to ease of manufacturing or the integrity of adjacent components. However, other embodiments may utilize a hollow configuration for the vertical plug, depending on specific design considerations.

In some embodiments, the integrated circuit may have a hollow vertical plug. Specifically, the vertical plug disposed adjacent to the source electrode and the drain electrode in the first vertical structure may be hollow rather than solid. Forming a hollow vertical plug structure allows for additional design flexibility.

In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure can be formed substantially identically to the first vertical structure, but positioned adjacent to the first vertical structure at a predetermined horizontal distance. In certain embodiments, the first and second vertical structures can be configured to form a 3D AND structure or a 3D NOR structure.

In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure can be formed substantially identically to the first vertical structure, but positioned adjacent to the first vertical structure at a predetermined horizontal distance.

In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed substantially identically to the first vertical structure but is positioned adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D AND structure.

In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed substantially identically to the first vertical structure but is positioned adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D NOR structure.

In some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure may be formed of at least one material selected from the group consisting of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as _TiSi2 , _CoSi2 , and NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

In some embodiments, the source electrode pillar of the first vertical structure is formed of at least one of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, _TiSi2 , _CoSi2 , NiSi, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

In some embodiments, the integrated circuit further includes a gate electrode pillar formed from at least one of tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides such as _TiSi2 , CoSi2, _NiSi , graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

In some embodiments, the ferroelectric pillar of the first vertical structure is formed of at least one of the following: calcium titanium ore, lead zirconium titanate (PZT), barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), bismuth ferrite (BiFeO ₃ ), potassium niobate (KNbO ₃ ), lithium niobate (LiNbO ₃ ), lithium niobate (LiTaO ₃ ), sodium bismuth titanate (Na _0.5 Bi _0.5 TiO ₃ ), bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ), bismuth zinc niobate (Bi(Zn _1/2 Ti _1/2 )O ₃ ), bismuth linium titanate (BiLaTiO _{3 )} . ), nickel bismuth titanate (BiNiTiO ₃ ), lead magnesium nibrate-lead titanate (PMN-PT), lead zinc zirconate titanate (PLZT), neodymium-doped bismuth titanate (Bi _4-x Nd _x Ti ₃ O ₁₂ ), cobium-based oxides, cobium oxide (HfO ₂ ), doped cobium oxide, zirconium-doped cobium oxide (HfZrO ₂ ), tungsten-bronze structural materials, barium strontium nibrate (BSN), lead barium nibrate (PBN), potassium tantalum nibrate (KTN), bismuth layered ferroelectrics, bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ), strontium bismuth tantalum (SBT), calcium bismuth niobate (CBN), organic ferroelectrics, polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), P(VDF-TrFE) copolymer, oliveris phase oxide, rare earth hydromanganite, YMnO ₃ , lead zirconium titanate modified with zinc (PLZT), nickel manganese oxide (NiMnO ₃ ), relaxor ferroelectrics, lead magnesium niobate (PMN), lead niobium titanate (PST), lead indium niobate (PIN), multiferroic materials, zinc manganite (TbMnO ₃ ), titania (EuTiO ₃ ), SbSI (antimony sulfur iodide), GeTe (germanium telluride), SnTe (tin telluride), thin film ferroelectrics, PZT thin films, SBT thin films and _HfO2 -based thin films, layered superlattices and _PbTiO3 / _SrTiO3 .

In some embodiments, the channel pillar of the first vertical structure is formed of at least one of: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), indium indium oxide (HIO), and cadmium oxide (CdO), polycrystalline silicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Si), crystalline germanium (c-Ge), gallium arsenide (GaAs), indium phosphide (InP), indium sulfide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polyphenylene vinylene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH ₃ NH ₃ PbX ₃ , X=Cl, Br, I), cesium lead halide (CsPbX ₃ , X=Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobalt, RP phase, inclusion compound, calcium titanium oxide, or magnetic semiconductor.

In some embodiments, the vertical plug of the first vertical structure is formed of at least one of the following: ferrite (HfO ₂ ), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lumen oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO ₃ ), barium strontium titanate (BST), lead zirconium titanate (PZT), bismuth ferrite (BiFeO ₃ ), magnesium oxide (MgO), calcite oxide (CeO ₂ ), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd ₂ O ₃ ), daphnia (Dy ₂ O ₃ ), sulphur oxide (Sm ₂ O ₃ ), chalcanthus oxide (Eu ₂ O ₃ ), zirconium oxide (Tb ₄ O ₇ ), vanadium oxide (V ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), chromium oxide (Cr ₂ O ₃ ), iron oxide (Fe ₂ O ₃ ), molybdenum oxide (MoO ₃ ), tungsten oxide (WO ₃ ), ruthenium oxide (RuO ₂ ), rhodium oxide (Rh ₂ O ₃ ), palladium oxide (PdO), silver oxide (Ag ₂ O), cadmium oxide (CdO), tin oxide (SnO ₂ ), antimony oxide (Sb ₂ O ₃ ), tellurium oxide (TeO ₂ ), iridium oxide (IrO ₂ ), platinum oxide (PtO ₂ ), gold oxide (Au ₂ O ₃ ), beryllium oxide (BeO), magnesium aluminate (MgAl ₂ O ₄ ), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeO _x ), bismuth oxide (Bi ₂ O ₃ ), bismuth titanium oxide (Bi ₄ Ti ₃ O ₁₂ ), calcium-titanium oxide, layered oxide, or complex transition metal oxide.

In some embodiments, the integrated circuit can include a plurality of transistors formed from one of the horizontal gate electrode layers and a first vertical structure according to any of the transistors described herein. The first vertical structure can include components such as a vertical plug pillar, source and drain electrode pillars, a channel pillar, and a ferroelectric pillar. The horizontal gate electrode layers can be positioned a predetermined distance apart from each other and adjacent to the ferroelectric pillar. Configuring a horizontal gate electrode layer and the first vertical structure in this manner allows for the formation of transistors having the properties described herein.

FIG1 shows a block diagram of an integrated circuit 100 that can be packaged as a bondable chiplet (e.g., a bondable face-to-face chiplet) according to one embodiment of the present invention. Integrated circuit (IC) 100 includes a module group 106 consisting of modules 108, 110, 112, and 114. IC 100 also has a common write port 102 that is configured to be written to module group 106 using a write peripheral 104. Additionally, it includes read peripherals 116, 118, 120, and 122 and read ports 124, 126, 128, and 130 that are configured to read from modules 108, 110, 112, and 114.

Write port 102 can be configured to provide a single write address space for the entire module group 106, with each of modules 108, 110, 112, 114 having a dedicated read port 124, 126, 128, 130, respectively. Integrated circuit 100 can be packaged as part of a die that is configured to be electrically connected to another integrated circuit device (e.g., another die or IC package, with or without electrical contacts, bumps, etc.). The die can be electrically connected to another device (including, for example, by bonding, soldering, wafer-to-wafer bonding, face-to-face die bonding, die-to-wafer bonding, die-to-interposer bonding) and/or can be connected together using an interposer or other interfacing technology. Zero, one, or more interposers may be used, or other interfacing technologies common to heterogeneous 3D system-level packaging solutions may be utilized to electrically connect a die to another device.

Each read port (124, 126, 128, 130) in the chiplet can have electrical contacts on one side of the chiplet or on multiple sides of the chiplet. Read ports 124, 126, 128, 130 can use multi-loop pipelined circuitry. When bonded to another device (e.g., a wafer, chiplet, chip, SOC, package, FPGA, etc.), the electrical contacts can be aligned in a manner that provides dedicated access to a specific module of modules 108, 110, 112, 114. For example, a processing/computing element can have exclusive access to module 108 via read port 124 (which can contain neural network weights in a register file). Similarly, a different processing/computing element can have exclusive read access to module 110 via read port 126 (which contains a different register file). In this particular embodiment, this configuration of electrical contacts ensures that each computing/processing element has the dedicated access required to efficiently perform its specific computation, thereby providing a compact, modular, and scalable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, 114. Without dedicated access, different processing elements may have to queue for use of the same resources, which would slow down overall processing speed. By providing dedicated access, in this particular embodiment, the proposed chiplet ensures that each processing element can operate at its maximum capacity without interference from other computing elements.

Write peripheral 104 is a peripheral circuitry responsible for processing and writing data to the memory cells found within modules 108, 110, 112, and 114. Write peripheral 104 may include dedicated contacts that allow a chip to be electrically connected (e.g., bonded) to a dielet of the integrated circuit, making write port 102 accessible via a shared write logic system that utilizes a shift register-based, differential voltage design, preferably a high voltage design, with shared write address and data components. This shared write logic system is designed to be accessed via a bonded chip, another bonded dielet, and/or other circuitry within the same package as integrated circuit 100. A shift register allows the system to shift data through a series of stages, with each subsequent stage receiving data from the previous stage. By utilizing a shift register, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location in the chiplet where data is written.

In another embodiment, an interlock 132 can disable read ports 124, 126, 128, and 130 while data is being written to module group 106 via write port 102. Similarly, interlock 132 can disable write port 102 while a read operation is being performed on read ports 124, 126, 128, and 130. The written data can then be accessed simultaneously by all processing elements that need to read data via each of read ports 124, 126, 128, and 130. This ensures that all processing elements have their most current data available, regardless of other reads being performed simultaneously by other processing elements.

The write peripherals 104 circuitry includes a write driver. This unit receives the data to be written and converts it into suitable signals that can change the state of the memory cell. Depending on the type of memory technology used, these signals may involve voltage levels, current pulses, or other types of energy. Due to the specific voltage requirements of small chips, the shared write logic system can be high voltage. The write driver must provide enough power to reliably change the state of the memory cell, but it must also operate within suitable parameters to avoid causing damage or unnecessary wear.

The write peripheral 104 circuitry may also include a data buffer or write buffer. This component temporarily stores data to be written to allow write operations to proceed at an optimal pace. By balancing the speed of incoming data with the speed at which the memory can be written, the write buffer helps prevent data loss and optimize system performance.

In some embodiments, the write peripheral 104 may also include a write control unit that orchestrates the sequence of operations in the write process. It generates control signals to activate the write driver at the appropriate time, controls the flow of data from the write buffer, and coordinates the timing of write operations. By synchronizing these various activities, the write control unit ensures efficient and reliable write operations.

The write peripheral device 104 may also include data encoding mechanisms to improve reliability and data integrity. For example, before writing data to the memory, these mechanisms encode the data in a way that allows potential errors to be detected and, in some cases, corrected when the data is later read. This can be helpful in systems where data integrity is a high priority, such as in servers or scientific research equipment.

The write peripheral device 104 may also include a timing unit that acts as the heartbeat of the system, providing a clock signal that synchronizes the operation of various components of the system. In some systems, this may include components such as an oscillator, a clock generator, or a phase-locked loop. The timing unit ensures that all operations occur at the appropriate time relative to each other.

IC 100 may be implemented as a face-to-face bonded die, with modules 108, 110, 112, and 114 formed from a non-volatile memory. In some specific embodiments, IC 100 may also include a dynamic allocation circuitry for allocating memory blocks to module group 106 based on usage of module group 106 (e.g., each module 108 may include dynamic allocation circuitry for dynamically allocating a range of read locations to a respective processing element).

IC 100 has a plurality of clocks, and each of the plurality of clocks is fed to a respective one of the plurality of modules so that each respective module has decoupled timing relative to the other modules. Module group 106 can be configured in any topology known to those skilled in the art. The bit cell density can be up to 10 times denser than the embedded SRAM cells in module group 106.

IC 100 may be formed on a chiplet comprising a first side and a second side, with the second side configured for bonding to a second semiconductor device. IC 100 may include high voltage write logic adjacent to the first side of the chiplet. A decoder circuitry, a driver circuitry, and a register circuitry may be formed on a silicon substrate portion of the chiplet, with module group 106 formed on a second layer portion of the chiplet. The second semiconductor device may include a plurality of processing elements. Each processing element includes a respective interface for communicating with a respective one of the plurality of modules on module group 106 when the second semiconductor device is bonded to the chiplet.

Silicon substrates typically serve as the initial stage of IC fabrication, focusing on the creation of active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are used to create the complex structures of transistors. These processes operate on a small scale. The application of photolithography, etching, and implantation techniques enables the precise definition of transistor structures. The importance of the silicon substrate lies in its ability to establish the basic building blocks required for signal processing, amplification, and control within the IC. This layer is sometimes referred to as the front-end of the line (FEOL).

Next in the process, a second layer can be added, which typically plays the role of interconnect fabrication to facilitate electrical connections between the various IC components. This stage typically focuses on the creation of passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The second layer processes typically differ in precision and scale from those used on silicon substrates. Interconnects are formed by depositing and patterning metal layers (usually aluminum or copper) to build the wiring network. Dielectric layers (such as silicon dioxide or low-k dielectrics) are introduced to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to create the necessary interconnects to enable the routing and distribution of electrical signals throughout the IC. However, as described herein, circuitry may be utilized within this second level (sometimes referred to as the back end of the line ("BEOL")).

Alternative embodiments of IC 100 can be implemented as a stacked die, a monolithic design, TSVs, or through-silicon vias. In a stacked die design, several dies can be stacked on top of each other, with each die performing different functions, such as memory and processing. The stacked dies can communicate via wire bonds, microbumps, or bumpless bonding. In a monolithic design, the various functions and modules of IC 100 can be integrated onto a single die, creating a more compact and power-efficient design.

In addition, IC 100 may include one or more interlocks 132 for managing conflicts when reading and writing data. Module group 106 may be formed from various non-volatile or semi-volatile (e.g., very long refresh cycle) memory technologies such as static random access memory (SRAM), ferroelectric field effect transistor (FeFET), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin transfer torque (STT) memory, charge trap, floating gate memory, and/or Schottky diode.

Module group 106 may utilize a static random access memory (SRAM) topology. SRAM topologies employ a cross-coupled flip-flop structure (e.g., latched flip-flops) to ensure that stored data remains intact as long as power is supplied. Therefore, in certain embodiments, module group 106 may utilize heterogeneous memory types, including volatile and non-volatile memory types.

Module group 106 can utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein has a matrix of memory cells, each consisting of a floating-gate transistor or a charge-trapping device. Module group 106 can also utilize wear-leveling techniques to extend the life of the memory cells.

Module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. FeRAM utilizes a ferroelectric material capable of maintaining a polarization state. In a specific embodiment, such a memory topology may utilize a FeFET to maintain state information and program the ferroelectric material. These ferroelectric materials can be used to maintain state information and function as a memory bit cell.

Module group 106 may utilize a phase change memory (PCM) topology, which is a non-volatile memory technology that uses reversible material phase changes to store data. A PCM topology may include any phase change material, such as a chalcogenide alloy or chalcogenide glass, housed in a memory cell.

Module group 106 may utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the phenomenon of resistive switching. ReRAM topology utilizes a thin film material that exhibits a reversible resistance change when an electrical stimulus is applied.

Module group 106 may utilize a spin-orbit moment (SOT) magnetic random access memory (MRAM) topology. SOT-MRAM is a type of non-volatile memory that uses spin-orbit moment to switch the magnetic state of a storage element. The SOT-MRAM topology may incorporate a magnetic tunneling junction (MTJ) structure and utilize spin-orbit coupling to write and read data. The MTJ may have a dielectric layer between a magnetic fixed layer and a magnetic free layer. Writing can be accomplished by injecting an in-plane current into an adjacent SOT layer to switch the magnetization of the free magnetic layer. Reading can be accomplished by passing a current into the MTJ. In some specific embodiments, SOT-MRAM can optimize spin-orbit materials by using a current-driven switching scheme while minimizing write energy consumption.

Module group 106 may utilize a spin-transfer torque (STT) magnetic random access memory (MRAM) topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of a storage element. STT-MRAM topology may use a magnetic tunneling junction (MTJ) structure, in which the magnetization orientation determines the stored data. Alternatively, the orientation of a magnetic layer in a MTJ or spin valve can be altered using, for example, a spin-polarized current.

IC 100 may include a single write peripheral 104 with a dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral (not shown in FIG1 ) utilizing a common clock. Additionally, module group 106 may be organized into separate partitions, each containing a dedicated read peripheral 116, 118, 120, 122 with an independent clock.

Another possible embodiment of IC 100 includes an interface (e.g., the same, different, higher, or lower voltage) for implementing data transfer outside the package of IC 100. In other specific embodiments, IC 100 may also include an integrated microcontroller unit (MCU) or a digital signal processor (DSP) for processing data within the IC.

FIG2 shows a perspective view of an assembly 200 of the integrated circuit 212 of FIG1 implemented on a chiplet 230 bonded to a second device 226 according to an embodiment of the present invention. The integrated circuit 212 is the circuit system within the chiplet 230. The second device 226 can be a chiplet, a semiconductor wafer, a semiconductor package, a packaged circuit system, etc. For example, the second device 226 can be an AI accelerator so that each processing unit can read and access one module (or a predetermined group) of the module group 236. In another embodiment, the second device 226 can be a network controller in which an offload circuit is present to read data from each of the modules to process incoming/outgoing packets, etc. Assembly 200 includes a module group 236 having a plurality of modules, including a first module 232 and a second module 234. FIG. 2 shows several modules, however, for clarity, only modules 232 and 234 are labeled. Integrated circuit 212 further includes a shared write port 222. Shared write port 222 interfaces to write peripheral device 202.

Although the second device 226 can use the common write port 222 to write data to any module in the module group 236 via an address and data bus with a clock and an enable signal, other methods of writing data are contemplated. For example, a serial connection, a parallel connection, various buses or ports such as a DDR (double data rate) interface, an SRAM (static random access memory) interface, a NAND flash memory interface, a NOR flash memory interface, an HBM (high bandwidth memory) interface, a GDDR (graphics double data rate) interface, an NVMe (non-volatile memory express) interface, SPI, IC2, etc. can be used. Each of the modules has a read port including a read address 218 (which sends an address to a module 234) and read data 220 (which is data read from module 232).

Module group 236 is formed on a chiplet 230 having two sides including a surface 228 that can be bonded to and complementary to a second device 226. Chiplet 230 can be formed by forming circuitry on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers can be reversed and/or other layers can be added or removed. Read address 218 and read data 220 are used to read module 232.

Although the second device 226 can read data from the module 232 using an address and data bus with a clock and an enable signal, other methods of reading data are contemplated. For example, a serial connection, a parallel connection, various buses or ports, such as a DDR (double data rate) interface, an SRAM (static random access memory) interface, a NAND flash memory interface, a NOR flash memory interface, an HBM (high bandwidth memory) interface, a GDDR (graphics double data rate) interface, an NVMe (non-volatile memory express) interface, SPI, IC2, etc. can be used.

All read ports (e.g., 218 and 222) are configured to be inactive when a write operation is applied to the shared write port 222. The read ports can also be configured to process reads simultaneously with each other. The shared write port 222 is configured to write to an address space, wherein the shared write port 222 is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion 234 of the address space. Each module of the plurality of modules 236 includes an independent read port for simultaneously reading via a respective independent read port of any of the plurality of modules.

Each read port of a respective module may include contacts for interfacing with circuitry found within second device 226 via metal contacts. Thus, metal contacts may be present on top layer 208 that are configured to interface with metal contacts on surface 228 of chiplet 230, such that the metal contacts allow for a read volume that is coextensive with a read volume of one of modules 236. The read volumes of module group 236 may all be coextensive with one another (as described with reference to FIG3 and FIG4 ).

In one embodiment, the read peripherals of the first module 232 are implemented on a silicon substrate (sometimes referred to as a front-end of the line). The second layer 206 (sometimes referred to as the back-end of the line) can then be constructed later in the process on top of the silicon substrate 204 (and any circuitry) and can contain the respective memory bit cells. In an alternative embodiment, the read peripherals of the first module 232 are implemented in the second layer 206 and positioned between the module group 236 and the surface 228 of the chiplet 230.

Module group 236 can be configured to process write commands only during reset. The write command can be a "slow write" command. That is, module group 236 can have a very slow write speed relative to its read speed. The write logic can be frozen (or disabled) when module group 236 is used to read data. In some specific embodiments, integrated circuit 212 provides functionality for allocating memory blocks to module group 236 based on the use of module group 236. In other embodiments, the memory address is fixed along with the allocation. Integrated circuit 212 can be implemented as a face-to-face bonded chiplet 230. The face-to-face bonding can be a bumpless wafer bond.

Module group 236 may have a single write peripheral 202. In other embodiments, each module in module group 236 may have a dedicated write peripheral that utilizes a common clock. In other embodiments, module group 236 may also be organized into separate partitions, each containing a partition with a dedicated read peripheral, where each dedicated read peripheral has an independent clock. A partition may be one, two, or more modules in module group 236.

The overall architecture of the write peripheral device 202 circuit system can include a series of different components, including a write driver, an address decoder, a sense amplifier, a data input latch, a data bus, etc. and/or a combination thereof. The write driver or write buffer can be responsible for transferring data to the memory cell. They can enhance the input signal to reach a level suitable for the memory cell. The address decoder can be used to interpret the memory address fed as an input when data needs to be written. By activating a specific row and column of the memory array linked to the address, they can be used to select the target memory cell. Sense amplifiers are used to identify and amplify signals from the memory bank during read operations and are also involved in resetting the memory bank after data is written during write operations. Write operations are initiated by a write enable signal. When a write command is issued, this signal triggers the write driver and decoder to begin the write process. A data input latch serves as a temporary storage unit to hold data to be written to the memory bank until the write operation is performed. A data bus with a transmission line facilitates the movement of data from the data input latch to the memory bank.

A write operation to the module group can be performed through a priority arbitration circuit that facilitates access to the modules in a predetermined order, and the shared write port 222 can be configured to write to a virtual address space mapped to a physical memory space. The integrated circuit 212 can include high-voltage write logic for writing to the peripheral device 202, and the second semiconductor device 226 can include a plurality of processing elements, each of which includes a respective interface for communicating with a respective module in the module group 236. In addition, the chiplet 230 can include an interface to the shared write port 222 on the second side, thereby interfacing with a complementary interface on the second semiconductor device 226.

The integrated circuit 212 may also include a power gating circuit system that selectively powers down one of the modules 236 when not in use. Additionally, the integrated circuit 212 may connect a write peripheral device 202 of the module group 236 to a dedicated I/O pad to enable data transfer outside the package of the integrated circuit.

Integrated circuit 212 may utilize multiple modules 234 grouped together in a module group. In certain embodiments, these modules may be synchronized with one another. In some cases, all modules are synchronized, while in other instances, only specific modules are synchronized. For example, when reading data from one of the modules in module group 236, circuitry on a second device 226 may need to synchronize with a specific module.

To synchronize the modules, integrated circuit 212 may utilize various timing techniques. In some cases, multiple clocks may be fed to each module in module group 236, thereby allowing each module to have decoupled timing relative to the other modules in the group. This decoupling ensures that any delay in one module does not affect the functionality of other modules. It is important to note that the clocks used may or may not be synchronized. In some cases, a common clock may be used to synchronize the modules. In other embodiments, one or more clock signals may be provided by second device 226.

In alternative embodiments, other synchronization techniques can be used, such as phase comparison of clock signals or a phase-locked loop (PLL) synchronization method. Another embodiment for synchronizing modules within an IC can use delay-locked loop (DLL) synchronization. In this method, a delay element is added to the clock signal path, and the output and input clock signals are compared. A feedback loop adjusts the delay element until the DLL output matches the input, resulting in synchronized clock signals.

In another embodiment, the integrated circuit 212 may use a combination of different synchronization techniques to achieve synchronization between modules. For example, some modules may use PLL synchronization, while other modules may use clock delay lines or DLL synchronization, depending on their specific requirements. Furthermore, the integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in the event that one method fails. For example, the integrated circuit 212 may use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the other method can still maintain synchronization.

FIG3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of FIG1 according to an embodiment of the present invention. The memory address space includes a write address space 316 and read data address spaces 310, 312, 314.

The write address space 316 consists of various cells in which data (such as weights and/or instructions) can be stored. These cells refer to memory addresses. The module group 302 includes a plurality of memory modules 304, 306, 308. The write address space 316 can be distributed among the memory modules 304, 306, 308 so that the write address space 316 spans from 0 to N*M-1. As shown in Figure 3, the module group 302 has N memory modules 304, 306, 308, where N is a positive integer and each module has a memory size of M. The total number of unique write memory addresses in the write address space will be N*M, which can be referenced by an integer from 0 to N*M-1.

Starting at 0, the memory addresses written into address space 316 are sorted sequentially up to N*M-1. In other words, the first address is 0 and the last address is N*M-1 to cover a total of N*M addresses. This sorting can be linear (each address increases by 1) or some other specified pattern, depending on the implementation.

Write memory addressing can be implemented in various ways based on the system architecture. One method used in one particular embodiment uses base and limit registers. The base register holds the minimum legal physical write memory address, and the limit register specifies the size of the range. Thus, to generate a logical address, the base address is added to the relative address. In other embodiments, a memory addressing scheme can be used in which the base address used is set to 0. Those skilled in the relevant art will understand additional write addressing techniques.

Each memory module may have a unique set of write memory addresses for any device writing to module group 302, such that all memory addresses within module group 302 are unique relative to the written data, e.g., starting at 0 for the first module and ending at N*M-1 for the last module. In some embodiments, this allocation may depend on the memory management system of the device writing data to modules 304, 306, 308, which may range from a simple fixed partitioning scheme to a more complex dynamic partitioning model.

For example, in a direct linear model where each module (304, 306, or 308) has an equal size of M addresses, the first module 304 will have write addresses 0 to M-1, the second module will have write addresses M to 2M-1, the third module will have write addresses 2M to 3*M-1, etc. Thus, the Nth module 308 will have write addresses from (N-1)*M to N*M-1.

It is anticipated that persons skilled in the art may use other implementations of write memory addresses from 0 to N*M-1, depending on various factors such as the hardware architecture, operating system, memory management scheme, and the nature of the programs running on the system.

Module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 can have overlapping address spaces, can have consecutive address spaces, or can have coextensive address spaces. Read address spaces 310, 312, and 314 can be relatively independent of each other. The system includes three independent read address spaces, labeled read address spaces 310, 312, and 314. Each of these read address spaces is distinct from the others, meaning that reads can be performed in each space without affecting the others.

The read address spaces 310, 312, 314 can be defined as contiguous blocks of memory addresses, each with its own starting address and ending address. In the module group 302, each read address space 310, 312, 314 can have an address range corresponding to a value from 0 to M-1, where M is a maximum value determined by the size of the modules 304, 306, 308 used.

In one embodiment, a processing unit is allowed to interface with each read address space 310, 312, 314, and read simultaneously as described herein. The independence of the read address spaces 310, 312, 314 ensures that each processing unit can access the data it needs without causing any interference or conflicts with other processing units.

FIG4 shows a block diagram 400 illustrating a memory address space having a signal interface with the integrated circuit of FIG1 according to an embodiment of the present invention. The signals used in FIG4 can be used with any of the embodiments described herein. However, one of ordinary skill in the relevant art will appreciate that different signaling schemes can be used.

Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. Write peripheral 411 includes a write address bus with addresses of data to be written, a write data bus with data, and a write clock that causes a write to occur (e.g., on a leading or trailing edge of a clock signal, etc.). Writing occurs only when the write enable signal indicates that a write should occur. Any logic can be used, for example, a high voltage can correspond to a 1 and a low voltage can correspond to a 0, or vice versa. In some embodiments, write peripheral 411 can be on chiplet 230, and in other embodiments, write peripheral 411 can be on second device 226.

Module group 402 includes modules 404, 406, and 408, each of which has a respective read peripheral device 410, 412, and 414. Each of read peripheral devices 410, 412, and 414 has a read address bus for sending a read address, a read data bus for receiving data, a read clock for controlling the timing of output of digital data, and an output enable (which is a prerequisite for outputting data). Any logic can be used; for example, a high voltage can correspond to a 1 and a low voltage can correspond to a 0, or vice versa. In alternative embodiments, multi-bit or analog data storage can be used. In some embodiments, one or more of the read peripheral devices 410 , 412 , 414 may be on the dielet 230 , and in other embodiments, one or more of the read peripheral devices 410 , 412 , 414 is on the second device 226 .

FIG5 shows a diagram of an integrated circuit 500 that may be part of a semiconductor device, such as a chiplet, according to an embodiment of the present invention. Integrated circuit 500 may be disposed on a semiconductor device, such as a chiplet, having a silicon substrate 506 and a second layer portion 508. Within integrated circuit 500, there may be an array section forming module 502, wherein a three-dimensional row array of memory bit cells 522 has the necessary components for storing memory in non-volatile memory, semi-volatile memory, or one of the memory formats described herein.

Integrated circuit 500 may include a module group having a plurality of modules including a first module and a second module (even though only a single module 502 is shown). Memory bit cells 522 are written to via shared write ports 512, 516, which include both a write address bus 512 and a write data bus 516. These buses run through second layer 508 and may be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement the electrical contacts on surface 518, allowing it to be electrically coupled to the write address and data buses. Memory bit cells 522 can be read via read ports 524, 526, which include a read address bus 524 and a read data bus 526. These two buses can also run through the second layer 508 to a second semiconductor device coupled to the surface 518, which also has complementary contacts to allow it to be electrically coupled to the read address and data buses.

Various memory technologies may be used for the memory bit grid 522, such as a vertically connected fabric structure formed by non-volatile memory cells arranged in a three-dimensional row array 522. The memory bit grid 522 may utilize one or more of a crosspoint, 3D NAND, 3D NOR, 3D AND, and/or stacked planar layers.

In some embodiments, integrated circuit 500 is electrically connected to a second semiconductor device (not shown in FIG. 5 ) that includes another integrated circuit (which may be a system-on-a-chip or a field programmable gate array). In some embodiments, memory bit cell 522 may be formed from various non-volatile memory types, such as FeFET, FeRAM, ReRAM, SOT, or STT. Additionally, alternatively, or optionally, the memory bit cell may be formed from a non-volatile memory cell having a 2-terminal device, a 3-terminal device, or a 4-terminal device.

For example, the memory cell 522 may be formed from a ferroelectric material (such as a ferroelectric tunneling junction, a diode, a capacitor, a single-gate transistor, or a double-gate transistor). Alternatively, the memory cell 522 may be formed from a memristive material (such as at least one ReRAM) or a magnetic material (such as at least one spin-orbit torque device or at least one spin-transfer torque device). Furthermore, the non-volatile memory cell 522 may also be formed from a phase-change material or an antiferroelectric material.

In some alternative embodiments, non-volatile memory cells 522 may be formed from other types of materials, such as phase change materials, antiferroelectric materials, or multi-bit PCM materials. Non-volatile cells may be formed using different structures, such as resistive random access memory (RRAM) technology, magnetic random access memory (MRAM) technology, or ferroelectric random access memory (FRAM) technology.

Furthermore, in some embodiments, 3D NAND technology can be used to form the memory cell bit grid 522. For example, the memory cell bit grid 522 can be formed by stacking memory layers, where each layer includes multiple memory cells that can be accessed using shared bit lines. In this case, the read ports 524 and 526 can be coupled to the bit lines, and the write ports 512 and 516 can be coupled to the word lines that control access to each layer.

In another embodiment, the 3D interconnect structure can be constructed using stacked layers of NAND gates, NOR gates, or AND gates. In some cases, different types of logic gates can be combined to optimize the functionality of the structure. Additionally, the 3D interconnect structure can be formed using through-silicon via (TSV) technology, which allows different layers of the structure to be vertically interconnected.

Additionally, the non-volatile memory cell may comprise a 2-terminal device, such as a capacitive or memristive device with or without an additional selector device, such as a series diode; a 3-terminal device, such as a floating gate transistor or a transistor with an access gate; or a 4-terminal device, such as a transistor with two access gates. The type and configuration of the non-volatile memory cell 522 may depend on the specific application requirements, including circuit speed, power consumption, and reliability. The memory cell may comprise or be a single ferroelectric transistor or a 6T SRAM cell. A memory cell can be a combination of many different devices, including but not limited to one or more of a transistor, a resistor, a capacitor, etc.

In some embodiments of the present invention, a ferroelectric material may be used to form the non-volatile memory cell 522. The ferroelectric material may be implemented as a variety of devices, including but not limited to a thin film device, such as a ferroelectric tunneling junction, a capacitor, a single-gate transistor, or a double-gate transistor.

In another embodiment, the non-volatile memory cell 522 may be formed of a memory material such as a metal oxide memory (MOM), conductive bridge RAM (CBRAM), or value change memory (VCM), each of which offers different benefits with respect to power consumption, speed, endurance, etc.

Furthermore, in some embodiments, the non-volatile memory cell 522 may be formed of a magnetic material, such as a spin-orbit torque (SOT) device, a spin transfer torque (STT) device, or a perpendicular magnetic tunneling junction (p-MTJ).

In one embodiment, a module group may include multiple modules, each of which can be accessed by a dedicated read peripheral 520 via dedicated read ports 524, 526, while sharing the same write ports 512, 516 and a common write peripheral 510. The shared write ports 512, 516 can be configured to selectively write to one or more of the multiple modules within the module group that includes the memory cell 522. The modules can be of the same or different sizes, and different module sizes can be configured to optimize memory array utilization under different operating conditions, etc.

Furthermore, the integrated circuit 500 may be formed using various processes and technologies, including but not limited to a CMOS or bipolar CMOS-DMOS (BCD) process, a silicon-on-insulator (SOI) process, a FinFET process, a silicon germanium (SiGe) process, a gallium arsenide (GaAs) process, etc.

In some embodiments, a three-dimensional array of rows of memory bit cells 522 is formed and configured as a micro-bank. Additionally or alternatively, each micro-bank will have a dedicated read peripheral 520 and a write peripheral 510 (which is also a dedicated write peripheral rather than a shared write peripheral). That is, in some embodiments, each micro-bank includes a dedicated write connection and a dedicated read connection, and a predetermined number of micro-banks (e.g., two or four) may have a dedicated write connection and a dedicated read connection, with or without dedicated peripherals.

FIG6 shows a perspective view of an assembly 600 having the integrated circuit of FIG1 implemented on a semiconductor device (such as chiplet 230) electrically connected to a system-on-a-chip (“SOC”) 610 according to an embodiment of the present invention. In this embodiment, the semiconductor device is chiplet 230 electrically connected to the system-on-a-chip (“SOC”) 610.

Referring to FIG. 6 , SOC 610 includes a silicon substrate 602 on which a plurality of processing elements (including a processing element 606) are formed. The processing elements can communicate with each other via a network-on-chip (NOC) 604, a communication fabric that directs data transfer between the processing elements. This communication fabric can take various forms, including buses, switches, and NOCs. NOC 604 in SOC 610 directs data traffic between various nodes (e.g., processing element 606) and links (which provide communication paths between the nodes).

The plurality of processing elements includes processing element 606, which may be any suitable type of processor capable of executing instructions, including a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), or an application-specific integrated circuit (ASIC).

Additionally, SOC 610 may include various modules, such as module 232, grouped together to provide memory functionality for assembly 600 as described herein. Modules in module group 236 may be coupled to a respective processing element, providing readable memory thereto. In some embodiments, coupling between a module (e.g., module 232) and a processing element (e.g., 606) may be achieved through interconnects on silicon substrate 602.

After the circuitry is formed on the silicon substrate 602, a second layer 608 can be placed on top of the substrate. The second layer 608 can be any suitable material, such as an insulating material, a metal, a dielectric, or an interconnect layer, and can be bonded to the chiplet 230. Bonding can be accomplished using any suitable technique, including, but not limited to, adhesives, soldering, or welding.

Generally speaking, assembly 600 provides a means of integrating chiplet 230 (which may include the integrated circuit of FIG. 1 ) with SOC 610. Integrating chiplet 230 offers various advantages, such as enhanced functionality, higher performance, and lower power consumption. Furthermore, the integration of chiplet 230 and SOC 610 can be achieved in a variety of ways, depending on the specific application and design goals of the system.

Depending on the specific requirements of the system, assembly 600 may incorporate various variations and modifications. For example, the number, type, and configuration of processing elements formed on silicon substrate 602 may vary. Similarly, the number, type, and function of modules in module group 236 may vary.

Furthermore, the second layer 608 can be modified to include additional functionality. For example, the second layer 608 can include passive components such as resistors, capacitors, and inductors, or active components such as transistors or diodes. Incorporating these components into the second layer 608 can further enhance the functionality and performance of the system.

In another variation, assembly 600 may incorporate a heterogeneous integration approach, where chiplets 230 are fabricated using a different technology than that used for SOC 610. This approach allows for optimal use of different fabrication technologies for different parts of the system, resulting in improved performance and reduced power consumption.

FIG7 shows a perspective view of an assembly 700 having a semiconductor device 707 including an array of processing elements 706 (on a grid of processing elements 706a,a through 706n,n, where the first subscript is a row and the second subscript is a series) and a second semiconductor device 709 having an array of micro-banks 708. The micro-bank array 708 is arranged on a grid of micro-banks 708a,a through 708n,n, where the first subscript is a row and the second subscript is a series. These subscripts can be arranged in a row so that each subscript of a processing element 706 corresponds to a respective subscript of a micro-bank 708. Micro-banks 708 are modules of the type described herein, in which the micro-banks are positioned vertically, for example, above each processing element 706. Semiconductor device 707 may be a chiplet. Furthermore, semiconductor device 709 may also be a chiplet. Chips 707 and 709 may be bonded together. Different layers 710 (e.g., layers 710a through 710d) may be assigned to separate AI models (e.g., parameters in a neural network, such as a CNN or transformer model).

Assembly 700 is the overall structure that houses the various components shown in Figure 7. It provides mechanical support and integration to the other components to allow the components to function as a unified system.

Assembly 700 includes two semiconductor devices: semiconductor device 707 and semiconductor device 709. Semiconductor device 707 includes an array of processing elements labeled 706a,a through 706n,n. Similarly, semiconductor device 709 includes an array of micro-storage banks labeled 708a,a through 708n,n.

Subscripts a,a through n,n indicate that processing elements 706 and micro-storage banks 708 are arranged in a grid pattern, with the first subscript referring to rows and the second subscript referring to columns. This grid arrangement allows each processing element 706 to have a corresponding micro-storage bank 708 positioned vertically above it. For example, processing element 706a,a has micro-storage bank 708a,a above it, processing element 706b,b has micro-storage bank 708b,b above it, and so on. This grid alignment allows for tight integration between processing and storage components.

In some embodiments, semiconductor devices 707 and 709 are integrated into a unified assembly 700 using packaging technology, possibly as separate small chips. The small chip form factor allows for greater flexibility and customization when assembling the system. This configuration enables each processing element 706 to access its own micro-storage 708 located above it to retrieve relevant data, such as weights for a neural network or AI model. This provides the high-bandwidth and low-latency data access required for efficient processing.

Input data enters the system via input DRAM memory 702. This data flows into processing elements 706 where it is locally operated on using weights or parameters from vertically integrated micro-storage 708. The results of the processing are output via output DRAM memory 704. Input DRAM memory 702 is composed of a plurality of individual DRAM modules labeled 702a, 702b, and 702c. DRAM memory 702 can be any type of dynamic random access memory, including (but not limited to) DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM. DRAM memory provides high-bandwidth data input capability to feed data (such as inference input or training data) into the processing pipeline.

In some embodiments, each DRAM module 702a, 702b, and 702c has a dedicated interface and data path to each processing element 706. For example, DRAM module 702a may only feed data to processing element 706a,a, while DRAM module 702b only feeds data to processing element 706b,b. This provides modular scalability, as additional DRAM modules can be added to feed more processing elements.

The number of input DRAM memory 702 and individual modules 702a-702c can vary depending on application requirements. For example, there may be 4, 8, 16, or more input DRAM modules. The capacity of each module can range from gigabytes to terabytes, depending on factors such as access speed, power, and cost budget.

High-speed interfaces such as DDR5, GDDR6, or HBM3 can be used to maximize the bandwidth of data transfer between the input DRAM memory 702 and the processing elements 706 across the semiconductor device 707. Shared data buses, crossbar switches, or on-chip networks can interconnect groups of DRAM modules 702 and processing elements 706.

In some embodiments, the input DRAM modules 702 can be stacked or configured in a multi-dimensional configuration to increase total memory capacity and bandwidth while reducing latency and power consumption. A dedicated memory controller and scheduler can manage parallel data access across multiple input DRAM modules 702.

Input DRAM memory 702 provides the high-bandwidth data needs of parallel processing elements 706 to enable fast and efficient data-intensive computations, such as neural network inference. Each processing element 706 can directly access the required input data from its dedicated DRAM module 702 without having to compete with other processors for data access.

In alternative embodiments, instead of or in addition to DRAM memory 702 and 706, adjacent accelerator chiplets may communicate with semiconductor device 707. That is, there may be a grid-like configuration of assemblies 700 communicating with each other to perform AI inference and/or AI training (e.g., transformer inference, CNN perturbation, ANN perturbation, etc.). In some embodiments, there may be a cluster of semiconductor devices 707 that share a bank or portion of DRAM memory 702 and/or 706. In some embodiments, input DRAM memory 702 and output DRAM memory 704 may be combined into the same DRAM memory.

Assembly 700 includes a semiconductor device 707, which includes an array of processing elements, labeled 706a through 706n. Each processing element in the array can be configured to perform specialized computational and data processing operations. For example, in some embodiments, a processing element may be optimized for artificial intelligence workloads, such as neural network inference. In other cases, a processing element may be more focused on general-purpose capabilities. Ultimately, the capabilities of each processing element will be determined by its specific microarchitecture, as desired for a particular application.

Processing elements 706 can access nearby memory storage to retrieve data fed into their computations. This memory can be physically separate from the processing element array 706, as is the case with micro-repositories 708 shown in Figure 7. Processing elements 706 and micro-repositories 708 are aligned so that each micro-repository is positioned directly above its corresponding processing element in a vertical configuration. This tight coupling provides fast data transfer speeds between each micro-repository-element pair.

In a physical embodiment, the processing element array 706 often resides within a semiconductor device 707. Semiconductor device 707 can potentially be fabricated as a standalone chiplet using advanced packaging techniques. This modular chiplet can then be integrated with other components, such as micro-storage chiplet 709, via high-density interconnects. Some options include bumpless hybrid bonding, interposers, or even monolithic 3D integration. Ultimately, combining chiplets allows for the creation of powerful heterogeneous systems with optimized die.

The specific number of processing elements 706 present, their design, and their interconnection scheme can vary between implementations of assembly 700. For example, a simpler system may require only a 2x2 grid of elements, while a complex AI accelerator may have a 32x32 array. Processing elements 706 themselves may also have different memory access routes across the assembly. Point-to-point links, crossbar switches, or a shared bus are all possible connection structures. These architectural decisions are driven by the performance and area constraints being sought.

The second semiconductor device 709 is a separate device from the first semiconductor device 707. Like the first semiconductor device 707, the second semiconductor device 709 can also be implemented as a small chip. The second semiconductor device 709 includes a micro-bank array 708 arranged on a grid spanning from micro-banks 708a,a to 708n,n.

As mentioned, micro-repositories 708 on second semiconductor device 709 are positioned vertically above processing elements 706 on first semiconductor device 707. Based on the subscripts identifying their positions in the grid, each micro-repository 708 is aligned and corresponds to the processing element 706 below it. For example, micro-repositories 708a,a are vertically aligned and correspond to processing elements 706a,a. This allows each processing element 706 to access the micro-repository 708 above it.

Microstore 708 acts as a memory structure that stores data such as AI model weights that can be accessed by underlying processing element 706 during operations such as neural network inference. Microstore 708 is optimized for very fast read times but slow write times. This allows processing element 706 to quickly access the weights and data it needs for its calculations, while less frequently updated data can still be written at a slower rate.

In some embodiments, a second semiconductor device 709 containing a micro-bank array 708 is directly bonded to the first semiconductor device 707 via processing elements 706. This bonding aligns each micro-bank 708 with its corresponding processing element 706 below it. Conductive interconnects between the devices allow each processing element 706 to communicate directly upward with its respective overlying micro-bank 708. This provides a compact, modular, and efficient system architecture.

Micro-storage 708 may contain multiple memory layers, labeled 710a through 710d, each storing weights or data for a different AI model. For example, layer 710a contains the weights for model A, layer 710b contains the weights for model B, and so on. Vertically stacking these layers enables high density and fast access times in the micro-storage design.

Micro-storage 708 can be implemented using a variety of memory technologies optimized for fast readout times to provide data to processing element 706 with minimal latency, including but not limited to SRAM, FeFET, ReRAM, SOT, and STT. Certain embodiments may configure micro-storage 708 to have a read speed significantly faster than its write speed. Micro-storage 708 can be implemented using any of the FeFET or memory structures described herein.

In some embodiments, each micro-bank 708 may have a capacity between 4 kilobytes and 128 kilobytes for storing machine learning model parameters or other data. The bit density per layer may exceed 0.4 gigabits per square millimeter. The compact size of micro-bank 708 (less than 100 microns on each side in one embodiment, or 12 microns by 12 microns in another embodiment) allows for high-density integration of memory modules.

The array-based configuration of micro-repositories 708 enables simultaneous parallel data access by processing elements 706 to support high-throughput data processing by assembly 700. The one-to-one alignment of micro-repositories 708 and processing elements 706 also ensures that each processing element 706 has dedicated access to the data it needs without contention.

Micro-storage bank 708 shares a semiconductor device interface provided by second semiconductor device 709, which facilitates writing data from input DRAM memory 702 to micro-storage bank 708. Reading data from micro-storage bank 708 to processing element 706 and out of DRAM memory 704 is handled through dedicated pathways between each vertically aligned micro-storage bank 708 and processing element pair.

Micro-bank memory layer 710 refers to multiple layers of micro-bank memory vertically stacked within second semiconductor device 709. As shown in FIG7 , there are four separate micro-bank memory layers labeled 710 a, 710 b, 710 c, and 710 d. Each layer contains a micro-bank array, such as micro-bank array 708 shown in the figure.

In one embodiment, micro-banks 708 can utilize a stacked 3D NAND architecture constructed from multiple layers of NAND memory arrays using charge trap flash technology. Each micro-bank 708 can contain a dedicated set of wordline drivers on the bottom layer to facilitate access to the 3D NAND grid array separated by alternating dielectric layers. 3D NAND implementations can be used to maximize density and throughput by leveraging vertical scaling.

In an alternative embodiment, micro-bank 708 employs a 3D NOR architecture constructed from multiple layers of NOR flash memory arrays. Each plane features NOR strings with a source and bit line architecture stacked on top of each other using vias. The 3D NOR configuration optimizes random read and write access times for stored data.

Micro-storage bank 708 can also employ a hybrid configuration with different types of volatile and/or non-volatile memory organized in vertical sub-arrays, such as combining FeRAM and ReRAM cells. This heterogeneous 3D integration allows for optimization of speed, endurance, and retention within the same storage bank structure.

In some embodiments, micro-repositories 708 integrate processing logic, such as analog computation, directly into the memory array stack itself. This in-memory processing approach places basic computational operators in memory peripherals or bit cells to achieve highly parallel and efficient in-situ data processing.

Some implementations may utilize 2.5D or 3D stacking to integrate micro-repositories 708 with other components, such as logic, CPUs, GPUs, or specialized accelerators. This tightly packaged integration, through technologies such as the High-Frequency Wide Memory Cube architecture, reduces data transfer latency and power consumption.

Micro-storage 708 can also employ a virtualized architecture in which an external memory controller handles the translation between the physical array organization and dynamically allocated virtual memory domains. These virtual domains mapped onto the physical array effectively create a separate virtual storage with flexible capacity tailored to application needs.

In some embodiments, micro-storage 708 is designed as a compute RAM (CRAM) with integrated processing capabilities within the bit cell periphery to implement a highly parallel compute-in-memory architecture. The gateless transistor structure integrated into the CRAM array facilitates efficient execution of batch bit-wise operations.

Some implementations place the micro-repositories 708 within a modular memory processing unit (MPU) architecture that contains dedicated processing logic suitable for workloads such as AI inference. The MPU architecture couples the repository array to the vector processor via a high-speed interface such as HBM2 for low-latency data transfer.

Microstore 708 can also implement content addressability by integrating comparison logic into memory peripherals. This facilitates searching or accessing data based on content rather than explicit addresses, enabling powerful pattern matching capabilities.

Some embodiments can stack multiple micro-repository dies on top of a base logic die featuring something like a GPU or AI accelerator. This creates a dense, high-bandwidth heterogeneous system optimized for data-centric workloads while minimizing data movement.

The micro-bank memory layer 710 can be fabricated using a three-dimensional integrated circuit process to stack multiple dies or wafers containing arrays of micro-banks 708 on top of each other. Through-silicon vias (TSVs) or other vertical interconnect technologies can be used to enable communication between layers.

In some embodiments, each micro-repository memory layer 710 corresponds to a different artificial intelligence (AI) model or application. For example, layer 710a may store weights and parameters for AI model A, layer 710b may store weights and parameters for AI model B, and so on. This allows multiple AI models to be efficiently stored within the same micro-repository memory 708 structure.

In some embodiments, micro-banks 708 may have a capacity ranging from 4 kilobytes to 128 kilobytes. In other cases, the capacity may be between 4 kilobytes and 16 kilobytes. In some embodiments, each micro-bank may have lateral dimensions of less than 100 microns by less than 100 microns, while extending vertically to incorporate potentially more than 200 memory cells.

In some embodiments, the bit density per square millimeter per layer within the micro-bank memory layer 710 can facilitate high-capacity storage with a small footprint. The layer can utilize non-volatile memory technologies (such as FeFETs, STT-MRAM, or ReRAM) to retain data when power is removed.

In operation, processing element 706 may access weights or parameters from micro-repository memory layer 710 to perform neural network inference or other machine learning computations.

The inference results of various AIs can be sent to output DRAM memory 704, which includes individual DRAM memory modules labeled 704a, 704b, and 704c. Output DRAM memory 704 is located adjacent to micro-storage array 708 and second semiconductor device 709. Output DRAM memory 704 can serve as temporary data storage, buffering output data retrieved from micro-storage 708 before external transmission.

Each DRAM memory module 704a, 704b, and 704c can have similar or different storage capacities, depending on design requirements. For example, in one embodiment, each module contains 16 million bits of storage. DRAM cells utilize a capacitor to hold data bits in the form of a charge. Due to charge leakage, DRAM memory requires periodic refresh cycles to maintain the integrity of stored data. To enable simultaneous reads and writes across multiple modules, each DRAM module 704a, 704b, and 704c can have dedicated internal control circuitry and I/O ports.

Data output from individual micro-storage banks 708 can be aggregated and buffered in output DRAM memory 704 before being transmitted to external components via the peripheral circuitry. Buffering the data allows the transfer rate to be adjusted to match the requirements of the external interface. It also enables data processing operations such as formatting, encoding, or encryption to be performed by the second semiconductor device 709 before output.

In some embodiments, output DRAM modules 704a, 704b, and 704c are designed to provide high-density, low-cost temporary data storage to support high-bandwidth, parallel reads from micro-storage array 708. Optimizing these performance parameters allows for efficient retrieval of data from the micro-storage to feed computational workflows hosted on external chips or devices. Certain implementations can utilize various types of DRAM, including asynchronous DRAM, synchronous DRAM, graphics DRM, and low-power DRM appropriate to the application. In summary, output DRAM memory 704 facilitates seamless data movement from the integrated micro-storage to the external execution pipeline.

FIG8 shows an assembly 800 including semiconductor devices 802, 804, 806, 808, 810, 812, and 814 of several memory types according to an embodiment of the present invention. Specifically, FIG8 shows an exemplary assembly 800 of semiconductor devices 802, 804, 806, 808, 810, 812, and 814 configured to provide a multi-level memory structure. Assembly 800 is modular and scalable to allow stacking of various combinations and numbers of semiconductor devices (which, in some embodiments, may be implemented as chiplets) to meet specific performance and density requirements.

Assembly 800 includes an application semiconductor 802, which may be a plurality of processing elements described herein. A semiconductor device 814 comprising a micro-bank array is located on top of semiconductor device 802. A semiconductor device 812, which may also comprise a micro-bank array, is located on top of semiconductor device 814. Semiconductor devices 810 and 808, which may be SRAM bank dies, are located on top of semiconductor device 812. Semiconductor devices 806 and 804, which may be DRAM bank dies, are located on top of semiconductor device 808. These banks 816 may be arranged in a grid-like manner, such that banks 816a,a through 816n,n are indexed. Each of these repositories may include a respective microrepository from semiconductor devices 804, 812, a respective SRAM repositories from semiconductor devices 810, 808, and a respective DRAM repositories from semiconductor devices 806, 804.

Semiconductor device 802, which includes a plurality of processing elements, is located at the base of assembly 800. These processing elements perform computing tasks and facilitate data flow within the system.

Directly above semiconductor device 802 is semiconductor device 814 (which includes an array of microbanks). These microbanks utilize field-effect transistors (FeFETs), known for their non-volatile properties and suitability for high-density memory applications. FeFET-based microbanks can be designed to achieve high-speed read operations, essential for rapid data retrieval during processing tasks such as AI inference, while also supporting slower write operations that are more tolerant of latency. Semiconductor device 812 (which similarly includes an array of microbanks) is stacked on top of semiconductor device 814. The presence of multiple layers of micro-storage in semiconductor devices 814 and 812 illustrates the scalability of the assembly, where additional memory capacity and functionality can be integrated through additional layers.

To further assist with the memory hierarchy, semiconductor devices 810 and 808 are depicted as SRAM bank dies positioned above semiconductor device 812. SRAM provides fast access memory that can act as a cache or buffer for the slower but denser FeFET micro-bank memory layer below.

Semiconductor devices 806 and 804 (shown as DRAM bank dies) are at the top of assembly 800 and therefore at the top of the memory structure. DRAM is commonly used for main memory due to its relatively higher speed and lower cost per bit than SRAM to provide a balance between performance and economy.

Arranging memory banks 816 (subscripted 816a, a through 816n, n) in a grid-like fashion indicates that each processing element at a given location (a, b) in semiconductor device 802 has dedicated access to a corresponding vertically aligned memory bank in the micro-memory bank and memory cell in the layer above. This vertical stacking and alignment ensures that data and control signals can be routed directly between the processing element and its respective memory stack, facilitated by interconnect technologies such as through-silicon vias (TSVs) and microbumps used in the 3D integrated circuit architecture of assembly 800.

The modular and scalable design of assembly 800 allows various combinations of semiconductor devices or chiplets to be integrated into a wider system. The flexibility in the number and combination of stacks provides the assembly with the adaptability to meet varying application requirements and performance demands. Each of the banks within bank 816 within assembly 800 exhibits a multi-die structure that contributes to the overall capacity and performance of the system.

FIG9 shows an assembly of a semiconductor device including a semiconductor device 914 having a single-chip system and another semiconductor 906 having a microstorage bank mounted on top, according to an embodiment of the present invention. Assembly 900 integrates semiconductor device 906 and semiconductor device 914, which can be implemented as separate small chips bonded together. Semiconductor device 914 includes various components for facilitating reading data from the microstorage bank on semiconductor device 906, such as a read address register input interconnect 924, read data register 922, and read data register output interconnect 950. These components pass the read address to the microstorage on semiconductor device 906 and return the read data to semiconductor device 914.

Specifically, the read address is entered into a read address register 926 via interconnect 924. The output of this register 962 is connected to another read address register 938 on semiconductor device 906 via interconnects and bumpless bonds, which in turn addresses the target micro-storage bank 936. Micro-storage bank 936 outputs the read data to a read data register 942 via interconnect 940, which transfers the data back to read data register 922 on semiconductor device 914 via bumpless bonds 910 and 918. This data can then be accessed externally via read data register output interconnect 950. Additionally, semiconductor devices 914 and 906 have interconnecting through-silicon vias 916 and 944 to allow communication with devices that may be stacked above semiconductor device 906.

Semiconductor device 906 has various memory structures for providing data storage capabilities. This includes a microstorage bank 936 that provides high-density, low-latency data storage, as well as other peripheral memory components (such as read data register 942 and read address register 938) to facilitate data access. Microstorage bank 936 is often located on the BEOL portion of a chiplet to allow for dense 3D integration of memory layers. In some embodiments, the microstorage bank utilizes non-volatile memory technology (such as FeFET or STT-MRAM) to retain data in the absence of power.

Semiconductor device 914 includes processing elements and data routing circuitry for retrieving and manipulating data stored in semiconductor device 906. Components such as read address register 926 and read data register 922 process sending read addresses and receiving data from micro-storage 936, respectively. Device 914 also includes interconnects 924, 950 and through-silicon vias 916 for external communications.

The two devices 906 and 914 are integrated via fine-pitch interconnects, such as bumpless hybrid bonds 908, 910, 918, 920, 930, and 932. This allows for direct data transfer paths between the processing elements in device 914 and the memory structures in device 906. Alignment during bonding ensures dedicated access, for example, the read data register output interconnect 950 on 914 is directly linked to the read data register 922 to receive the requested data.

The path that facilitates data flow during a read can be summarized as follows: A read address is entered into read address register 926 on device 914 via interconnect 924. This is passed via the interconnect and bumpless bonding to read address register 938 on device 906, which then addresses microstore 936. The request data is passed via interconnect 940 to read data register 942, which is then passed back via bonding to read data register 922 on 914, where it can be made available externally via interconnect 950.

Assembly 900 exemplifies a modular, high-density architecture optimized for data-centric applications such as AI inference. Advanced packaging technology allows for close integration of processing and storage dies, enabling localized data access with minimal latency and power. Scalability is also achieved by incorporating multiple chiplets (in this case, devices 906 and 914). Assembly 900 illustrates a potential configuration suitable for space-constrained high-performance computing systems.

Through-silicon via (TSV) 916 is an electrical connection that passes vertically through semiconductor device 914. Its purpose is to provide a path for signals to travel between the top and a processing element within semiconductor device 914. This allows the device to be stacked and interconnected with other components in a vertical configuration. TSV 916, along with other TSVs on the device, facilitates high-density 3D integration and heterogeneous stacking of multiple devices (such as chiplets).

TSVs 916 interact with several other components within the system. On the top side of semiconductor device 914, it connects to interconnect 912, which couples it to bumpless bonds 918. When the two devices are stacked, these bonds interface with complementary bumpless bonds 910 on the bottom side of semiconductor device 906. This allows signals to travel from device 914 to device 906 through TSVs 916. Routing continues when the signal passes through interconnect 902 to TSVs 944 on device 906. TSVs 944 provide a vertical signal path to the top surface of device 906 where additional devices can be stacked. In the reverse direction, signals can travel from TSV 944 down through device 906, back along TSV 916, and down into device 914. Thus, TSV 916 provides bidirectional vertical communication across the device boundary.

There are several possible variations on the TSV 916 implementation. First, multiple TSVs configured in an array can be used instead of a single via to increase throughput and redundancy. Second, the size and material of the TSVs can be optimized. For example, a smaller TSV diameter using a denser material such as tungsten can be advantageous. Additionally, the interface circuitry that drives the signals into the TSVs (such as interconnects 912 and 902) can employ variable line drivers to support different voltage levels or signal integrity enhancements. Further embodiments may include integrated monitoring circuitry within TSVs 916 to track metrics such as temperature and link utilization. And in future scenarios, alternative signaling schemes other than electrical signals may be employed. For example, integrated silicon photonics that uses modulated light to transmit data through TSVs can achieve very high-bandwidth and low-latency connectivity. There are multiple paths to further develop the capabilities of TSV-based vertical links (such as TSV 916 in these complex 3D integration architectures).

There are several variations and alternatives to the interconnect 912 implementation. For example, the paths forming the interconnect 912 can be fabricated using different conductive materials, such as copper or aluminum, and optimized for conductivity or heat dissipation. Additionally, the interconnect 912 can have redundant signal paths or self-healing capabilities using spare interconnects to improve reliability and resilience. The bumpless joints 918 and 910 of the connecting devices 906 and 914 can also be replaced with other high-density joint methods, such as hybrid joints or through-silicon vias. Furthermore, alternative signaling schemes other than simple digital logic, such as analog signaling or multi-level digital waveforms, can be used on the interconnect 912 to enhance data transmission capabilities. The routing and size of the interconnect 912 can also be adjusted based on bandwidth requirements or circuit layout considerations. In summary, there are many structural and functional alternatives for making interconnect 912 to meet application requirements.

Bumpless bond 918 is an electrical connection between interconnect 912 and bumpless bond 910 of semiconductor device 906 on semiconductor device 914. Bumpless bond 918 provides an electrical path for signals to travel between semiconductor device 914 and any additional semiconductor devices stacked on top of assembly 900, such as semiconductor device 906. Signals transmitted through bumpless bond 918 may include data signals, control signals, address signals, or any other signals required to coordinate operations between multiple semiconductor devices.

There are several possible variations of bumpless bonding 918. Depending on the signal bandwidth requirements, the number of individual bonding sites can range from just a few to hundreds. The bonding method can utilize techniques such as direct bonding, plasma activated bonding, adhesive bonding, or compression bonding. Hybrid bonding methods are also possible, which combine direct wafer bonding with intermediate metal bonding. The size and pitch of each bonding site can be varied and a pitch of less than 10 microns can be used to achieve high-density connections. Redundant bonding can provide backup paths. Shielding structures can be used around the bonding for noise immunity. In summary, many embodiments of bumpless bonding 918 can meet cost, reliability, and performance requirements.

Bumpless bond 910 provides an interface for transmitting signals between semiconductor device 906 and semiconductor device 914. Specifically, bumpless bond 910 of semiconductor device 906 is electrically coupled to a complementary bumpless bond 918 of semiconductor device 914. This allows signals such as read/write data and addresses to be transmitted between the two devices. The bumpless nature of the bond allows for a low-profile, high-density interconnect.

Bumpless bond 910 interacts with other components in the system to facilitate data transfer operations. For writes, data enters semiconductor device 914 through through-silicon via 916, passes through interconnect 912 and bumpless bond 918 before reaching bumpless bond 910 on device 906. For reads, the address flows from read address register 926 on device 914 through interconnects 928, 930, and bumpless bond 932 to read address register 938 on device 906. The read data then returns to device 914 through bumpless bonds 908 and 920. Thus, bumpless bond 910 provides critical data and address routing between devices.

Possible variations of bumpless joint 910 include using different joint densities, materials, or electrical contact configurations to optimize performance. The joint can use alloying or doping techniques to improve conductivity. In addition, the routing of signals can be changed, such as by using separate ports for input and output rather than shared ports. More bumpless joints can be added to increase bandwidth between devices. Shielding can be added around the joint to reduce interference. In summary, many modifications can be made to bumpless joint 910 within the scope of electrically interconnecting multiple devices.

Through-silicon vias (TSVs) 944 are electrical connections that pass vertically through semiconductor device 906 from the top to the bottom. They facilitate the transfer of signals and data between semiconductor device 906 and any additional semiconductor devices that may be stacked atop it in a 3D integrated circuit configuration. TSVs 944 enable high-density interconnects between multiple stacked semiconductor layers, providing an efficient method for data routing and signaling.

The TSVs 944 interface with the surrounding circuitry within the semiconductor device 906 to allow signals to be transmitted upward or downward, depending on the system configuration. On one end, the TSVs 944 are coupled to the read data register 942 via interconnects 946. The read data register 942 can use the TSV 944 path to transmit read data from the microstorage 936 to the external semiconductor device. This enables efficient data offloading from the on-chip memory. On the other end, the TSVs 944 continue through to the top surface of the semiconductor device 906, where the TSVs 944 can interface with complementary contacts or interconnects on the bonded semiconductor above it. This facilitates the vertical transmission of signals and data along the assembly 900.

There are many variations in the specific implementation of TSV 944. Its size can range from a few microns to tens of microns to match pitch requirements. TSV 944 can be tapered, straight, or have a non-uniform cross-section. It can utilize different conductive materials as a liner and filler, including metals such as copper, tungsten, or alloys. An insulating liner made of a material such as silicon dioxide can separate the conductive filler from the substrate. The contacts and interconnects coupled to TSV 944 can also have different layouts. If desired, multiple TSVs can be placed adjacent to each other in a high-density array configuration. In summary, many architectural optimizations in the design and manufacturing process of TSV 944 are within the scope of the present invention.

FIG10 shows a semiconductor assembly 1000 incorporating a daisy-chain configuration of micro-storage banks 1036 and 1058 operatively connected to a multiplexer 1060 and managed by a counter 1062 for coordinating data selection and retrieval, according to an embodiment of the present invention. This assembly 1000 is designed to perform data processing tasks, potentially for applications such as artificial intelligence (AI) and machine learning that utilize high-speed data access and processing.

Assembly 1000 includes two main semiconductor devices: semiconductor device 1006 and semiconductor device 1014. Semiconductor device 1014 is depicted as containing several interfaces and registers for data communication, including a read address register input interconnect 1024. This interconnect 1024 facilitates the transfer of read addresses to a read address register 1026, which temporarily stores the read addresses before they are transferred to corresponding micro-banks 1036, 1058 in semiconductor device 1006 for data retrieval operations.

In semiconductor device 1014, interconnect 1028 serves as a path for transitioning the read address from read address register 1026 to bumpless bond 1030. Bumpless bonds 1030 and 1032 represent high-density, low-profile electrical connections between semiconductor device 1014 and semiconductor device 1006 to ensure that the read address is transmitted with minimal signal loss and physical space requirements.

The received address reaches the read address register 1038 in the semiconductor device 1006 via interconnect 1034, which then instructs the micro-storage bank 1036 to output a request to read the data. The micro-storage bank 1036 (a memory storage unit) can encompass a variety of memory technologies (such as FeFET and/or 3D-NAND structures described herein) to facilitate storage and fast retrieval of data.

Multiplexer 1060 selects the appropriate data stream from the outputs of multiple micro-banks 1036 and 1058. Controlled by a counter 1062, which can operate according to a predefined sequence or be driven by an external control signal, multiplexer 1060 arbitrates between the outputs of micro-bank 1036 and another micro-bank (designated micro-bank 1058). Micro-bank 1058, similar in function and underlying memory technology to micro-bank 1036, provides multiplexer 1060 with an additional data source to choose from.

Once the multiplexer 1060 selects the desired data, it is temporarily stored in a read data register 1042, also located within the semiconductor device 1006. This register 1042 acts as a buffer to hold the data for subsequent processing or transmission. The read data is then routed via the interconnect 1004 to the bumpless bond 1008, which facilitates data transfer to the semiconductor device 1014.

Bumpless bonds 1010, 1018 facilitate continuous data travel through assembly 1000 to ensure data is transferred from semiconductor device 1006 to semiconductor device 1014. Once the read data reaches semiconductor device 1014, it is directed via interconnect 1048 to a read data register, specifically, read data register 1022, where it can be accessed by an external system, such as an application specific integrated circuit (ASIC) or a system on a chip (SoC), via read data register output interconnect 1050.

Additionally, assembly 1000 includes through-silicon vias (TSVs) 1016 and 1044 to provide vertical electrical connections through semiconductor devices 1014 and 1006, respectively. These TSVs enable additional semiconductor devices or die to be stacked on top of assembly 1000, thereby allowing the system's capabilities to be expanded vertically. Interconnects 1012 and 1046 serve as horizontal pathways for signals to travel to and from TSVs 1016 and 1044, respectively.

Although the description presents a particular configuration, assembly 1000 is susceptible to various modifications and alternative embodiments. For example, the number and arrangement of micro-storage banks, the specific type of memory technology used within the micro-storage banks, and the configuration of interconnects and bonding areas can be adapted to meet the requirements of different applications.

In some embodiments, semiconductor devices 1006 and 1014 can be designed to accommodate additional functionality, such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or power management circuitry for optimizing energy consumption. Thus, the detailed structure of FIG10 serves as a foundation upon which a variety of complex semiconductor systems can be built, each tailored to the specific needs of its intended application.

10 , the micro-banks exemplified by micro-banks 1036 and 1058 present a daisy-chain configuration that allows for a scalable and flexible memory architecture within semiconductor device 1006. This daisy-chain is facilitated by a series of interconnecting paths and controlled by multiplexer 1060 in coordination with counter 1062.

Each micro-storage bank (such as 1036 and 1058) is designed to store and provide fast access to data, which may be in the form of stored charge, magnetic state, ferroelectric material state, or other physical embodiments of binary information. The micro-storage banks are interconnected so that the output of one micro-storage bank can be routed to the input of another micro-storage bank to create a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 1034 for micro-storage bank 1036 and interconnect 1056 for micro-storage bank 1058, which act as conduits for the read data signals emitted from the micro-storage banks.

Multiplexer 1060 manages the flow of data from this micro-storage daisy chain. It is designed with multiple inputs, each connected to a micro-storage output via its own interconnect. In the example provided, interconnect 1040 carries read data from micro-storage 1036, and interconnect 1056 carries read data from micro-storage 1058 to multiplexer 1060. Multiplexer 1060 can select which input is connected to its output at any given time, thereby controlling the forwarding of data from that micro-storage to read data register 1042.

Counter 1062 orchestrates the operation of multiplexer 1060. It can be a binary counter or any form of sequential logic circuitry that generates a series of output states in response to a clock signal. Counter 1062 advances through its state with each tick of the clock, which can be provided by an external clock source or generated internally within semiconductor device 1006. As counter 1062 advances, its output provides a control signal that indicates which input of multiplexer 1060 is selected.

For example, at the first clock pulse, counter 1062 may instruct multiplexer 1060 to connect the output from micro-storage bank 1036 to read data register 1042. At the next clock pulse, the counter may switch the connection to the output of micro-storage bank 1058, and so on, cycling through the available micro-storage banks in a predefined order. The sequence and timing of the counters can be configured based on the desired data access pattern and the specific requirements of the processing task at hand.

Pulse-driven coordination allows for efficient and organized data retrieval from a potentially large array of micro-repositories. It ensures that each micro-repository has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable, rhythmic progression. This is particularly advantageous in systems where large amounts of data must be processed in parallel, as it provides a systematic approach to accessing and utilizing stored information.

It should be noted that although Figure 10 shows only two micro-banks, the daisy-chain structure described can be expanded to accommodate any arbitrary number of micro-banks. Additional micro-banks can be added to the chain, with each new micro-bank connected to the multiplexer via an additional input line. Multiplexer 1060 and counter 1062 will be scaled accordingly to manage the increased number of inputs to maintain a synchronously pulsed sequential data acquisition process across the expanded memory architecture.

This microstorage daisy-chain combined with a multiplexer and counter-driven control system exemplifies a modular and scalable approach to memory design in semiconductor devices. It allows customizing memory arrays to match the capacity and performance requirements of a wide range of applications, from embedded systems to large data centers, providing a versatile solution to modern computing challenges.

FIG11 shows a semiconductor assembly 1100 incorporating a daisy-chain configuration of a plurality of semiconductor devices 1106, 1116 into a microstorage bank operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval according to an embodiment of the present invention.

This detailed description relates to FIG. 11 of the accompanying drawings, which illustrates an embodiment of an assembly 1100 as part of an integrated circuit. Assembly 1100 can be viewed as a multi-layer structure including a bottom semiconductor device 1122, a middle semiconductor device 1116, and a top semiconductor device 1106 (each of which can be a small chip). Each semiconductor device is configured to interface with other semiconductor devices via a series of bumpless bonds (e.g., bumpless bonds 1128, 1129, 1158, 1159, 1160, 1161, 1162, and 1163), which facilitates electrical connectivity without the additional outline of traditional bonding methods, thereby achieving a compact and dense stacking of semiconductor layers.

The bottom semiconductor device 1122 includes a read address register 1126 that can be configured to store read addresses and transmit them to a micro-repository located across the assembly 1100. The read address register 1126 communicates via an interconnect 1174 that acts as a conduit for signals directed to bumpless bonds 1128. These bonds, in turn, bond to bumpless bonds 1129 of the middle semiconductor device 1116, thereby transmitting the read address to the middle semiconductor device. The bottom semiconductor device 1122 also includes a read data register 1124 that can serve as a repository for the received read data. The read data is received via an interconnect 1176 connected to the bumpless bond 1158 , which communicates with the bumpless bond 1159 of the middle semiconductor device 1116 .

Intermediate semiconductor device 1116 serves as an intermediate layer within assembly 1100, housing microstorage banks, such as microstorage bank 1132 and microstorage bank 1118, each of which can be designed to store and quickly provide access to data. These microstorage banks are linked to other components within the device via interconnects, such as interconnect 1130 and interconnect 1134, which direct the flow of read addresses and read data, respectively. Intermediate semiconductor device 1116 also has a read address register 1146 that receives read addresses from interconnect 1130 and a read data register 1154 that collects read data from TSVs 1152.

A multiplexer 1114 within the middle semiconductor device 1116 selects between the various data streams. This multiplexer is controlled by a phase counter 1110, which determines the data selection sequence based on input received from the top semiconductor device 1106 via TSVs 1152. A read data register 1112 serves as a storage area for the selected data stream from the multiplexer 1114.

The top semiconductor device 1106 has a phase counter 1102 and a read data register 1104, which are used to coordinate the flow of data within the assembly 1100. The phase counter 1102, in conjunction with the multiplexer 1150, directs the output of read data from the micro-storage banks 1138 and 1164 based on the selected phase. The read data register 1104 captures the output from the multiplexer 1150, which is then relayed via the interconnect 1108 to the bumpless bond 1162 to facilitate communication with the middle semiconductor device 1116.

Assembly 1100 illustrates the integration of multiple micro-banks across different semiconductor devices. For example, micro-bank 1132 on intermediate semiconductor device 1116 can receive a read address from read address register 1146 via interconnect 1134 (path "1"). Similarly, micro-bank 1118 can receive a read address from the same register via interconnect 1156 (path "2"). Micro-repositories 1138 and 1164 on the top semiconductor device 1106 receive read addresses from a read address register 1142 via interconnect 1140 and paths "3" and "4," respectively. The read address register 1142 communicates with the middle semiconductor device 1116 via TSV 1136 and bumpless joints 1160 and 1161.

Each micro-bank (e.g., 1132, 1118, 1138, and 1164) can potentially output read data to multiplexer 1114 or 1150, where the data is then selected based on the configuration of the respective phase counter 1110 or 1102. The selected data is temporarily stored in a read data register (1112 or 1104) before being transmitted down the assembly 1100 through the respective bumpless bonds and interconnects to ultimately reach the read data register 1124 of the bottom semiconductor device 1122. This configuration allows data to be read out simultaneously from all micro-banks, which can be essential in applications requiring parallel processing and high-speed data access.

TSVs (such as 1136 and 1152) provide vertical connectivity across the semiconductor device to enable integration of additional layers or functionality on top of the existing assembly 1100. These TSVs couple to various interconnects and bumpless joints that create the necessary pathways for signal transmission within and between semiconductor devices.

In some embodiments, the micro-storage banks within assembly 1100 may include various memory technologies (such as 3D-NAND or 3D-NOR structures) and be configured to facilitate parallel processing and efficient data retrieval. Each micro-storage bank may include additional features such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or power management circuitry for optimizing energy consumption.

Data path 1 within assembly 1100 illustrates a route through which read addresses and corresponding read data are transmitted across the assembly, specifically, directing operations from a read address register 1126 located on the bottom semiconductor device 1122 to a read data register 1124 within the same device.

The process begins with a specific read address stored in read address register 1126. This address is sent via interconnect 1174, which acts as a channel for the signal. The read address is then transferred to bumpless bonds 1128, which are carefully designed to create a reliable electrical connection without the physical protrusions associated with traditional bonding methods. These bonds ensure a low-profile interface that maintains the compactness of the semiconductor stack.

The signal continues from bumpless bond 1128 to bond with bumpless bond 1129 of middle semiconductor device 1116. The read address is carried forward by interconnect 1130, which transmits the address to read address register 1146 of middle semiconductor device. Read address register 1146 then propagates the read address through interconnect 1134 (labeled as path "1" which directs the signal to microbank 1132).

Upon receiving a read address, micro-bank 1132 accesses the requested data. This data is then output via interconnect 1170 and directed to multiplexer 1114. In some embodiments, multiplexer 1114 acts as a selective switch that selects between data streams based on the configuration determined by phase counter 1110. This phase counter can be designed to cycle through a sequence indicating the timing and selection of the data stream to ensure that each micro-bank is read in a coordinated manner.

The selected data from multiplexer 1114 is then captured by read data register 1112, which temporarily stores the data. The data is then sent through interconnect 1120, which carries the signal to bumpless bonds 1159. These bonds are part of a complex electrical interconnect system that, along with bumpless bonds 1158 on the bottom semiconductor device 1122, enable vertical and horizontal integration within the semiconductor stack.

The signal, now in the form of read data, traverses from bumpless bond 1159 to bumpless bond 1158 and is ultimately introduced into interconnect 1176. This interconnect completes the connection to read data register 1124, which is configured to receive and store the read data. Read data register 1124 can be configured to hold the data for subsequent processing or external communication.

Data path 2 within assembly 1100 defines a route specifically designed to transfer a read address from a read address register 1126 on the bottom semiconductor device 1122 to the microstorage 1118 on the middle semiconductor device 1116 and then transfer the read data back to the read data register 1124 on the bottom device.

The process begins at read address register 1126, which holds a read address in preparation for dispatch. This register is part of the semiconductor device's control mechanism and orchestrates the retrieval of data by issuing specific addresses to memory cells. The read address is sent from read address register 1126 via interconnect 1174, which provides a safe and reliable path for electrical signals within the integrated circuit.

The read address continues from interconnect 1174 to bumpless bond 1128, which provides a seamless and low-profile connection to the middle semiconductor device 1116 via corresponding bumpless bond 1129. These bonds maintain signal integrity during inter-layer communication and are designed to accommodate the requirements of modern semiconductor architectures.

The signal is then directed via interconnect 1130 to read address register 1146 within intermediate semiconductor device 1116. Read address register 1146 acts as a secondary storage and retention register, from which the read address is directed down interconnect 1156 (labeled path "2" which terminates at micro-repository 1118).

Upon receiving a read address, micro-storage 1118 accesses the corresponding data. This data retrieval process is facilitated by the micro-storage's internal architecture, which may include a memory array optimized for fast access and data stability. The read data is output from micro-storage 1118 and travels through interconnect 1172, which leads to multiplexer 1114.

Multiplexer 1114 determines which data stream to forward based on the input from phase counter 1110. Phase counter 1110 operates in synchronization with the system clock or an external control signal to cycle through various states to control the selection process of multiplexer 1114 in a precise and predictable manner.

The output of multiplexer 1114, now carrying the selected read data, is sent to read data register 1112. This register temporarily stores the read data, acting as a buffer. The read data is then dispatched via interconnect 1120 toward bumpless bond 1159.

Bumpless bond 1159 interfaces with bumpless bond 1158 on bottom semiconductor device 1122, where signals are transmitted downward through the assembly. The read data then passes through interconnect 1176 to its final destination: read data register 1124. Read data register 1124 captures the read data and stores it for further processing or transmission to external circuitry.

Data path 3 within assembly 1100 is another communication route that illustrates the data transfer sequence from the read address register 1126 on the bottom semiconductor device 1122 through various components to the microstorage 1138 on the top semiconductor device 1106 and then back to the read data register 1124 on the bottom device.

The sequence begins at the read address register 1126, which serves as the origin for the read address. Register 1126 safely holds the address until it is dispatched via interconnect 1174. Interconnect 1174 acts as a dedicated channel to ensure the read address is accurately transmitted to the bumpless bonds 1128. These bumpless bonds 1128 facilitate a streamlined connection to the bumpless bonds 1129 of the intermediate semiconductor device 1116 to maintain the integrity and compactness of the signal path.

Upon reaching the middle semiconductor device 1116, the read address is relayed to the read address register 1146 via interconnect 1130. The read address register 1146 serves as a junction for further propagation of the address signal via through-silicon via (TSV) 1136. TSV 1136 is a vertical interconnect that penetrates the semiconductor substrate, providing a direct link from the middle semiconductor device 1116 to the top semiconductor device 1106, thereby exemplifying the 3D integration capability of semiconductor designs.

The read address rises from TSV 1136 and appears on bumpless bond 1160 on middle semiconductor device 1116. Bumpless bond 1160 connects to bumpless bond 1161 on top semiconductor device 1106. The address signal is conducted through interconnect 1140 to read address register 1142 on top device 1106.

Read address register 1142 directs a signal along interconnect 1144 upon receiving a read address. This path (labeled "3") directs the address to micro-storage 1138. Micro-storage 1138, designed for data storage, retrieves the request information in response to the read address. The read data is output via interconnect 1166, which feeds the data into multiplexer 1150.

The multiplexer 1150 in the top semiconductor device 1106 is controlled by the phase counter 1102, which indicates the selection of the data stream directed to the read data register 1104. The selected data stream is temporarily stored in the read data register 1104, where it awaits transmission downstream.

Read data leaves the read data register 1104 via interconnects 1108 connected to bumpless bonds 1162. These bonds 1162 bond to corresponding bumpless bonds 1163 on the middle semiconductor device 1116 to transfer the read data to the TSVs 1152.

TSV 1152 operates as a vertical conduit to allow read data to pass down to middle semiconductor device 1116, where the read data is received by read data register 1154. Read data register 1154 temporarily stores the read data before it is directed to multiplexer 1114 via interconnect 1156.

Multiplexer 1114 in intermediate semiconductor device 1116 selects the data suitable for output in coordination with phase counter 1110. The read data is then directed to read data register 1112, where it is temporarily stored. The read data then travels through interconnect 1120 to bumpless bond 1159.

Bumpless bond 1159 forms an interface with bumpless bond 1158 on bottom semiconductor device 1122. The read data signal is then carried through interconnect 1176 to terminate at read data register 1124 on the bottom device.

Data path 4 within assembly 1100 establishes a path for read address flow from the read address register 1126 on the bottom semiconductor device 1122 to the micro-storage 1164 located on the top semiconductor device 1106, and then facilitates the movement of read data back down to the read data register 1124 on the bottom device.

This data path begins at the read address register 1126, which is responsible for storing and issuing the read address required to retrieve data from the microstorage. The read address is sent from register 1126 through interconnect 1174 (a path that maintains signal integrity and facilitates electrical communication).

The read address is routed from interconnect 1174 to bumpless bonds 1128. These bond areas create an interconnect between bottom semiconductor device 1122 and middle semiconductor device 1116 via bumpless bonds 1129. The design of these bumpless bonds facilitates data transfer.

Once the read address reaches the middle semiconductor device 1116, it is carried forward via interconnect 1130 to the read address register 1146. This register acts as an intermediary to prepare the address for vertical ascent through the device stack. The address is then transmitted via through-silicon vias (TSVs) 1136, which facilitate vertical integration by providing a direct electrical link through the semiconductor substrate.

After rising through TSV 1136, the read address appears on bumpless bond 1160, which is aligned to connect with bumpless bond 1161 on top semiconductor device 1106. The read address then travels along interconnect 1140 to read address register 1142 located on the top device.

Read address register 1142 is used to forward the read address to its final destination, micro-repository 1164, via interconnect 1148 (labeled as path "4"). Micro-repository 1164, upon receiving the read address, retrieves the request data, which is then output via interconnect 1168. This data is directed to multiplexer 1150, which is under the control of phase counter 1102.

Phase counter 1102 determines which data stream is selected by multiplexer 1150, which then sends the read data to read data register 1104. Read data register 1104 acts as a temporary storage repository to hold the data until it can be sent down through the device stack.

The data leaves the read data register 1104 and travels through interconnect 1108 to bumpless bonds 1162. These bonds maintain a connection to bumpless bonds 1163 on the middle semiconductor device 1116. The read data is then transferred to TSVs 1152, which carry the data vertically downward to the read data register 1154 on the middle semiconductor device 1116.

Read data register 1154 temporarily stores read data before it is fed to multiplexer 1114 via interconnect 1156. Multiplexer 1114, coordinated by phase counter 1110, directs the appropriate data stream to read data register 1112. This register serves as a reserve area for read data, which is then sent to bumpless bond 1159 via interconnect 1120.

Bumpless bond 1159 interfaces with bumpless bond 1158 on bottom semiconductor device 1122 to provide a downward transmission of read data. Finally, the signal is routed through interconnect 1176 and reaches read data register 1124, where the data can be used for subsequent processing or external communication.

FIG12 illustrates a three-dimensional (3D) memory row 1200 configured as a 3D-NOR or 3D-AND structure having a series of ferroelectric field effect transistors (FeFETs) 1202 having interconnected drain terminals 1204 linked to a common select line 1212 and individual gate terminals 1206 (e.g., 1214 a for FeFETs 1202 a, all coupled to a common bit line) connected to respective read/write enable lines 1214, according to one embodiment of the present invention.

12 depicts a three-dimensional (3D) memory row, designated as element 1200, which can be configured in various embodiments as a 3D-NOR or 3D-AND structure to provide flexibility in integrated circuit applications and usage. This memory row is an assembly of a plurality of ferroelectric field-effect transistors (FeFETs), collectively referred to as FeFETs 1202, where each FeFET is indicated by an element such as 1202a, 1202b, 1202c, and 1202d, which may be present in the array.

Within each FeFET (e.g., 1202a), there is a drain terminal 1204a. This drain terminal is part of the output path of the memory cell and is connected to a common select line 1212. In some embodiments, the common select line 1212 acts as a control mechanism that can select a specific FeFET for data read or write operations.

The gate terminal of each FeFET (exemplified by 1206a of FeFET 1202a) is individually connected to a separate read/write enable line (e.g., 1214a). This controls the state of the FeFET, allowing it to be in a conductive (on) state for reading or writing data, or in a non-conductive (off) state to prevent data flow. The presence of separate read/write lines for each FeFET allows for precise control and operation of each memory cell.

Furthermore, each FeFET (e.g., 1202a) includes a source terminal (e.g., 1208a) coupled to a common bit line 1210. Bit line 1210 provides a conduit for writing data to or reading data from the FeFET. In some embodiments, this bit line can be shared across multiple memory rows, which can facilitate parallel processing and increase data throughput.

According to various embodiments of the present invention, 3D memory row 1200 may incorporate additional components and configurations to enhance performance and functionality. For example, 3D memory row 1200 may include insulating materials, conductive traces, and other structural components not explicitly shown in FIG. 12 but inherent to these 3D memory structure implementations. FeFETs 1202 may also exhibit variations in material composition, structural dimensions, and electrical properties to facilitate a range of performance characteristics suitable for different applications.

Furthermore, memory rows 1200 can be incorporated into larger memory arrays to form part of a memory module or system. These arrays can be arranged in various configurations (e.g., rows and columns) to create a matrix that efficiently addresses high-density data storage needs. Memory rows 1200 can also interface with other circuit components and control logic that manage the operation of the memory array, including data management protocols, error correction algorithms, and power optimization strategies.

In some embodiments, memory row 1200 can be fabricated using advanced semiconductor fabrication techniques such as photolithography, etching, deposition, and planarization processes. The materials used for FeFETs, including ferroelectric materials, semiconductor channels, and conductive elements, can be selected based on desired electrical properties such as charge retention, switching speed, and energy efficiency.

As shown in FIG12 , 3D memory row 1200 may include FeFETs, such as 1202, fabricated from a variety of materials that provide the electrical and physical properties necessary to achieve desired functionality. For example, in some embodiments, the channel layer of each FeFET in FeFET 1202 may be constructed from materials such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) such as zinc tin oxide or indium tungsten oxide (IWO). These materials are selected based on their electronic properties, such as carrier mobility and stability.

The ferroelectric material rigidly coupled to the channel layer in each FeFET can include ferroelectric zirconium oxide ( _HfZrO2 ) or other transition metal oxides, calcium titanium, etc. These ferroelectric materials are selected for their ability to maintain a polarization state when an electric field is applied, which is used for the non-volatile memory properties of the FeFET. The thickness, crystal structure, and stoichiometry of the ferroelectric layer can be controlled to achieve the desired threshold voltage, residual polarization, and other electrical parameters for reliable data storage and retrieval.

The drain terminal 1204 and source terminal 1208 of FeFET 1202 are connected to a common select line 1212 and a common bit line 1210, respectively. These common lines can be formed from conductive materials such as tungsten, titanium nitride, or other metals and metal alloys that provide a low-resistance path for electrical signals. The configuration of these terminals and their respective common lines ensures efficient access and control of the FeFET during operation.

Each gate terminal (e.g., gate 1206 of FeFET 1202a) is connected to its respective read/write enable line (e.g., 1214a). The gate terminals help control the state of the FeFET, and the materials chosen for these terminals can include various conductive materials that provide a reliable electrical interface with ferroelectric materials. Read/write enable line 1214 is designed to deliver a suitable voltage level to gate 1206 of FeFET 1202 for switching between states.

Memory row 1200 is designed overall to support a range of operating parameters. In some embodiments, these parameters may include, but are not limited to, an off-state current less than 10^-8 amps/cm3, an on-state current greater than 10^-7 amps/cm3, and a channel mobility maintained despite the presence of the ferroelectric layer. The channel layer thickness can be less than 30 nm to ensure high device density, while the properties of the ferroelectric layer (such as the threshold voltage and residual polarization) are optimized to provide the desired memory functionality.

In some embodiments, FeFET 1202 may include additional materials or dopants to enhance its electrical properties. For example, dopants such as gallium (Ga), indium (In), or zinc (Zn) may be introduced into the channel layer to modulate carrier concentration or adjust the threshold voltage of the FeFET. Similarly, the ferroelectric layer may include dopants such as lumen (La) or niobium (Nb) to adjust its ferroelectric properties.

In other embodiments, 3D memory bank 1200 may be integrated with additional semiconductor devices and structures to form complex memory systems that can provide storage capabilities and support a variety of memory architectures.

13 depicts a three-dimensional (3D) memory row 1300 configured as a 3D-NAND structure, consisting of a vertical stack of ferroelectric field-effect transistors (FeFETs) 1302, each having a source terminal 1304 and a drain terminal 1308. The source 1304 of each FeFET (e.g., 1304a of FeFET 1302a) is coupled to the start of a bit line 1310 or to the drain of the previous FeFET, as exemplified by the source 1304b of FeFET 1302b coupled to the drain 1308a of FeFET 1302a. According to one embodiment of the present invention, each FeFET includes a gate 1306 (such as 1306a of FeFET 1302a) connected to a respective read/write enable line (illustrated by 1314a of FeFET 1302a).

3D memory row 1300 consists of a series of vertically stacked FeFETs (FeFETs), collectively identified as FeFETs 1302. These transistors, including FeFETs 1302a, 1302b, 1302c, and 1302d, are characterized by the incorporation of ferroelectric material within their gate structures. Each FeFET in the series belongs to a memory row and contributes to the device's memory storage capabilities.

In the depicted embodiment, each FeFET, such as FeFET 1302a, includes a source terminal 1304, such as source 1304a, coupled to a bit line 1310. Bit line 1310 serves as a conduit for electrical signals read from and written to the memory cell associated with FeFET 1302a. In the case where FeFET 1302a is not the bottom transistor in the row, its source 1304b can be connected to the drain 1308a of the immediately preceding FeFET (such as FeFET 1302a) to facilitate defining a series connection for a vertical NAND architecture.

Each FeFET within FeFET 1302 is further equipped with a gate terminal 1306, exemplified by gate 1306a of FeFET 1302a. This gate terminal 1306 is coupled to a respective read/write enable line, exemplified by 1314a of FeFET 1302a. Read/write enable line 1314a controls the state of the FeFET, allowing it to conduct or prevent current flow through the device, thereby enabling data to be written or read.

Furthermore, each FeFET of FeFET 1302 also includes a drain terminal 1308 that is typically connected to the source of the subsequent FeFET in the vertical stack, such as drain 1308a of FeFET 1302a. This configuration ensures that the charge stored in the ferroelectric material of the gate can modulate the current flowing from the source to the drain to allow data storage and retrieval.

Memory row 1300 in Figure 13 indicates a memory architecture that can be used in a variety of applications, from portable electronic devices to enterprise-class data storage systems. In some embodiments, the ferroelectric material used in the FeFET can include various compositions, such as einsteinium oxide, zirconium oxide, or any combination thereof, which can be doped with elements such as lumen or yttrium to adjust the ferroelectric properties as desired.

In some variations, 3D memory row 1300 may incorporate additional features that enhance performance, reliability, or manufacturability. For example, FeFET 1302 may include a protective layer to shield the ferroelectric material from environmental factors or process-induced damage. Row 1300 may also be integrated with other circuit elements (such as capacitors or diodes) to facilitate operations such as charge pumping or provide additional functionality within the memory array.

3D memory row 1300 can be fabricated from a variety of materials that impart specific electrical properties to enhance device performance. In some embodiments, the channel layer of each FeFET can be formed from a material such as indium gallium zinc oxide (IGZO). Other materials used for the channel layer can include amorphous oxide semiconductors (AOS), such as zinc tin oxide or aluminum zinc oxide.

The ferroelectric layer within FeFET 1302 can include materials such as ferrozirconium oxide (HfZrO ₂ ). The thickness and material composition of the ferroelectric layer can be controlled by methods such as atomic layer deposition (ALD) to achieve desired threshold voltage, residual polarization, and durability characteristics. In some embodiments, the threshold voltage of the ferroelectric layer can be tuned between -3 volts and +3 volts to facilitate low-voltage operation of the memory device.

The source and drain terminals of the FeFET 1302 can be composed of conductive materials such as tungsten or titanium nitride. These materials can also be selected to optimize the contact resistance with the channel layer to reduce overall power consumption and improve the device's Ion/Ioff ratio.

Additionally, FeFET 1302 can be engineered to exhibit specific electrical parameters. For example, in some embodiments, the channel layer can have a thickness of less than 30 nm. In some embodiments, the channel layer can exhibit a carrier concentration of 10^17/cm³ to 10^20/cm³, which can be tuned by doping with elements such as gallium, indium, or zinc to adjust the electrical properties.

The memory cell formed by the FeFETs 1302 within the 3D memory row 1300 can also target operational parameters such as read and write latency, endurance, and energy consumption. For example, read and write operations can be performed at less than 10 picojoules of energy and in a time frame of less than 20 nanoseconds to contribute to the low-power and high-speed properties of the memory row.

Furthermore, the 3D-NAND configuration of memory row 1300 can be designed to achieve a high off-state resistance to on-state resistance ratio (Roff/Ron), which is important for distinguishing different data states and ensuring reliable data retention. This ratio can be approximately 10^3 or greater, which helps maintain a high signal-to-noise ratio during memory operation.

FeFETs 1302 in memory row 1300 are also designed to maintain a high reliability, with an endurance rating greater than or equal to 10^11 cycles to ensure the life and durability of the memory device. This endurance is complemented by the ferroelectric layer's ability to maintain data retention for at least one minute at room temperature (25°C).

FIG14 illustrates a three-dimensional (3D) memory row configured as a 3D-NAND with an integrated transfer gate according to one embodiment of the present invention. The figure shows a series of ferroelectric field-effect transistors (FeFETs) 1402, each including a source terminal 1404 and a drain terminal 1408, gated by respective gate terminals 1406 and coupled to a read/write enable line 1414. The FeFETs are interconnected to form a vertical memory structure having a transfer gate 1418 linked to a transfer gate line 1416.

14 illustrates a three-dimensional (3D) memory row, designated element 1400, that can be configured as a 3D-NAND structure with an integrated pass gate. This configuration enables enhanced control over individual memory cells within the 3D structure, potentially improving read/write operations and facilitating efficient memory management.

Specifically, 3D memory row 1400 includes a plurality of ferroelectric field-effect transistors (FeFETs), collectively referred to as FeFETs 1402. Each FeFET within row 1402 (e.g., 1402a, 1402b, 1402c, 1402d, etc.) constitutes a memory cell of 3D memory row 1400. Due to the ferroelectric properties of their gate materials, these FeFETs are able to retain data in a non-volatile manner, allowing them to retain data for a period of time without the need for continuous power supply.

Each FeFET in series 1402 includes a source, exemplified by source 1404a of FeFET 1402a. Source 1404 of each FeFET is coupled to a bit line (illustrated as bit line 1410 of FeFET 1402a) or to the drain of the previous FeFET in the series. For example, source 1404b of FeFET 1402b is electrically coupled to drain 1408a of FeFET 1402a. This series connection forms the basis for a daisy-chain configuration in a NAND architecture, allowing sequential access to the FeFET array.

In addition, each FeFET within FeFET 1402 is equipped with a gate terminal, such as gate 1406a of FeFET 1402a. The gates of the FeFETs are connected to their respective read/write enable lines, depicted as element 1414. For example, gate 1406a of FeFET 1402a is affected by read/write enable line 1414a. These enable lines control the application of voltages suitable for reading and writing data.

In addition, each FeFET in the FeFET series 1402 includes a drain, such as drain 1408a of FeFET 1402a. This drain is connected to the source of the next FeFET in the series, thus establishing the continuity of the pillar structure of the 3D memory stack.

In some embodiments, each FeFET of FeFET 1402 incorporates a transfer gate, such as transfer gate 1418a, connected to a transfer gate line (represented by 1416 in the figure). Transfer gate line 1416 provides a conductive path for providing electrical signals to control the transfer gate 1418 of the FeFET. Including a transfer gate in the FeFET can allow for improved isolation between memory cells during operation, thereby reducing interference and potentially enhancing the reliability of data storage and retrieval.

As depicted in Figure 14, 3D memory row 1400 also encompasses a variety of materials and parameters that can be used to optimize its performance in various embodiments. Each FeFET 1402 within the row can be fabricated using a variety of semiconductor materials. For example, the channel layer of a FeFET can be formed from materials such as indium gallium zinc oxide (IGZO).

The ferroelectric layer, a defining characteristic of FeFETs, can be composed of materials such as ferrozirconium oxide ( _HfZrO2 ) or other calcium-titanium materials, known for their residual polarization. This property determines the data retention capability of the FeFET. The threshold voltage of this layer (which influences the energy required to switch the polarization state) is another key parameter that can be adjusted according to the requirements of the specific application. In one embodiment, it ranges from -3 volts to 3 volts.

The source and drain terminals of the FeFETs, comprising elements 1404 and 1408, respectively, can be made of conductive materials such as tungsten or titanium nitride. These materials provide the current path required for switching. The read/write enable line 1414, which controls the gate 1406 of the FeFET, can also be made of similar materials to ensure consistent electrical characteristics throughout the device.

In terms of physical parameters, the channel layer thickness can be less than 30 nm. The electron mobility in these channel layers can be maintained at a predetermined level even when the layer thickness is less than 30 nm.

The transfer gate 1418 may be fabricated using low resistance materials to achieve fast switching times, which is beneficial when memory rows are frequently accessed during operation.

FIG15 illustrates a three-dimensional (3D) memory row 1500 that can be configured as a 3D-NOR or 3D-AND structure with independent read/write enable capabilities according to one embodiment of the present invention. This memory row includes a series of vertically aligned FeFETs 1502, such as FeFETs 1502a, 1502b, 1502c, 1502d, etc., each integrated with a source 1504 (e.g., source 1504a of FeFET 1502a) linked to a respective read enable line 1520 (e.g., read enable line 1520a of FeFET 1502a) and a gate 1506 (e.g., gate 1506a of FeFET 1502a) connected to a corresponding write enable line 1522 (e.g., write enable line 1522a of FeFET 1502a). All FeFETs within a row share a common bit line 1510 connected to their drains 1508 to enable the row to perform coordinated memory operations.

Figure 15 shows a detailed depiction of a three-dimensional (3D) memory row 1500 that can be configured as a 3D-NOR or 3D-AND structure with independent read/write enable functionality. This memory row is an assembly of field-effect transistors with a ferroelectric gate layer, collectively referred to as FeFETs 1502, which are individually identified as, for example, 1502a, 1502b, 1502c, 1502d, etc., each representing a memory cell within the row.

In the illustrated embodiment, each FeFET 1502 includes a source 1504, such as source 1504a corresponding to FeFET 1502a. Source 1504 is designed to be electrically coupled to a respective read enable line 1520, such as read enable line 1520a dedicated to FeFET 1502a. Read enable line 1520 is used to selectively enable FeFET 1502 for a read operation to allow stored data to be read from the memory cell.

In addition, each FeFET 1502 is equipped with a gate 1506, exemplified by gate 1506a of FeFET 1502a. Gate 1506 is connected to a respective write enable line 1522, such as write enable line 1522a, specific to FeFET 1502a. Write enable line 1522 is used to selectively enable FeFET 1502 for a write operation to enable storage of data within the memory cell.

Additionally, each FeFET 1502 includes a drain 1508, such as drain 1508a associated with FeFET 1502a. Drain 1508 is connected to a common bit line 1510. Bit line 1510 acts as a conduit for transferring data to and from the memory cell during read and write operations. The commonality of bit line 1510 across multiple FeFETs 1502 means that data from any active memory cell can be routed through this common path.

In some embodiments of memory row 1500, the configuration of FeFETs 1502 allows high-density memory cells to be stacked vertically in a compact footprint.

The ferroelectric material used in the gate 1506 of the FeFET 1502 can include various compositions, such as a material based on bismuth oxide, which can be deposited using atomic layer deposition techniques. The ferroelectric properties of the material allow for data retention, enabling the memory cell to maintain stored information even when no power is supplied.

The source 1504, gate 1506, and drain 1508 of each FeFET 1502 can be made of materials that provide predetermined electrical performance. These materials can include metals such as tungsten or copper, or metal nitrides such as titanium nitride.

In some embodiments, the read enable line 1520 and the write enable line 1522 can be designed to minimize crosstalk and interference between adjacent lines. In some specific embodiments, a shielding layer or insulating material can be included to further isolate the signal paths.

Furthermore, the described memory bank 1500 may be integrated into a larger semiconductor device, such as a processor or a memory module. It may form part of a system on a chip (SoC) or be included in a multi-chip module (MCM) to facilitate a data storage and retrieval system.

The materials that comprise FeFETs 1502 within memory row 1500 are selected to provide specific electrical and physical properties to optimize the performance of the integrated circuit. For example, the channel layer in each FeFET can be formed from advanced semiconductor materials such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) such as zinc tin oxide or cadmium oxide. These materials are chosen for their excellent electron mobility characteristics and stability.

The ferroelectric layer integrated with FeFET 1502 can be fabricated from a variety of ferroelectric materials exhibiting suitable polarization properties. Materials such as helium zirconium oxide ( _HfZrO2 ) or lead zirconium titanate (PZT) can be used. These materials can be doped with elements such as lumen, yttrium, or other suitable dopants to modify their ferroelectric properties, such as threshold voltage, residual polarization, and crystallization temperature. The thickness and material composition of the ferroelectric layer can be adjusted to achieve desired memory characteristics, such as write endurance and retention time, while ensuring compatibility with the overall semiconductor process and other considerations.

The source terminal 1504, gate terminal 1506, and drain terminal 1508 of the FeFET 1502 can be made of a conductive material such as tungsten, titanium nitride, nickel, or molybdenum. Connection to the read enable line 1520 and the write enable line 1522 can be facilitated through conductive vias or contacts.

Read enable line 1520 and write enable line 1522, along with common bit line 1510, can be patterned using lithography to achieve a predetermined precision and alignment for proper functionality. These lines can be insulated from each other using dielectric materials such as silicon dioxide ( _SiO2 ), _silicon nitride ( _Si3N4 ), or low-k dielectrics to reduce parasitic capacitance and crosstalk.

Each device within memory row 1500 may be fabricated based on factors such as line width, pitch, and aspect ratio to ensure manufacturability, functionality, and/or other goals or characteristics. The materials and processes used to construct memory row 1500 are selected to ensure compatibility with standard semiconductor fabrication techniques (e.g., photolithography, etching, deposition, and annealing) while also enabling material and structural integration.

Fabricating FeFETs 1502 within memory row 1500 may involve deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) to create uniform and/or non-uniform layers.

Figure 16 shows a cross-sectional view of a 3D memory structure (designated 1600) configured as a single-port 3D NAND according to an embodiment of the present invention. The structure includes a first vertical structure 1608a and a second identical vertical structure 1608b, each of which includes a dielectric pillar 1610a, 1610b, a channel pillar 1612a, 1612b disposed around the dielectric pillar, and a ferroelectric pillar 1614a, 1614b disposed around the channel pillar. A series of horizontal gate electrode layers 1606a-1606c are disposed at predetermined distances from each other and adjacent to the ferroelectric pillars along the length of the vertical structure. The assembly further includes a drain select layer 1602 and a source select layer 1604 with respective end dielectric pillars 1618a, 1618b and 1616a, 1616b positioned at the interface with the vertical structure to illustrate a detailed and complex design for high-density data storage.

Thus, Figure 16 provides a cross-sectional view of a three-dimensional (3D) memory structure (designated 1600) configured as a single-port 3D NAND architecture. This structure incorporates a pair of vertical structures 1608a and 1608b, which can be manufactured to be substantially identical, as indicated by their respective subscripts a and b, suggesting the possibility of a modular and scalable memory array design.

Each vertical structure, exemplified by first vertical structure 1608a, includes a dielectric pillar 1610a. Dielectric pillars can take various geometric forms, including cylindrical, substantially cylindrical, or characteristically curved. Alternatively, they can exhibit a tapered shape, with different diameters at each end, implicitly tapering toward the top. Both solid and hollow dielectric pillar configurations are contemplated within the scope of the present invention, providing design flexibility for varying electrical and structural requirements.

A channel pillar 1612a surrounds the dielectric pillar 1610a. The channel pillar 1612a is the path for charge carriers during device operation. The channel pillar is also described as possibly cylindrical, substantially cylindrical, or characteristically curved and/or may exhibit diameter variations along its length similar to the dielectric pillar.

Enclosing channel post 1612a is a ferroelectric post 1614a that extends along the length of the channel post but may be stepped back at the end, meaning that ferroelectric post 1614a does not extend along the entire length of channel post 1612a.

Intersecting the vertical structures are a series of horizontal gate electrode layers 1606a-1606c, which are positioned a predetermined distance from one another. These layers play a role in controlling the operating state of the device by influencing the electric field within the ferroelectric column.

A drain select layer 1602, parallel to the horizontal gate electrode layer 1606, sits atop the 3D memory structure 1600. At the intersection of the drain select layer 1602 and the vertical structures 1608a and 1608b, terminal dielectric pillars 1618a and 1618b are discernible. These terminal dielectric pillars 1618 interface with the channel pillar 1612 and the drain select layer 1602 to help isolate and control charge carriers within the channel pillar. They can contact the ferroelectric layer 1614, encapsulating the channel pillar 1612 at various locations along its length.

Similarly, a source select layer 1604 is located at the bottom of the structure 1600, also parallel to the horizontal gate electrode layer 1606. Corresponding terminal dielectric pillars 1616a and 1616b exist at the interface between the source select layer 1604 and the vertical structure to provide a function similar to the terminal dielectric pillar 1618 near the drain select layer 1602.

The horizontal gate electrode layer 1606 can be constructed from a range of conductive materials (including metals and metal compounds) that offer varying work functions, conductivity, and compatibility with other materials in the structure. Similarly, the ferroelectric pillar 1614 can incorporate a variety of ferroelectric materials, each with its own unique polarization properties, induced field, and dielectric constant that influence the device's memory retention and switching behavior.

The channel pillar 1612 material can be selected based on its electronic properties (such as carrier mobility and bandgap) to achieve the desired on-state and off-state current levels. The dielectric pillar 1610 provides the electrical insulation required to prevent leakage current and ensure proper operation of the device.

The dielectric pillars (such as 1610a for the first vertical structure) can be constructed from a material that provides insulation to mitigate any potential leakage current. Dielectric materials of choice can be _HfO2 or _SiO2 .

The channel pillar (1612a) surrounding the dielectric pillar has a channel material that can be selected from a variety of semiconductor materials that provide a predetermined carrier mobility. For example, indium gallium zinc oxide (IGZO) can be used for its electrical properties. The thickness of the channel layer can vary, with some embodiments contemplating a thickness of less than 30 nm. This thickness is selected to achieve a predetermined electrical performance. The ferroelectric pillar (e.g., 1614a) can include a calcium titanium structure, such as lead zirconate titanate (PZT).

The horizontal gate electrode layers denoted by 1606a to 1606c are composed of a conductive material (such as tungsten or titanium nitride, which can be selected based on their electrical behavior) that facilitates the application of an electric field to the ferroelectric pillars. The choice of gate electrode material also takes into account factors such as work function, thermal stability, and ease of integration with existing semiconductor processes.

Drain and source select layers (1602 and 1604, respectively) are incorporated to enable addressing of individual memory banks within the array. The materials used for these layers are selected based on their conductivity and compatibility with the channel and ferroelectric materials. The design of these layers may also be incorporated to minimize parasitic capacitance and ensure fast data access.

End dielectric posts (such as 1618a and 1616a) provide electrical insulation at the ends of the channel posts where the ferroelectric material does not extend.

The disclosed embodiment of 3D memory structure 1600 outlines an assembly capable of providing data storage. The design allows for variations in structural dimensions, such as the diameter of cylindrical pillars, which can be uniform or tapered. Additionally, options for solid or hollow configurations are available.

FIG17 illustrates a 3D memory structure as a dual-port 3D NAND configuration according to an embodiment of the present invention. The three-dimensional (3D) memory structure depicted in FIG17 (referred to as 3D memory structure 1700) illustrates a dual-port 3D NAND configuration to provide memory functionality. This structure is characterized by two primary vertical formations, designated as a first vertical structure 1708a and a second vertical structure 1708b, which may be identical or nearly identical (as indicated by the subscripts "a" and "b").

The first vertical structure 1708a includes a hollow or solid tapered transfer gate electrode post 1718a that is substantially cylindrical in shape. The transfer gate electrode post 1718a can be made of titanium nitride and can have a larger diameter at the bottom than at the top.

A dielectric pillar 1710a, which may be made of bismuth oxide, surrounds the transfer gate electrode pillar 1718a. Dielectric pillar 1710a is also substantially cylindrical with a slightly tapered shape, with a slightly larger diameter at the top. Dielectric pillar 1710a provides electrical isolation between the transfer gate electrode and subsequent layers.

A cylindrical channel pillar 1712a, which can be made of IGZO semiconductor material, is disposed around dielectric pillar 1710a. Channel pillar 1712a has a curve along its length and a uniform diameter throughout. The thickness of the channel pillar can be less than 30 nm.

A PZT ferroelectric post 1714a surrounds the channel post 1712a. The PZT ferroelectric post 1714a covers most of the length of the channel post 1712a but steps back at the end so that a portion of the channel post 1712a is uncovered. The ferroelectric post 1714a is substantially cylindrical and contains lead, zirconium, and titanium as key elements.

Vertical structures 1708a and 1708b pass through several horizontal gate electrode layers 1706a, 1706b, and 1706c, which can be made of tungsten and are positioned at regular intervals to form an interconnected grid layout. These layers affect the electric field within the ferroelectric pillar 1714a during memory operation.

At the top of memory structure 1700, a drain select layer 1702 (e.g., titanium nitride) runs parallel to horizontal gate electrode layer 1706. At the intersection of drain select layer 1702 and vertical structures 1708a and 1708b, terminal dielectric pillars 1718a and 1718b are visible. These terminal pillars (e.g., made of _HfO2 ) contact ferroelectric pillar 1714a on one end and surround the uncovered portion of channel pillar 1712a to provide insulation.

Similarly, at the bottom of structure 1700, a source select layer 1704 (e.g., made of tungsten) interfaces with the vertical structure, also parallel to electrode layer 1706. At these intersections, terminal dielectric pillars 1716a and 1716b can be observed to enclose the open ends of channel pillars 1712a and 1712b.

Within the hollow regions of the transfer gate electrode pillars 1718a and 1718b at the ends, a thin dielectric horizontal layer 1720a and 1720b may be placed near the bottom terminal (e.g., HfO ₂ ). These layers seal the bottom open ends of the vertical hollow voids.

FIG18 illustrates a 3D memory structure 1800 that can be configured as a 3D NOR vertical transistor memory array. The 3D memory structure 1800 includes a first vertical structure 1808a and an identical (or substantially identical) second vertical structure 1808b that are adjacent to each other.

The first vertical structure 1808a includes a vertical plug 1802a that provides an electrical connection to the lower portion of the 3D memory structure. Vertical plug 1802a can have a uniform diameter along its entire length or can have a larger diameter at its lower end than at its upper end. In various embodiments, plug 1802a can be fabricated as a solid pillar or a hollow pillar.

A source electrode column 1804a and a drain electrode column 1816a are disposed adjacent to the vertical plug column 1802a. The source electrode column 1804a and the drain electrode column 1816a provide electrical connections to the source and drain nodes of the vertical transistor formed along the vertical structure 1808a. The source electrode pillar 1804a and the drain electrode pillar 1816a can be made of various conductive materials, including (but not limited to) tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, eum, eum nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

A channel column 1812a surrounds the vertical plug column 1802a, the source electrode column 1804a, and the drain electrode column 1816a. The channel column 1812a provides a semiconductor channel region for the vertical transistor along the first vertical structure 1808a. The channel pillar 1812a may be formed of materials including, but not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), helium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon, crystalline germanium, arsenic Gallium arsenide (GaAs), indium phosphide (InP), indium sulfide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT, polythiophene, PPV, graphene, carbon nanotubes (CNT), methylammonium lead halide, cesium lead halide, lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), and other semiconductor materials.

A ferroelectric pillar 1814a surrounds the channel pillar 1812a. The ferroelectric pillar 1814a provides a gate dielectric for the vertical transistor along the first vertical structure 1808a. The ferroelectric pillar 1814a may be made of ferroelectric materials, including but not limited to calcium titanium oxide, lead zirconium titanate (PZT), barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), bismuth ferrite (BiFeO ₃ ), potassium niobate (KNbO ₃ ), lithium niobate (LiNbO ₃ ), lithium niobate (LiTaO ₃ ), sodium bismuth titanate (Na _0.5 Bi _0.5 TiO ₃ ), bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ), bismuth zinc niobate (Bi(Zn _1/2 Ti _1/2 )O ₃ ), bismuth vanadium titanate (BiLaTiO _{3 ).} ), bismuth nickel titanate ( _BiNiTiO3 ), PMN-PT, PLZT, neodymium-doped bismuth titanate ₍ Bi4 _{- xNdxTi3O12} ), bismuth-based oxides such as bismuth oxide ( _HfO2 ) and bismuth oxide-doped bismuth oxide, tungsten bronze structural materials, barium strontium niobate (BSN), lead barium niobate (PBN), potassium niobate (KTN), bismuth titanate ( _Bi4Ti3O12 ) _, bismuth strontium niobate (SBT), calcium bismuth niobate (CBN), organic ferroelectrics such as PVDF, TrFE and _P (VDF-TrFE) copolymers, Aurivilis phase oxides, such as YMnO ₃ rare earth manganese ore, nickel-modified PLZT, nickel manganese oxide (NiMnO ₃ ), relaxor ferroelectrics such as PMN, PST, and PIN, multiferroic materials such as TbMnO ₃ and EuTiO ₃ , SbSI, GeTe, SnTe, PZT thin films, SBT thin films, HfO ₂ -based thin films, layered superlattices, and PbTiO ₃ /SrTiO ₃ .

The 3D memory structure 1800 further includes a plurality of horizontal gate electrode layers 1806, including layers 1806a, 1806b, 1806c, etc. The horizontal gate electrode layers 1806 are regularly spaced along the vertical structure 1808 and provide gate electrodes for the vertical transistors. The gate electrode layer 1806 can be formed of materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, cobium, cobium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AlCu and TiW, and conductive polymers.

Each of the horizontal gate electrode layers 1806 may be surrounded by an oxide/nitride/oxide (ONO) stack 1810 (such as 1810a surrounding gate electrode layer 1806a) to provide insulation between the gate electrodes.

The second vertical structure 1808b in the 3D memory structure 1800 is configured identically to the first vertical structure 1808a. The two vertical structures 1808a and 1808b are arranged horizontally adjacent to each other at a spacing that allows for integration of the gate electrode layer 1806 and the ONO stack 1810. Together, the first and second vertical structures 1808a and 1808b, along with the horizontal gate electrode layer 1806, form a 3D NOR memory architecture.

FIG19 illustrates an embodiment of a planar FeFET 1900. FeFET 1900 includes a substrate 1910 upon which various layers and components are formed. Substrate 1910 can be composed of silicon or other suitable semiconductor materials. A layer of TiN 1912 is disposed on top of substrate 1910. TiN layer 1912 can serve as an electrode and can be deposited by sputtering or other suitable deposition techniques.

A layer of HZO 1908 is disposed on top of substrate 1910 and TiN layer 1912. HZO 1908 comprises einsteinium, zirconium, and oxygen and can exhibit ferroelectric properties. HZO 1908 can be deposited by ALD, CVD, PVD, or other suitable deposition methods and can have a thickness ranging from 5 nm to 50 nm. As a ferroelectric layer, HZO 1908 enables non-volatile data storage in FeFET 1900.

A layer of IWO 1906 is conformally deposited on top of HZO 1908. IWO 1906 includes indium, tungsten, and oxygen. It can be deposited by sputtering or other suitable techniques and can have a thickness within a variety of ranges. IWO layer 1906 serves as a control oxide layer in FeFET 1900.

A drain contact 1904 and a source contact 1914 are formed on top of the IWO layer 1906. The drain contact 1904 and the source contact 1914 may comprise a metal such as copper, aluminum, or alloys thereof and may be deposited by PVD, CVD, or other suitable methods. The drain contact 1904 and the source contact 1914 allow electrical connection to the FeFET 1900. They may have a thickness in the range of 50 nm to 500 nm.

In operation, a voltage applied to drain 1904, source 1914, and TiN gate contact 1912 controls the polarization of the iron electrode in HZO layer 1908. This polarization state can be used to store information in a non-volatile manner, enabling memory storage capabilities. IWO layer 1906 helps improve the switching speed and endurance of FeFET 1900. Overall, the layered structure shown in FIG19 makes FeFET 1900 suitable for non-volatile memory applications.

Figure 20 shows the transfer characteristics of a ferroelectric FET (FeFET) device, plotting the gate voltage (V_GS) on the x-axis and the resulting drain current (I_D) on the y-axis. Figure 20 illustrates the characteristics of a FeFET disclosed herein. The x-axis spans from -1 V to 1 V, while the y-axis displays current values on a logarithmic scale from 10^-12 A/μm to 10^-4 A/μm.

Two different curves show the drain current behavior of the FeFET under clockwise (CW) and counterclockwise (MW) polarization. The blue curve (CW) starts at approximately 10^-11 A/μm at -1 V and exhibits a sharp increase near -1 V, reaching just over 10^-5 A/μm at 1 V. This demonstrates the rapid increase in drain current exhibited by the FeFET under forward bias in the clockwise polarization state.

In contrast, the red curve (MW) starts at approximately 10^-11 A/μm at -1 V and gradually increases as it approaches 0 V. At approximately 1 V, it then closely follows the blue curve above 1 V. This indicates fairly draining current behavior under reverse bias conditions, independent of the polarization state.

Note that in the negative voltage range around -1 V, the gap between the red and blue curves spans several orders of magnitude. This substantial difference in the off-state current highlights the non-volatile memory effect achievable with FeFETs, which depends on the polarization orientation of the FeFET. This large memory window is clearly marked in the green box labeled "Large Memory Window" in the upper left.

Additional key details provided include the FeFET device dimensions, specifying a width/length ratio of 1 μm/50 nm. The drain voltage is also fixed at 0.05 V. Specific points along the curves are annotated, such as "MW @5e-7 A/μm = 1 V" on the red MW curve, which indicates the 1 V memory window at a drain current of 5×10^-7 A/μm. Another marked point is "CW @-0.5 V = 1×10^6" on the blue CW curve, which highlights a clockwise current value of 1×10-6 A/μm at a gate voltage of -0.5 V.

In summary, Figure 20 provides a comprehensive depiction of the bidirectional transfer characteristics of the FeFET device, highlighting the large memory window achievable through polarization switching and providing detailed voltage, current, and dimensional specifications to fully convey the measurement conditions and transistor performance. The paired curves actually compare clockwise and counterclockwise operating modes over the full gate voltage range.

Those skilled in the art may envision various substitutions and modifications without departing from the present invention. Therefore, the present invention is intended to cover all such substitutions, modifications, and variations. In addition, although several embodiments of the present invention have been shown in the drawings and/or discussed herein, it is not intended that the present invention be limited thereto, as the scope of the present invention is intended to be as broad as the art allows and the specification is to be interpreted so. Therefore, the above description should not be interpreted as limiting, but merely as an example of a particular embodiment. And those skilled in the art will envision other modifications within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that are not materially different from the elements, steps, methods, and techniques described above and/or in the appended claims are also intended to be within the scope of the present invention.

The embodiments shown in the drawings are intended only to demonstrate certain embodiments of the present invention. The drawings are illustrative and non-restrictive. For illustrative purposes, the size of some elements in the drawings may be exaggerated and not drawn to scale. Furthermore, depending on the context, elements with the same reference numerals in the drawings may represent the same or similar elements.

When the term "comprising" is used in this description and the scope of the patent application, it does not exclude other elements or steps. When the indefinite or definite article (for example, "a" or "the") is used when referring to a singular noun, this includes the plural of the noun unless otherwise expressly stated. Therefore, the term "comprising" should not be interpreted as being limited to the items listed thereafter; it does not exclude other elements or steps. Therefore, the scope of the expression "a device comprising items A and B" should not be limited to the device consisting of only components A and B. This expression means that, with respect to the present invention, the only relevant components of the device are A and B.

Furthermore, whether used in the embodiments or the claims, the terms "first," "second," "third," and the like are provided to distinguish similar elements and do not necessarily describe a sequential or chronological order. It should be understood that the terms so used are interchangeable where appropriate (unless otherwise clearly disclosed) and that the embodiments of the present invention described herein are capable of operating in sequences and/or configurations other than those described or illustrated herein.

Each of the features and embodiments described herein and any combination thereof may be considered to be encompassed by the present invention. The present invention therefore relates to the following non-limiting numbered aspects:

1. An integrated circuit comprising: a plurality of micro-storage banks, each of the plurality of micro-storage banks being disposed in a spaced relationship relative to one another and adjacent to a first surface, the plurality of micro-storage banks including a first micro-storage bank; and a plurality of bonding regions, each of the plurality of bonding regions being disposed on the first surface and adjacent to a respective one of the plurality of micro-storage banks, the plurality of bonding regions including a first bonding region in operative communication with the first micro-storage bank.

2. The integrated circuit of aspect 1, wherein the first bonding region comprises a plurality of bondings each in operative communication with the first micro-storage bank.

3. The integrated circuit of aspect 2, wherein the plurality of joints are bumpless joints.

4. An integrated circuit as in any preceding aspect, wherein the first micro-storage bank has a capacity between 4 kilobytes and 1 million bytes.

5. The integrated circuit of any preceding aspect, wherein the first micro-storage bank has a capacity between 4 kilobytes and 128 kilobytes.

6. An integrated circuit as in any preceding aspect, wherein the first micro-storage bank has a capacity between 4 kilobytes and 16 kilobytes.

7. The integrated circuit of any of the preceding aspects, wherein the first micro-repository has dimensions of less than 256 microns x less than 256 microns and extends a predetermined distance in a vertical dimension.

8. The integrated circuit of any of the preceding aspects, wherein the first micro-repository has dimensions of 32 microns x 32 microns and extends a predetermined distance in a vertical dimension.

9. The integrated circuit of aspect 8, wherein the vertical dimension corresponds to at least 8 memory layers.

10. An integrated circuit as in any of the preceding aspects, wherein the bit density of the first micro-storage bank is greater than 0.2 gigabits per square millimeter for each layer of the micro-storage bank.

11. The integrated circuit of any of the preceding aspects, wherein the first micro-repository is disposed on a back-end-of-line portion of a die.

12. The integrated circuit of aspect 1, further comprising an SRAM memory bank disposed adjacent to the first micro memory bank.

13. The integrated circuit of aspect 12, wherein the first bonding region is in operative communication with the SRAM memory bank.

14. The integrated circuit of aspect 12, further comprising a second bonding region disposed on the first surface and in operative communication with the SRAM memory bank.

15. The integrated circuit of aspect 12, wherein the plurality of micro-banks are formed on a first die and the SRAM bank is formed on a second die, wherein the first and second dies are bonded together.

16. The integrated circuit of any of the preceding aspects, further comprising a DRAM memory bank adjacent to the micro memory bank.

17. The integrated circuit of aspect 16, wherein the first bonding region is in operative communication with the DRAM bank.

18. The integrated circuit of aspect 16, further comprising a second bonding region disposed on the first surface and in operative communication with the DRAM bank.

19. The integrated circuit of aspect 16, wherein the plurality of micro-banks are formed on a first die and the DRAM bank is formed on a third die, wherein the first and third dies are rigidly fixed together.

20. The integrated circuit of aspect 1, further comprising a read address register operatively coupled to the first bonding region, the read address register configured to store a read address and transfer it to the first micro-bank.

21. The integrated circuit of aspect 1 or 20, further comprising a read data register operatively coupled to the first micro-storage bank and configured to receive and store read data from the first micro-storage bank.

22. The integrated circuit of aspect 21, wherein the read data register is operatively coupled to the first bonding region to transfer read data to the first bonding region.

23. The integrated circuit of aspect 21, wherein the read data register is operatively coupled to a second bonding region of the plurality of bonding regions to transfer read data to the second bonding region.

24. The integrated circuit of any one of aspects 21 to 23, further comprising a second read data register in operative communication with the read data register and configured to receive and store read data from the read data register.

25. The integrated circuit of aspect 24 depending upon aspect 22, wherein the second read data register is disposed on a die having a second side, wherein the second side includes a read data bonding region operatively coupled to the first bonding region of the first surface.

26. The integrated circuit of aspect 24 as dependent upon aspect 23, wherein the second read data register is disposed on a die having a second side, wherein the second side includes a read data bonding region operatively coupled to the second bonding region of the first surface.

27. The integrated circuit of any of the preceding aspects, further comprising a second read data register disposed on a die different from a die having the plurality of micro-banks.

28. The integrated circuit of any of the preceding aspects, further comprising a second read address register disposed on a die different from a die having the plurality of micro-banks.

29. The integrated circuit of any one of aspects 1 or 20, further comprising a second read address register.

30. The integrated circuit of aspect 29, further comprising a second bonding region on a second surface.

31. The integrated circuit of aspect 30, wherein the second read address register is configured to receive and store the read address and the read address is transmitted to the read address register via the second surface.

32. The integrated circuit of aspect 31, wherein the second surface and the first surface are bonded together.

33. The integrated circuit of any of the preceding aspects, further comprising a through-silicon via (TSV) operatively coupled at a first end of the TSV to a third surface located on an opposite side of the first surface.

34. The integrated circuit of aspect 33, further comprising an interconnect coupled to the first surface and a second end of the through-silicon via.

35. The integrated circuit of aspect 1, further comprising a second micro-storage bank in operative communication with the first bonding region.

36. The integrated circuit of aspect 35, further comprising a multiplexer operatively coupled to the first micro-storage bank to receive a first read data from the first micro-storage bank, the multiplexer operatively coupled to the second micro-storage bank to receive a second read data from the second micro-storage bank, wherein the multiplexer is configured to select between the first read data and the second read data for output.

37. The integrated circuit of aspect 36, further comprising a counter in operative communication with the multiplexer and configured to serially read out the first read data and the second read data.

38. The integrated circuit of any one of aspects 36 or 37, further comprising a read data register configured to receive the first read data or the second read data for storage therein.

39. The integrated circuit of aspect 38, further comprising a second bonding region on the first surface, wherein the read data register is coupled to the second bonding region to transfer the stored first read data or the second read data from the multiplexer to the second bonding region.

40. The integrated circuit of any of the preceding aspects, further comprising an assembly comprising a first die having the plurality of micro-banks.

41. The integrated circuit of any of the preceding aspects, further comprising an assembly comprising a first die having the plurality of micro-storage banks, the plurality of micro-storage banks comprising the first micro-storage bank and a second micro-storage bank.

42. The integrated circuit of any one of aspects 40 or 41, further comprising a second die having a read address register and a read data register, wherein the first die is bonded to the second die.

43. The integrated circuit of aspect 42, wherein the first die includes a second bonding region on the first surface, wherein the second die includes a third bonding region and a fourth bonding region, wherein the first bonding region of the first die is coupled to the third bonding region of the second die and the second bonding region of the first die is coupled to the fourth bonding region of the second die.

44. The integrated circuit of aspect 43, wherein the read address register is operatively coupled to the third bonding region to transfer read data to the third bonding region.

45. The integrated circuit of any one of aspects 43 or 42, wherein the read data register is operatively coupled to the fourth bonding region of the second die to receive read data from the fourth bonding region.

46. The integrated circuit of any one of aspects 41 to 45, wherein the first die includes a second read address register configured to receive and store a read address, the second read address register configured to transmit a read address to the first micro-storage bank and the second micro-storage bank.

47. The integrated circuit of aspect 45, wherein the first die further comprises a multiplexer configured to select between an output of the first micro-bank and an output of the second micro-bank.

48. The integrated circuit of aspect 47, further comprising a second bonding area on a second surface of the first die, wherein an interconnect connects the second bonding area to an input of the multiplexer, wherein the multiplexer is configured to select between the output of the first micro-storage bank, the output of the second micro-storage bank, and communication from the bonding area.

49. The integrated circuit of any one of aspects 47 or 48, further comprising a phase counter configured to control the multiplexer.

50. The integrated circuit of one of aspects 47 or 48, further comprising a third address register configured to receive and store an output of the multiplexer.

51. The integrated circuit of aspect 49, wherein the third address register is operatively coupled to a second bonding region of the first die.

52. The integrated circuit of any one of aspects 42 to 50, further comprising a TSV coupled to the read address register and a second surface of the die.

53. The integrated circuit of any one of aspects 42 to 51, further comprising a second TSV coupled to a second bonding region of the first die and a second read data register on the second surface.

54. The integrated circuit of aspect 1, wherein a multiplexer is configured to select between one of the plurality of micro-banks.

55. The integrated circuit of aspect 54, wherein a phase counter is configured to control the selection of the multiplexer.

56. The integrated circuit of aspect 1, further comprising a through-silicon via (TSV) operatively coupled to the first surface and a second surface of a die having the plurality of micro-banks.

57. The integrated circuit of aspect 1, wherein a through-silicon via is configured to facilitate communication between a second die coupled to a first die having the plurality of micro-banks.

58. The integrated circuit of aspect 1, wherein the first micro-bank comprises at least one row of 3D-NOR formed by a plurality of transistors, wherein each transistor comprises a gate coupled to a read-write enable line, a source coupled to a bit line, and a drain coupled to a select line.

59. The integrated circuit of aspect 1, wherein the first micro-bank comprises a row of 3D-NAND transistors formed by a plurality of transistors, each transistor having a gate coupled to a read/write enable line, a source coupled to a bit line, and a drain coupled to a source of a second transistor.

60. The integrated circuit of aspect 1, wherein the first micro-bank comprises a row of 3D-NAND transistors having a transfer gate formed of a plurality of transistors, each transistor having a gate coupled to a read/write enable line, a source coupled to a bit line, a drain coupled to a source of a second transistor, and a transfer gate coupled to all of the plurality of transistors.

61. The integrated circuit of aspect 1, wherein the first micro-bank comprises a column of 3D-NOR with independent read and write enable formed by a plurality of transistors, wherein each transistor includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line.

62. The integrated circuit of any of the preceding aspects, wherein the plurality of micro-banks include a thermal management layer configured to dissipate heat generated by the micro-banks during operation.

63. The integrated circuit of aspect 62, wherein the thermal management layer comprises a material having high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene.

64. The integrated circuit of any of the preceding aspects, further comprising a hardware-based encryption module operatively coupled to at least one microstorage to secure data written to or read from the microstorage.

65. The integrated circuit of any of the preceding aspects, further comprising a power management circuit configured to adjust voltage and current supplied to the plurality of micro-storage banks based on an operating state of the plurality of micro-storage banks.

66. The integrated circuit of aspect 65, wherein the power management circuit includes a low power mode that reduces power supply to the micro-banks during inactive periods.

67. The integrated circuit of any of the preceding aspects, further comprising a signal conditioning circuit operatively coupled to the plurality of micro-storage banks to enhance signal integrity of data transmission.

68. The integrated circuit of aspect 67, wherein the signal conditioning circuit comprises a filter, an amplifier, or an error correction encoder.

69. The integrated circuit of any of the preceding aspects, further comprising a diagnostic module configured to monitor the health and performance of the micro-storages and report metrics to an external controller.

70. The integrated circuit of aspect 69, wherein the diagnostic module is capable of performing self-tests on the micro-storages and generating an alarm when a fault is detected.

71. An integrated circuit as in any of the preceding aspects, wherein each micro-storage bank includes a built-in self-repair mechanism capable of isolating and bypassing faulty memory cells.

72. The integrated circuit of aspect 71, wherein the self-repair mechanism utilizes redundancy in the form of spare memory cells that can be dynamically allocated to replace the failed cells.

73. An integrated circuit as in any preceding aspect, wherein the micro-storage banks are arranged in a matrix configuration to enable parallel processing and data retrieval.

74. The integrated circuit of aspect 73, wherein the matrix configuration includes row and column decoders for facilitating access to individual micro-banks.

75. The integrated circuit of any of the preceding aspects, further comprising a flexible substrate to enable the integrated circuit to conform to non-planar surfaces.

76. The integrated circuit of aspect 75, wherein the flexible substrate comprises a material selected from the group consisting of polyimide, PEEK, liquid crystal polymer, and flexible glass.

77. The integrated circuit of any of the preceding aspects, wherein the first micro-bank is configured to operate as a cache memory for a processor.

78. The integrated circuit of aspect 77, wherein the cache memory operates in one of the following modes: write-through, write-back, write-bypass, or a combination thereof.

79. An integrated circuit as in any of the preceding aspects, wherein the first micro-bank is part of a redundant array of independent memory elements used for error correction and data recovery.

80. The integrated circuit of any of the preceding aspects, wherein the first micro-storage bank comprises a crossbar switch architecture for facilitating data routing between memory cells.

81. The integrated circuit of aspect 80, wherein the vertical and horizontal switch architecture enables uninterrupted data transmission within the integrated circuit.

82. An integrated circuit as in any of the preceding aspects, wherein the first micro-storage comprises a dedicated read peripheral device.

83. An integrated circuit as in any of the preceding aspects, wherein the first micro-storage comprises a dedicated read port.

84. An integrated circuit as in any of the preceding aspects, wherein the first micro-storage comprises a dedicated write peripheral device.

85. An integrated circuit as in any of the preceding aspects, wherein the first micro-storage comprises a dedicated write port.

86. A method comprising: forming an integrated circuit as in one of aspects 1 to 85.

87. A method of using an integrated circuit, the method comprising: forming an integrated circuit as in one of aspects 1 to 85.

100: Integrated Circuit (IC) 102: Shared Write Port 104: Write Peripheral 106: Module Group 108: Module 110: Module 112: Module 114: Module 116: Read Peripheral 118: Read Peripheral 120: Read Peripheral 122: Read Peripheral 124: Read Port 126: Read Port 128: Read Port 130: Read Port 132: Interlock 200: Assembly 202: Write Peripheral 204: Silicon Substrate 206: Second Layer 208: Top Layer 212: Integrated circuit 218: Read address 220: Read data 222: Shared write port 226: Second device 228: Surface 230: Chiplet 232: First module 234: Second module 236: Module group 300: Block diagram 302: Module group 304: Memory module 306: Memory module 308: Memory module 310: Read data address space 312: Read data address space 314: Read data address space 316: Write address space 402: Module group 404: Module 406: Module 408: Module 410: Read peripherals 411: Write peripherals 412: Read peripherals 414: Read peripherals 500: Integrated circuit 502: Module 506: Silicon substrate 508: Second layer 510: Shared write peripherals 512: Write address bus 516: Write data bus 518: Surface 520: Dedicated read peripherals 522: Memory bit cells 524: Read address bus 526: Read data bus 600: Assembly 602: Silicon substrate 604: Network on a Chip (NOC) 606: Processing Component 608: Second Layer 610: System on a Chip (SOC) 700: Assembly 702: Input Dynamic Random Access Memory (DRAM) Memory 702a: DRAM Module 702b: DRAM Module 702c: DRAM Module 704: Output DRAM Memory 704a: DRAM Memory Module 704b: DRAM Memory Module 704c: DRAM Memory Module 706: Processing Component Array 706a,a through 706n,n: Processing Components 707: First Semiconductor Device 708: Microstorage Bank Array 708a,a through 708n,a: Microstorage 709: Second semiconductor device 710: Layer 710a through 710d: Layer 800: Assembly 802: Semiconductor device 804: Semiconductor device 806: Semiconductor device 808: Semiconductor device 810: Semiconductor device 812: Semiconductor device 814: Semiconductor device 816: Storage 816a,a through 816n,n: Storage 900: Assembly 902: Interconnect 906: Semiconductor device 908: Bumpless bonding 910: Bumpless bonding 912: Interconnect 914: Semiconductor device 916: Through-Silicon Via (TSV) 918: No Bump Bond 920: No Bump Bond 922: Read Data Register (RDR) 924: Read Address Register (RAR) Input Interconnect 926: Read Address Register (RAR) 928: Interconnect 930: No Bump Bond 932: No Bump Bond 936: Micro-storage Library 938: Read Address Register (RAR) 940: Interconnect 942: Read Data Register (RDR) 944: Through-Silicon Via (TSV) 946: Interconnect 950: Read Data Register (RDR) Output Interconnect 1000: Semiconductor Assembly 1004: Interconnect 1006: Semiconductor device 1008: Bumpless bond 1010: Bumpless bond 1012: Interconnect 1014: Semiconductor device 1016: Through-silicon via (TSV) 1018: Bumpless bond 1022: Read data register 1024: Read address register input interconnect 1026: Read address register 1028: Interconnect 1030: Bumpless bond 1032: Bumpless bond 1034: Interconnect 1036: Microstorage 1038: Read address register 1040: Interconnect 1042: Read Data Register 1044: TSV 1046: Interconnect 1048: Interconnect 1050: Read Data Register Output Interconnect 1056: Interconnect 1058: Microstorage Bank 1060: Multiplexer 1062: Counter 1100: Assembly 1102: Phase Counter 1104: Read Data Register 1106: Top Semiconductor Device 1108: Interconnect 1110: Phase Counter 1112: Read Data Register 1114: Multiplexer 1116: Middle Semiconductor Device 1118: Microstorage Bank 1120: Interconnect 1122: Bottom semiconductor device 1124: Read data register 1126: Read address register 1128: Bumpless bond 1129: Bumpless bond 1130: Interconnect 1132: Microstorage bank 1134: Interconnect 1136: TSVs 1138: Microstorage bank 1140: Interconnect 1142: Read address register 1144: Interconnect 1146: Read address register 1148: Interconnect 1150: Multiplexer 1152: TSVs 1154: Read data register 1156: Interconnect 1158: Bumpless Bond 1159: Bumpless Bond 1160: Bumpless Bond 1161: Bumpless Bond 1162: Bumpless Bond 1163: Bumpless Bond 1164: Microstorage 1166: Interconnect 1168: Interconnect 1170: Interconnect 1172: Interconnect 1174: Interconnect 1176: Interconnect 1200: Three-Dimensional (3D) Memory Bank 1202: Ferroelectric Field-Effect Transistor (FeFET) 1202a: FeFET 1202b: FeFET 1202c: FeFET 1202d: FeFET 1204: Drain terminal 1204a: Drain terminal 1206: Gate terminal 1208: Source terminal 1208a: Source terminal 1210: Common bit line 1212: Common select line 1214: Read/write enable line 1214a: Read/write enable line 1300: Three-dimensional (3D) memory row 1302a: FeFET 1302b: FeFET 1302c: FeFET 1302d: FeFET 1304: Source terminal 1306: Gate terminal 1308: Drain terminal 1310: Bit line 1314a: Read/write enable line 1400: 3D memory row 1402a: FeFET 1402b: FeFET 1402c: FeFET 1402d: FeFET 1404: Source terminal 1404a: Source 1406: Gate terminal 1406a: Gate 1408: Drain 1408a: Drain 1410: Bit line 1414: Read/write enable line 1416: Transfer gate line 1418: Transfer gate 1500: Three-dimensional (3D) memory row 1502: FeFET 1502a: FeFET 1502b: FeFET 1502c: FeFET 1502d: FeFET 1504: Source terminal 1504a: Source terminal 1506: Gate terminal 1506a: Gate terminal 1508: Drain terminal 1508a: Drain terminal 1510: Common bit line 1520: Read enable line 1520a: Read enable line 1522: Write enable line 1522a: Write enable line 1600: 3D memory structure 1602: Drain select layer 1604: Source select layer 1606a to 1606c: Horizontal gate electrode layer 1608a: First vertical structure 1608b: Second vertical structure 1610a: Dielectric pillar 1610b: Dielectric pillar 1612a: Channel pillar 1612b: Channel pillar 1614a: Ferroelectric pillar 1614b: Ferroelectric pillar 1616a: Terminal dielectric pillar 1616b: Terminal dielectric pillar 1618a: Terminal dielectric pillar 1618b: Terminal dielectric pillar 1700: 3D memory structure 1702: Drain select layer 1704: Source select layer 1706: Horizontal gate electrode layer 1706a: Horizontal gate electrode layer 1706b: Horizontal gate electrode layer 1706c: Horizontal gate electrode layer 1708a: First vertical structure 1708b: Second vertical structure 1710a: Dielectric pillar 1712a: Channel pillar 1712b: Channel pillar 1714a: Ferroelectric pillar 1716a: Terminal dielectric pillar 1716b: Terminal dielectric pillar 1718a: Transfer gate electrode pillar 1718b: Transfer gate electrode pillar 1720a: Thin dielectric horizontal layer 1720b: Thin dielectric horizontal layer 1800: 3D memory structure 1802a: Vertical plug pillar 1804a: Source electrode pillar 1806: Horizontal gate electrode layer 1806a: Horizontal gate electrode layer 1806b: Horizontal gate electrode layer 1806c: Horizontal gate electrode layer 1808a: First vertical structure 1808b: Second vertical structure 1810: Oxide/nitride/oxide (ONO) stack 1810a: ONO stack 1812a: Channel pillar 1814a: Ferroelectric pillar 1816a: Drain electrode pillar 1900: Planar FeFET 1904: Drain contact 1906: Indium tungsten oxide (IWO) 1908: HZO 1910: Substrate 1912: TiN layer 1914: Source contact

These and other aspects will become more apparent from the following detailed description of various embodiments of the present invention with reference to the accompanying drawings, in which:

FIG1 is a block diagram of an integrated circuit that may be part of a semiconductor device such as a small chip according to an embodiment of the present invention;

FIG2 shows a perspective view of an assembly having the integrated circuit of FIG1 implemented on a semiconductor device according to an embodiment of the present invention, the semiconductor device being electrically connected to another device to form the assembly;

FIG3 shows a block diagram illustrating the memory address space of the integrated circuit of FIG1 according to an embodiment of the present invention;

FIG4 shows a block diagram illustrating a memory address space having a signal interface of the integrated circuit of FIG1 according to an embodiment of the present invention;

FIG5 shows a diagram of an integrated circuit that may be part of a semiconductor device such as a small chip according to an embodiment of the present invention;

FIG6 shows a perspective view of an assembly having the integrated circuit of FIG1 implemented on a semiconductor device electrically connected to a single-chip system according to an embodiment of the present invention;

FIG7 shows a perspective view of an assembly having a semiconductor device including a processing element array and a second semiconductor device having a micro-bank array;

FIG8 shows an assembly of a semiconductor device including several memory types according to an embodiment of the present invention;

FIG9 shows an assembly of a semiconductor device including a semiconductor device having a single-chip system and another semiconductor having a micro-storage device disposed on top according to an embodiment of the present invention;

FIG10 shows a semiconductor assembly incorporating a daisy-chain configuration of micro-banks operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval according to an embodiment of the present invention.

FIG11 shows a semiconductor assembly incorporating a daisy-chain configuration of a microstorage bank operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval in a plurality of semiconductor devices according to an embodiment of the present invention;

FIG12 illustrates a three-dimensional (3D) memory row configured as a 3D-NOR or 3D-AND structure having a series of ferroelectric field effect transistors (FeFETs) with interconnected drain terminals linked to a common select line and individual gate terminals connected to respective read/write enable lines, all coupled to a common bit line, according to one embodiment of the present invention;

FIG13 depicts a three-dimensional (3D) memory row configured as a 3D-NAND structure consisting of a vertical stack of ferroelectric field effect transistors (FeFETs) according to one embodiment of the present invention;

FIG14 depicts a three-dimensional (3D) memory row configured as a 3D-NAND with an integrated pass gate according to one embodiment of the present invention;

FIG15 illustrates a three-dimensional (3D) memory row 1500 configured as a 3D-NOR or 3D-AND structure with independent read/write enable capabilities according to an embodiment of the present invention;

FIG16 shows a cross-sectional view of a 3D memory structure configured as a single-port 3D NAND according to an embodiment of the present invention;

FIG17 shows a cross-sectional view of a 3D memory structure configured as a dual-port 3D NAND according to an embodiment of the present invention;

FIG18 illustrates a 3D memory structure configurable as a 3D NOR vertical transistor memory array according to an embodiment of the present invention;

FIG19 shows a planar FeFET according to an embodiment of the present invention; and

FIG20 shows the electrical characteristics of an embodiment of a FeFET according to an embodiment of the present invention.

700: Assembly

702a: Dynamic random access memory (DRAM) module

702b: DRAM module

702c: DRAM module

704a: DRAM memory module

704b: DRAM memory module

704c: DRAM memory module

706a,a to 706n,n: Processing elements

707: First semiconductor device

708a,a to 708n,a: Microstorage

709: Second semiconductor device

710a to 710d: Layers

Claims (20)

An integrated circuit includes: a plurality of micro-storage banks, each of the plurality of micro-storage banks disposed in a spaced relationship relative to one another and adjacent to a first surface, the plurality of micro-storage banks including a first micro-storage bank; and a plurality of bonding regions, each of the plurality of bonding regions disposed on the first surface and adjacent to a respective one of the plurality of micro-storage banks, the plurality of bonding regions including a first bonding region in operative communication with the first micro-storage bank. The integrated circuit of claim 1, wherein the first bonding region comprises a plurality of bondings each in operative communication with the first micro-storage bank. The integrated circuit of claim 2, wherein the plurality of joints are bumpless joints. The integrated circuit of claim 1, further comprising an SRAM memory bank disposed adjacent to the first micro memory bank. The integrated circuit of claim 4, wherein the first bonding region is in operative communication with the SRAM memory bank. The integrated circuit of claim 4, further comprising a second bonding region disposed on the first surface and in operative communication with the SRAM memory bank. The integrated circuit of claim 4, wherein the plurality of micro-banks are formed on a first die and the SRAM bank is formed on a second die, wherein the first and second dies are bonded together. The integrated circuit of claim 1, further comprising a read address register operatively coupled to the first bonding region, the read address register being configured to store a read address and transmit it to the first micro-storage bank. The integrated circuit of claim 1, further comprising a read data register operatively coupled to the first micro storage and configured to receive and store read data from the first micro storage. The integrated circuit of claim 9, wherein the read data register is operatively coupled to the first bonding region to transfer read data to the first bonding region. The integrated circuit of claim 9, wherein the read data register is operatively coupled to a second bonding region of the plurality of bonding regions to transfer read data to the second bonding region. The integrated circuit of claim 1 further comprising a second read address register. The integrated circuit of claim 12, further comprising a second bonding area on a second surface. The integrated circuit of claim 13, wherein the second read address register is configured to receive and store the read address and transmit the read address to the read address register via the second surface. The integrated circuit of claim 14, wherein the second surface and the first surface are bonded together. The integrated circuit of claim 1, further comprising a second micro-storage bank in operative communication with the first bonding area. The integrated circuit of claim 16 further includes a multiplexer operatively coupled to the first micro-storage bank to receive a first read data from the first micro-storage bank, the multiplexer operatively coupled to the second micro-storage bank to receive a second read data from the second micro-storage bank, wherein the multiplexer is configured to select between the first read data and the second read data for output. The integrated circuit of claim 17, further comprising a counter in operative communication with the multiplexer and configured to serially read out the first read data and the second read data. The integrated circuit of claim 17, further comprising a read data register configured to receive the first read data or the second read data for storage therein. The integrated circuit of claim 19 further comprises a second bonding region on the first surface, wherein the read data register is coupled to the second bonding region to transfer the stored first read data or the second read data from the multiplexer to the second bonding region.