TW202516525A - Test method and test system - Google Patents

Abstract

A test method for a memory is disclosed. The test method includes the following steps: transmitting an input voltage to several memory columns, in which during a first time interval, the input voltage rises from the first voltage value to a second voltage value and then drops to the first voltage value, and during a second time interval, the input voltage drops from the second voltage value to the first voltage value and then rises to the second voltage value; obtaining a first address setup time, a first address hold time, a second address setup time and a second address hold time of the memory columns respectively; and determining a performance of the memory columns respectively according to the respective memory columns, the first address setup time, the first address hold time, the second address setup time and the second address hold time.

Description

Test methods and test systems

The embodiments described in this disclosure are related to a testing method and a testing device, and in particular to a testing method and a testing device for memory performance.

A data storage device is an electronic device used to write and/or read electronic data. A data storage device can be implemented as a volatile memory, such as random-access memory (RAM), which traditionally requires power to maintain its stored information; or a non-volatile memory, such as read-only memory (ROM), which can maintain its stored information even when it is not powered. RAM can be implemented as dynamic random-access memory (DRAM), static random-access memory (SRAM), and/or non-volatile random-access memory (NVRAM), commonly referred to as flash memory configurations. Electronic data can be written to and/or read from an array of memory cells that are accessible via various control lines.

Various methods for testing memory performance have been proposed. Among them, the current test for the total setup time (TIS) and total hold time (TIH) of the memory is to input a low voltage value to the memory array. When the memory array performs an action, the voltage value of the memory array increases from a low voltage value to a high voltage value. However, when the memory array does not perform an action, the voltage value of the memory array is maintained at a low voltage. In this way, it is impossible to obtain the address setup time and address hold time of the memory array when the memory array is not in action, and it is also impossible to evaluate the performance of the memory array.

Some embodiments of the present disclosure are related to a testing method applicable to a memory. The memory includes a plurality of memory rows, wherein the testing method includes the following steps: transmitting an input voltage having a first voltage value to a plurality of memory pins of the memory row, wherein the input voltage increases from the first voltage value to a second voltage value in a first time interval, and then decreases to the first voltage value, and obtaining a first address establishment time and a first address retention time corresponding to the first time interval for each of the memory rows; adjusting the first time interval length of the first time interval to obtain a first minimum address establishment time and a first minimum address retention time corresponding to the first time interval for each of the plurality of memory rows; transmitting an input voltage having a second voltage value to The memory pins of the memory row, wherein the input voltage drops from the second voltage value to the first voltage value and then rises to the second voltage value in the second time interval, and obtains the second address establishment time and the second address retention time corresponding to the second time interval of each memory row; adjusts the second time interval length of the second time interval to obtain the second minimum address establishment time and the second minimum address retention time corresponding to the second time interval of multiple memory rows; and determines the performance of each memory row according to the first address establishment time, first address retention time, second address establishment time and second address retention time of each memory row.

Some embodiments of the present disclosure are related to a test system. The test system includes a memory and a test device. The memory includes a plurality of memory rows. The test device includes a voltage output circuit and a performance judgment circuit. The voltage output circuit is used to transmit an input voltage having a first voltage value to multiple memory pins of multiple memory rows of the memory in a first time period, and to transmit an input voltage having a second voltage value to multiple memory pins of multiple memory rows of the memory in a second time period, wherein the input voltage rises from the first voltage value to the second voltage value and then drops to the first voltage value in the first time period, and drops from the second voltage value to the first voltage value and then rises to the second voltage value in the second time period. The performance determination circuit is coupled to the voltage output circuit, and is used to obtain the first address establishment time and the first address retention time of each of the multiple memory columns corresponding to the first time period, and the second address establishment time and the second address retention time of each of the multiple memory columns corresponding to the second time period, and is used to determine the performance of each of the multiple memory columns based on the first address establishment time, the first address retention time, the second address establishment time and the second address retention time of each of the multiple memory columns.

As used herein, the term “coupled” may also refer to “electrically coupled”, and the term “connected” may also refer to “electrically connected”. “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a test device 100 according to some embodiments of the present disclosure. The test device 100 includes a voltage output circuit 130 and a performance judgment circuit 170. In terms of connection, the voltage output circuit 130 and the performance judgment circuit 170 are coupled. In some embodiments, the test device 100 further includes a clock output circuit 110. The clock output circuit 110 is coupled to the voltage output circuit 130 and the performance judgment circuit 170. The test device 100 shown in FIG. 1 is used for illustration purposes, and the implementation method of the present case is not limited thereto.

In operation, the clock output circuit 110 is used to output a clock signal CLK to a plurality of memory rows MA1 to MAn of the memory 900. The voltage output circuit 130 is used to transmit an input voltage VIN (which may be a working voltage or a test voltage) to the memory 900.

In detail, as shown in FIG. 1 , the memory 900 includes a plurality of memory rows MA1 to MAn. The plurality of memory rows MA1 to MAn each include a memory pin. The memory row MA1 includes a memory pin P1, the memory row MA2 includes a memory pin P2, the memory row MA3 includes a memory pin P3, and so on. The voltage output circuit 130 is used to transmit an input voltage VIN to the plurality of memory pins P1 to Pn of the plurality of memory rows MA1 to MAn of the memory 900.

The detailed operation of the test device 100 shown in FIG. 1 will be described below together with FIG. 2 .

Please refer to FIG. 2. FIG. 2 is a flow chart of a test method 200 according to some embodiments of the present disclosure. The test method 200 can be applied to the test device 100 shown in FIG. 1. The test method 200 includes steps S210 to S250. Please refer to FIG. 1 and FIG. 2 together.

In step S210, an input voltage having a first voltage value is transmitted to multiple memory pins of multiple memory rows, wherein the input voltage increases from the first voltage value to the second voltage value in a first time period and then decreases to the first voltage value, and a first address establishment time and a first address retention time corresponding to the first time period of each of the multiple memory rows are obtained.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a voltage value change of an input voltage according to some embodiments of the present disclosure. As shown in FIG. 3, in the time interval T1, the clock output circuit 110 in FIG. 1 outputs the clock signal CLK to the memory rows MA1 to MAn. The voltage output circuit 130 in FIG. 1 transmits the input voltage VIN of the voltage value VL to the memory pins P1 to Pn of the memory rows MA1 to MAn.

As shown in FIG. 3 , during a time period TP1 in the time period T1 , the input voltage VIN increases from the voltage value VL to the voltage value VH, and then decreases from the voltage value VH to the voltage value VL.

Specifically, the input voltage VIN starts to increase from the voltage value VL at the time point TA1 and reaches the voltage value VH at the time point TB1. The input voltage VIN starts to decrease from the voltage value VH at the time point TD1 and reaches the voltage value VL at the time point TE1.

In normal operation, when one of the memory arrays MA1 to MAn receives the input voltage VIN as shown in FIG3, the memory array performs an action. For example, if the memory array MA1 receives the input voltage VIN as shown in FIG3, the memory array MA1 performs an action.

In some embodiments, the performance determination circuit 170 obtains the voltage value of the input voltage VIN of the memory columns MA1 to MAn, and obtains the address setup time and address retention time of each of the memory columns MA1 to MAn according to the voltage value of the input voltage VIN of the memory columns MA1 to MAn and the clock signal CLK.

Please refer to Figure 3. Time point TA1 is the time point when the voltage value of the input voltage VIN starts to increase from the voltage value VL to the voltage value VH, time point TC1 is the time point when the voltage value of the clock signal CLK rises to 1/2VDD (or the time point of 1/4 clock cycle), and time point TD1 is the time point when the voltage value of the input voltage VIN starts to decrease from the voltage value VH to the voltage value VL.

The performance determination circuit 170 obtains the length of the time interval between the time point TA1 and the time point TC1 as the address setup time TIS1 and obtains the length of the time interval between the time point TC1 and the time point TD1 as the address retention time TIH1 according to the above-mentioned time points TA1, TC1 and TD1.

Accordingly, the performance determination circuit 170 obtains the address setup time TIS1 and the address retention time TIH1 of each of the memory columns MA1 to MAn according to the voltage value of the input voltage VIN of each of the memory columns MA1 to MAn.

In some embodiments, step S210 further includes adjusting the time interval length of the time interval TP1 by the voltage output circuit 130 in Figure 1, and the performance judgment circuit 170 judges whether multiple memory columns MA1 to MAn operate according to the input voltage VIN during the time interval TP1, and obtains the first minimum address establishment time TIS1min (not shown) and the first minimum address retention time TIH1min (not shown) corresponding to the time interval TP1 of the multiple memory columns MA1 to MAn.

For example, in some embodiments, the voltage output circuit 130 gradually shortens the time interval length of the time interval TP1. That is, the input voltage VIN will rise from the voltage value VL to the voltage value VH in a shorter time interval, and then drop from the voltage value VH to the voltage value VL. When the time interval length of the time interval TP1 is too short, the plurality of memory arrays MA1 to MAn cannot operate normally according to the voltage value change of the input voltage VIN.

In some embodiments, the performance determination circuit 170 obtains the shortest time interval length of the time interval TP1 during which each of the plurality of memory arrays MA1 to MAn can change normally according to the voltage value of the input voltage VIN. That is, when the time interval TP1 is shortened to less than the shortest time interval length, the plurality of memory arrays MA1 to MAn cannot operate normally.

In some embodiments, the performance determination circuit 170 obtains the minimum address setup time TIS1min and the minimum address retention time TIH1min corresponding to the shortest time interval length of the time interval TP1 according to the shortest time interval length of the time interval TP1.

The method of obtaining the minimum address setup time TIS1min and the minimum address retention time TIH1min is similar to the method of obtaining the address setup time TIS1 and the address retention time TIH1, and is not repeated here.

In step S230, an input voltage having a second voltage value is transmitted to multiple memory pins of multiple memory rows, wherein the input voltage decreases from the second voltage value to the first voltage value and then increases to the second voltage value during a second time period, and a second address establishment time and a second address retention time corresponding to the second time period of each of the multiple memory rows are obtained.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a voltage value change of an input voltage according to some embodiments of the present disclosure. As shown in FIG. 4, in the time period T2, the clock output circuit 110 in FIG. 1 outputs the clock signal CLK to the memory rows MA1 to MAn. The voltage output circuit 130 in FIG. 1 transmits the input voltage VIN having a voltage value VH to the memory pins P1 to Pn of the memory rows MA1 to MAn.

As shown in FIG. 4 , during a time period TP2 in the time period T2 , the voltage value of the input voltage VIN decreases from the voltage value VH to the voltage value VL, and then increases from the voltage value VL to the voltage value VH.

Specifically, the input voltage VIN starts to decrease from the voltage value VH at the time point TA2 and reaches the voltage value VL at the time point TB2. The input voltage VIN starts to increase from the voltage value VL at the time point TD2 and reaches the voltage value VH at the time point TE2.

In normal operation, when one of the memory arrays MA1 to MAn receives the input voltage VIN as shown in FIG4, the memory array does not perform any operation. For example, if the memory array MA1 receives the input voltage VIN as shown in FIG4, the memory array MA1 does not perform any operation.

In some embodiments, the performance determination circuit 170 obtains the voltage value of the input voltage VIN of the memory columns MA1 to MAn, and obtains the address setup time and address retention time of each of the memory columns MA1 to MAn according to the voltage value of the input voltage VIN of the memory columns MA1 to MAn and the clock signal CLK.

Please refer to Figure 4. Time point TA2 is the time point when the voltage value of the input voltage VIN starts to drop from the voltage value VH to the voltage value VL, time point TC2 is the time point when the voltage value of the clock signal CLK rises to 1/2VDD (or the time point of 1/4 clock cycle), and time point TD2 is the time point when the voltage value of the input voltage VIN starts to rise from the voltage value VL to the voltage value VH.

The performance determination circuit 170 obtains the length of the time interval between the time point TA2 and the time point TC2 as the address setup time TIS2 and obtains the length of the time interval between the time point TC2 and the time point TD2 as the address retention time TIH2 according to the above-mentioned time points TA2, TC2 and TD2.

Accordingly, the performance determination circuit 170 obtains the address setup time TIS2 and the address retention time TIH2 of each of the memory columns MA1 to MAn according to the voltage value of the input voltage VIN of each of the memory columns MA1 to MAn.

In some embodiments, step S230 further includes adjusting the time interval length of the time interval TP2 by the voltage output circuit 130 in Figure 1, and the performance judgment circuit 170 determines whether the multiple memory columns MA1 to MAn do not operate according to the input voltage VIN during the time interval TP2, and obtains the second minimum address establishment time TIS2min (not shown) and the second minimum address retention time TIH2min (not shown) corresponding to the time interval TP2 of the multiple memory columns MA1 to MAn.

For example, in some embodiments, the voltage output circuit 130 gradually shortens the time interval length of the time interval TP2. That is, the input voltage VIN will drop from the voltage value VH to the voltage value VL in a shorter time interval, and then rise from the voltage value VL to the voltage value VH. When the time interval length of the time interval TP2 is too short, the plurality of memory arrays MA1 to MAn cannot operate normally according to the voltage value change of the input voltage VIN.

In some embodiments, the performance determination circuit 170 obtains the shortest time interval length of the time interval TP2 during which each of the plurality of memory arrays MA1 to MAn can change normally according to the voltage value of the input voltage VIN. That is, when the time interval TP2 is shortened to less than the shortest time interval length, the plurality of memory arrays MA1 to MAn cannot operate normally.

In some embodiments, the performance determination circuit 170 obtains the minimum address setup time and the minimum address retention time corresponding to the shortest time interval length of the time interval TP2 according to the shortest time interval length of the time interval TP2.

The method of obtaining the minimum address setup time TIS2min and the minimum address retention time TIH2min is similar to the method of obtaining the address setup time TIS2 and the address retention time TIH2, and is not repeated here.

In step S250, the performance of each memory row is determined according to the first address setup time TIS1, the first address retention time TIH1, the second address setup time TIS2 and the second address retention time TIH2 of each memory row.

In some embodiments, step S250 is performed by the performance determination circuit 170 as shown in FIG1. In some embodiments, the performance determination circuit 170 is used to determine the performance of each memory row according to whether the address setup time TIS1, the address retention time TIH1, the address setup time TIS2 and the address retention time TIH2 are greater than the time threshold.

In some embodiments, the time threshold is 1/4 of the clock period of the clock signal.

When the address setup time TIS1, the address retention time TIH1, the address setup time TIS2, and the address retention time TIH2 are greater than the time threshold, the performance determination circuit 170 determines that the corresponding memory is out of spec, and the performance is poor.

When more of the address setup time TIS1, the address retention time TIH1, the address setup time TIS2, and the address retention time TIH2 is greater than the time threshold, it is determined that the performance of the corresponding memory row is worse.

For example, if one of the address setup time TIS1, address retention time TIH1, address setup time TIS2, and address retention time TIH2 of the memory row MA1 is greater than the time threshold, the performance determination circuit 170 determines that the performance of the memory row MA1 is poor. If four of the address setup time TIS1, address retention time TIH1, address setup time TIS2, and address retention time TIH2 of the memory row MA1 are greater than the time threshold, the performance determination circuit 170 determines that the performance of the memory row MA1 is the worst.

In some embodiments, step S250 further includes determining the performance of each memory row according to whether the minimum address setup time TIS1min, the minimum address retention time TIH1min, the minimum address setup time TIS2min, and the minimum address retention time TIH2min are greater than a time threshold.

When more of the minimum address setup time TIS1min, the minimum address retention time TIH1min, and the minimum address setup time TIS2min is greater than the time threshold, it is determined that the performance of the corresponding memory row is worse.

In some embodiments, during the test, the time period T1 as shown in FIG. 3 and the time period T2 as shown in FIG. 4 are performed alternately.

In some embodiments, the voltage value VH of the input voltage VIN is 1.2V, and the voltage value VL of the input voltage VIN is 0V.

In summary, the embodiment of the present case provides a testing method and a testing device, by alternately providing low voltage input and high voltage input to the memory, so as to obtain test parameters such as address setup time and address retention time under action and no action. In this way, the performance of the memory row can be understood more accurately.

In addition, the above examples include exemplary steps in sequence, but these steps do not have to be executed in the order shown. Executing these steps in different orders is within the scope of the present disclosure. Within the spirit and scope of the embodiments of the present disclosure, these steps can be added, replaced, changed in order and/or omitted as appropriate.

Although the present disclosure has been disclosed in the above implementation form, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

100: Test device 110: Clock output circuit 130: Voltage output circuit 170: Performance judgment circuit 900: Memory CLK: Clock signal VIN: Input voltage P1, P2, P3, Pn: Memory pins MA1, MA2, MA3, MAn: Memory array 200: Test method S210, S230, S250: Steps T1, T2, TP1, TP2: Time interval TIS1, TIS2: Address establishment time TIH1, TIH2: Address retention time TA1, TB1, TC1, TD1, TE1: Time point TA2, TB2, TC2, TD2, TE2: Time point VDD: voltage value VH: voltage value VL: voltage value

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a schematic diagram of a test device according to some embodiments of the present disclosure; FIG. 2 is a flow chart of a test method according to some embodiments of the present disclosure; FIG. 3 is a schematic diagram of a voltage value change of an input voltage according to some embodiments of the present disclosure; and FIG. 4 is a schematic diagram of a voltage value change of an input voltage according to some embodiments of the present disclosure.

200:Test method

S210, S230, S250: Steps

Claims (9)

A testing method is applicable to a memory, wherein the memory includes a plurality of memory rows, wherein the testing method includes: Transmitting an input voltage having a first voltage value to a plurality of memory pins of the memory rows, wherein the input voltage rises from the first voltage value to a second voltage value in a first time interval, and then drops to the first voltage value, and obtaining a first address establishment time and a first address retention time corresponding to the first time interval for each of the memory rows; Adjusting a first time interval length of the first time interval to obtain a first minimum address establishment time and a first minimum address retention time corresponding to the first time interval for each of the memory rows; Transmitting the input voltage having the second voltage value to the memory pins of the memory rows, wherein the input voltage decreases from the second voltage value to the first voltage value and then increases to the second voltage value in a second time interval, and obtaining a second address establishment time and a second address retention time corresponding to the second time interval for each of the memory rows; Adjusting a second time interval length of the second time interval to obtain a second minimum address establishment time and a second minimum address retention time corresponding to the second time interval for each of the memory rows; and Determining a performance of each of the memory rows according to the first address establishment time, the first address retention time, the second address establishment time and the second address retention time of each of the memory rows. The test method as described in claim 1 further includes: Determining whether the memory cells are activated according to the input voltage during the first time period. The test method as described in claim 1 further includes: Determining whether the memory cells are inactive in the second time period according to the input voltage. The testing method as described in claim 3 further comprises: Determining the performance of each of the memory rows based on the first minimum address setup time, the first minimum address retention time, the second minimum address setup time, and the second minimum address retention time. A test system, comprising: a memory, comprising a plurality of memory rows; and a test device, comprising: A voltage output circuit for transmitting an input voltage having a first voltage value to a plurality of memory pins of the memory rows of the memory in a first time period, and for transmitting the input voltage having a second voltage value to the memory pins of the memory rows of the memory in a second time period, wherein the input voltage rises from the first voltage value to the second voltage value and then drops to the first voltage value in the first time period, and drops from the second voltage value to the first voltage value and then rises to the second voltage value in the second time period; and A performance determination circuit is coupled to the voltage output circuit, and is used to obtain a first address establishment time and a first address retention time corresponding to the first time interval of each of the memory rows, and a second address establishment time and a second address retention time corresponding to the second time interval of each of the memory rows, and is used to determine a performance of each of the memory rows according to the first address establishment time, the first address retention time, the second address establishment time, and the second address retention time of each of the memory rows. A test system as described in claim 5, wherein the performance determination circuit is further used to determine whether the memory cells act according to the input voltage during the first time period. A test system as described in claim 5, wherein the performance determination circuit is further used to determine whether the memory cells are inactive during the second time period according to the input voltage. A test system as described in claim 5, wherein the voltage output circuit is further used to adjust a first time interval length of the first time interval, and to adjust a second time interval length of the second time interval, wherein the performance judgment circuit is further used to obtain a first minimum address establishment time and a first minimum address retention time corresponding to the first time interval for each of the memory rows, and to obtain a second minimum address establishment time and a second minimum address retention time corresponding to the second time interval for each of the memory rows. A test system as described in claim 8, wherein the performance determination circuit is further used to determine the performance of each of the memory rows based on the first minimum address setup time, the first minimum address retention time, the second minimum address setup time and the second minimum address retention time.

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