TW202509533A - Methods for ag mirror encapsulation - Google Patents

Abstract

The present disclosure provides a method including depositing a mirror over a waveguide, the waveguide having an input coupler and an output coupler. An encapsulation layer is deposited over the mirror. A resist is formed over the input coupler, exposing a residual encapsulation portion of the encapsulation layer over the non-input coupler area. The residual encapsulation portion of the encapsulation layer is removed, exposing a residual mirror portion of the mirror over the non-input coupler area. The residual mirror portion of the mirror of the input coupler is removed, exposing the non-input area of the waveguide. The resist over the input coupler is removed, in which the waveguide has the mirror only over the input coupler and the encapsulation layer is only over the mirror.

Description

Method for packaging AG mirror

Embodiments of the present disclosure generally relate to waveguides for augmented, virtual, and mixed reality.

Waveguides can be used to manipulate the propagation of light using structures of the waveguide formed on a substrate. The waveguide comprises an arrangement of structures having in-plane dimensions less than half the design wavelength of the light. The structures have submicron critical dimensions, such as nano-sized dimensions, to alter light propagation by manipulating photons, thereby causing local phase discontinuities (i.e., abrupt changes in phase over distances less than the wavelength of light). Metal coatings can be placed over the structures, where the metal coating acts as a mirror to guide the light and improve device efficiency. However, metal coatings often corrode in the ambient atmosphere due to reactions with oxygen- and/or sulfur-containing gases.

Therefore, there is a need for an improved method of forming waveguides.

The present disclosure provides methods. The methods include depositing a mirror over a waveguide, the waveguide having an input coupler and an output coupler. A packaging layer is deposited over the mirror. A barrier is formed over the input coupler, thereby exposing a remaining packaging portion of the packaging layer over a non-input coupler area. Removing the remaining packaging portion of the packaging layer, thereby exposing a remaining mirror portion of the mirror over a non-input coupler area. Removing the remaining mirror portion of the mirror of the input coupler, thereby exposing a non-input area of the waveguide. Removing the barrier over the input coupler, wherein the waveguide has a mirror only over the input coupler and the packaging layer is only over the mirror.

The present disclosure also provides methods. The methods include depositing a mirror on a waveguide, wherein the waveguide has an input coupler and an output coupler. Forming a first resistor on the input coupler, thereby exposing a residual mirror portion of the mirror above a non-input coupler area. Exposing a residual mirror portion of the mirror above a non-input coupler area. Removing the first resistor. Depositing an encapsulation layer on the mirror and the non-input coupler area. Forming a second resistor on the mirror, wherein the residual encapsulation portion of the encapsulation layer is exposed above the non-input coupler area. Removing the residual encapsulation portion, wherein the non-input coupler area of the waveguide is exposed. The second resistor is removed, wherein the waveguide has a mirror only over the input coupler and the encapsulation layer is only over the mirror, or over the mirror and an outer portion of the grating surrounding the input coupler.

The present disclosure also provides methods. The methods include depositing a mirror comprising silver or aluminum on a waveguide. The waveguide has an input coupler and an output coupler. Depositing a packaging layer comprising chromium nitride or silicon nitride on the mirror. Forming a resistor on the input coupler. Exposing a residual packaging portion of the packaging layer above a non-input coupler area. Removing the residual packaging portion of the packaging layer and the residual mirror portion of the mirror above the non-input coupler area. Removing the resistor on the input coupler.

Embodiments of the present disclosure are generally directed to methods of making an input coupler for a waveguide for augmented reality and virtual reality devices. The methods described herein provide a waveguide having a mirror only over the input coupler, wherein an encapsulation layer is only over the mirror or over an outer portion of the mirror and a grating surrounding the input coupler, as shown in FIG. 1. The mirror layer only over the input coupler with the encapsulation layer provides a barrier to the ingress of oxygen, sulfur, and moisture. The encapsulation layer protects the mirror from corrosion in the ambient atmosphere.

The encapsulation layer of the present disclosure does not require an electron beam PVD deposition process. Instead, other deposition processes may be utilized, such as PVD or printing methods, such as screen printing or inkjet printing, where such PVD or printing methods reduce costs and improve process flow. The deposition process described herein allows the encapsulation layer to be deposited without including the optical performance of the AR/VR device. In summary, the present disclosure provides a method for forming an input coupler having reflectivity and preventing oxidation or other chemical reactions.

The waveguide 100 includes a substrate 101. The substrate 101 can be selected to transmit light at an operating wavelength. Without limitation, in some embodiments, the substrate 101 is configured so that the substrate 101 transmits greater than or equal to about 50%, 60%, 70%, 80%, 90%, 95%, 99% of the UV region of the spectrum. As long as the substrate 101 can sufficiently transmit light at the operating wavelength, the substrate 101 can be formed of any suitable material and can serve as sufficient support for the layout of at least the waveguide structure 106 and the encapsulation layer 104. In some embodiments that can be combined with other embodiments described herein, the material of the substrate 101 has a relatively low refractive index compared to the refractive index of the material used in each of the waveguide structures 106. Substrate selection may include substrates of any suitable material, including but not limited to semiconductors, doped semiconductors, amorphous dielectrics, non-amorphous dielectrics, crystalline dielectrics, silicon oxides, polymers, and combinations thereof. In some embodiments, which may be combined with other embodiments described herein, substrate 101 includes a transparent material. Substrate 101 is transparent, wherein the absorption coefficient is less than 0.001. Examples may include but are not limited to oxides, sulfides, phosphides, tellurides, and combinations thereof. For example, substrate 101 includes but is not limited to silicon (Si), silicon dioxide (SiO ₂ ), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), sapphire, glass, or combinations thereof.

The waveguide 100 includes an input coupler 102. The input coupler 102 includes a first arrangement of a waveguide structure 106. The waveguide structure 106 may be any suitable shape to transmit and/or guide incident light to the substrate 101. For example, but not limited to, the waveguide structure 106 may have a square or rectangular cross-section. As another non-limiting example, the waveguide structure 106 may have a cross-section having a circular, triangular, elliptical, regular polygon, irregular polygon, and/or irregularly shaped cross-section. The cross-section of the waveguide structure 106 on the substrate 101 may be different.

The waveguide structure 106 may include materials including but not limited to titanium dioxide (TiO ₂ ), zinc oxide (ZnO), tin dioxide (SnO ₂ ), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), cadmium stannate (tin oxide) (CTO), zinc stannate (tin oxide) (SnZnO ₃ ), and silicon-containing materials. The silicon-containing material may include at least one of materials including silicon nitride (Si ₃ N ₄ ) or amorphous silicon (a-Si). The waveguide structure 106 may have a refractive index of about 1.8 or greater and an absorption coefficient of less than 0.001.

Mirror 103 is disposed on input coupler 102 of waveguide structure 106, wherein mirror 103 is not disposed on output coupler 105. Mirror 103 is a coating capable of reflecting one or more wavelengths of light entering substrate 101 and proceeding toward input coupler 102. Mirror 103 is not disposed on output coupler 105. Mirror 103 can be any suitable material capable of reflecting more than 90% of light, such as reflecting about 90%, about 91%, about 92%, about 93%, about 94%, about 95%, about 96%, about 97%, about 98%, about 99%, or about 100% of light. For example, but not limited to, mirror 103 can be silver, aluminum, gold, a nanocrystalline oxide such as titanium dioxide, zinc oxide, magnesium oxide, aluminum oxide, or the like. For example, the mirror 103 may be silver. For example, the mirror 103 may be aluminum.

The input coupler 102 includes a packaging layer 104 disposed on the mirror 103, wherein the packaging layer 104 is disposed on the mirror 103, and the mirror 103 is disposed only on the input coupler 102. In some embodiments that can be combined with other embodiments, the packaging layer 104 is disposed only on the top side of the mirror 103. In other embodiments that can be combined with other embodiments, the packaging layer 104 is disposed on the top side of the mirror 103 and one or more side walls.

The encapsulation layer 104 contains one or more materials for encapsulating or protecting the underlying layers, i.e., the mirror 103 and the substrate 101 of the waveguide 100. For example, the encapsulation layer 104 may include chromium, silicon nitride, silicon oxide (e.g., silicon dioxide), aluminum oxide, magnesium oxide, dopants thereof, or any combination thereof. The encapsulation layer 104 may be formed using one or more vapor deposition processes that do not utilize plasma (e.g., polymer printing, such as inkjet printing or screen printing). The encapsulation layer 104 may be formed using one or more vapor deposition processes that utilize plasma (e.g., PVD or sputtering processes), a furnace CVD (FCVD) process, a PE-CVD process, a PE-ALD process, or other plasma processes.

In one or more examples, encapsulation layer 104 may be deposited by a PVD process that includes generating ozone or oxygen plasma while depositing encapsulation layer 104. For example, silicon oxide may be deposited in a magnetron sputtering PVD chamber using a silicon target and reactive deposition with a plasma containing argon and oxygen (Ar/O ₂ ). In other examples, encapsulation layer 104 is deposited on mirror 103 by inkjet printing with one or more polymers or metals.

The encapsulation layer 104 has a thickness of about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, or about 50 nm to about 55 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about 100 nm, about 120 nm, about 135 nm, about 150 nm, about 180 nm, about 200 nm, or more. For example, the encapsulation layer 104 has a diameter of about 10 nm to about 200 nm, about 10 nm to about 180 nm, about 10 nm to about 150 nm, about 10 nm to about 120 nm, about 10 nm to about 100 nm, about 10 nm to about 80 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, about 10 nm to about 40 nm, about 10 nm to about 20 nm, about 15 nm to about 50 nm, about 20 nm to about 200 nm, about 20 nm to about 180 nm, about 20 nm to about 150 nm, about 20 nm to about 120 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 60 nm, about 20 nm to about 50 nm, about 20 nm to about 40 nm, about 20 nm to about 30 nm, about 40 nm to about 200 nm, about 40 nm to about In some embodiments, the encapsulation layer 104 has a refractive index of about 1.0 to about 1.5, such as about 1.0 to about 1.4, about 1.1 to about 1.4, about 1.2 to about 1.4, or about 1.2 to about 1.3.

The waveguide 100 includes an output coupler 105. The output coupler 105 includes a second arrangement of waveguide structures 106 as described herein. The second arrangement of waveguide structures 106 guides refracted or reflected light within the substrate 101 as it exits the substrate 101 and/or the waveguide 100. The waveguide structure 106 may have a cross-section that is square, rectangular, circular, triangular, elliptical, a regular polygon, an irregular polygon, and/or an irregular shape. The second arrangement of waveguide structures 106 has a depth and critical dimensions as described herein. In some embodiments, a medium fills one or more gaps between the second arrangement of waveguide structures 106 of the output coupler 105. In some embodiments, the medium includes a refractive index of approximately 1. For example, the medium filling one or more gaps between the second arrangement of waveguide structures 106 of the output coupler can be air. The second arrangement of waveguide structures 106 has a structural refractive index as described herein.

The plurality of waveguide structures 106 include, but are not limited to, one or more of materials containing silicon (e.g., amorphous silicon), silicon carbide (SiC), silicon oxycarbide (SiOC), titanium dioxide (TiO ₂ ), silicon dioxide (SiO ₂ ), vanadium (IV) oxide (VO _x ), aluminum oxide (Al ₂ O ₃ ), aluminized zinc oxide (AZO), indium tin oxide (ITO), tin dioxide (SnO ₂ ), zinc oxide (ZnO), tantalum pentoxide (Ta 2 O 5 ), silicon nitride (Si ₃ N ₄ ), zirconium dioxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), cadmium tin oxide (Cd ₂ SnO ₄ ), or silicon carbonitride (SiCN).

2, method 200 includes depositing a mirror 103 on a waveguide 100. The waveguide 100 includes an input coupler 102 and an output coupler 105. The mirror 103 is deposited on a plurality of waveguide structures 106 of the waveguide 100. The mirror 103 may be deposited by PVD or another vapor deposition process (e.g., CVD or ALD). The mirror 103 may be deposited or otherwise formed by one or more processes or techniques, such as CVD, plasma enhanced CVD (PE-CVD), sub-atmospheric pressure CVD (SA-CVD), high density plasma CVD (HDP-CVD), flowable CVD, ALD, furnace or thermal ALD, thermal ALD, plasma enhanced ALD (PE-ALD), PVD, sputtering, evaporation deposition, ion beam deposition, inkjet printing, screen printing, or any combination thereof.

The method 200 includes depositing an encapsulation layer 104 on the mirror 103 at operation 202, as shown in FIG. 3A. The encapsulation layer 104 is disposed above the mirror 103, as shown in FIG. 3A. The anti-reflective coating 107 is disposed under the substrate 101. The encapsulation layer 104 is chromium nitride or silicon nitride.

At operation 203, as shown in FIG. 3B, a resist 302 is formed over the input coupler. As shown in FIG. 3B, the remaining packaging portion of the packaging layer 104 over the non-input coupler area is exposed. The resist 302 protects the packaging layer 104 from being removed during subsequent processing steps.

Resist 302 may be deposited by a block photolithography process, for example, spinning on the resist, baking, exposing with a pattern, and developing areas to remove the resist at areas on the waveguide where no input coupler is present.

At operation 204, as shown in FIG. 3C, the remaining packaging portion of the packaging layer 104 is removed, thereby exposing the exposed remaining mirror portion of the mirror 103 above the non-input coupler area. The etching process at operation 204 may include a wet etching process using tetramethylammonium, potassium iodide, or iodine to etch the remaining portion of the packaging layer 104. For example, the etching process may be a dry etching process that provides good selectivity between the packaging layer 104 and the mirror 103. As another non-limiting example, the etching process may be a wet etching process that avoids oxidation of the mirror 103 and potential contamination of the chamber. The etching process may etch all remaining portions of the encapsulation layer 104 not covered by the resist 302 down to the mirror 103 .

In operation 205, as shown in FIG. 3D, an etching process is used to etch the remaining mirror portion of the mirror 103 of the input coupler 102, thereby exposing the output coupler 105 of the waveguide 100. The etching process includes a wet etching process using tetramethylammonium, potassium iodide, or iodine. The wet etching process can etch all the remaining portions of the mirror 103 that are not covered by the resist 302 or the encapsulation layer 104 down to the plurality of optical structures 301.

At operation 206, as shown in FIG. 3E, the resist 302 is removed from the input coupler 102. The waveguide has only the mirror 103 above the input coupler 102, and the encapsulation layer 104 only above the mirror 103. The resist 302 is removed according to one or more etching processes. The etching process at operation 206 may include a dry etching process using _O plasma, an organic solvent such as propylene glycol methyl ether acetate (PGMEA), or using an immersion exposure process followed by using a tetramethylamoonium hydroxide (TMAH) solvent to etch the remaining portion of the encapsulation layer 104. The etching process removes the resist 302 so that the input coupler 102 includes an encapsulation layer 104 disposed on a mirror 103 disposed on a plurality of waveguide structures 106 on a substrate 101. This process allows a single block lithography process to form an encapsulated mirror only on the input coupler of the guide, but not on the output coupler, thereby providing the efficiency and life of a device containing a silver mirror.

4, method 400 includes depositing a mirror 103 on a waveguide 100 at operation 401, wherein the waveguide has an input coupler 102 and an output coupler 105. The mirror 103 is deposited on a plurality of waveguide structures 106 of the waveguide 100. The mirror 103 may be deposited by PVD or another vapor deposition process (e.g., CVD or ALD). Mirror 103 may be deposited or otherwise formed by one or more processes or techniques, such as CVD, plasma enhanced CVD (PE-CVD), sub-atmospheric pressure CVD (SA-CVD), high density plasma CVD (HDP-CVD), flowable CVD, ALD, furnace or thermal ALD, thermal ALD, plasma enhanced ALD (PE-ALD), PVD, sputtering, evaporation deposition, ion beam deposition, inkjet printing, screen printing, or any combination thereof. At operation 402, a first resist 501 is formed over the input coupler, as shown in FIG. 5A, wherein the first resist is disposed over the mirror 103. The remaining mirror portion of the mirror 103 is exposed over the output coupler 105. The anti-reflective coating 107 is disposed under the substrate 101. The first resist 501 includes any of the resists 302 described above.

At operation 403, as shown in FIG. 5B, the remaining mirror portion of the mirror 103 above the output coupler is removed. A wet etching process may be used to remove the remaining mirror portion of the mirror 103. The wet etching process may include a process using tetramethylammonium, potassium iodide, or iodine. The wet etching process may etch all remaining portions of the mirror 103 that are not covered by the first resist 501.

At operation 404, as shown in FIG. 5C, the first resist 302 is removed. The resist 302 is removed according to one or more etching processes. The etching process at operation 404 may include a wet etching process using tetramethylammonium or a dry etching process using _O plasma, an organic solvent such as propylene glycol methyl ether acetate (PGMEA), or an immersion exposure process followed by a tetramethylammonium hydroxide (TMAH) solvent to etch the remaining portion of the encapsulation layer 104. As shown in FIG. 5C, the etching process may remove the first resist 501 so that the mirror 103 remains only where the first resist 501 remains.

At operation 405, as shown in FIG. 5D, an encapsulation layer 104 is deposited over the mirror 103 and the output coupler 105. The encapsulation layer 104 may be deposited by PVD or another vapor deposition process, such as CVD or ALD. The encapsulation layer 104 may be deposited or otherwise formed by one or more processes or techniques, such as CVD, plasma enhanced CVD (PE-CVD), sub-atmospheric pressure CVD (SA-CVD), high density plasma CVD (HDP-CVD), flowable CVD (FCVD® process), ALD, furnace or thermal ALD, thermal ALD, plasma enhanced ALD (PE-ALD), PVD, sputtering, evaporation deposition, ion beam deposition, or any combination thereof.

At operation 406, as shown in FIG. 5E, a second resist 502 is formed over the mirror 103, wherein the remaining package portion of the package layer 104 over the non-input coupler area is exposed by the second resist 502. The second resist 502 protects the package layer 104 from etching during subsequent processing steps. The second resist 502 is formed so that it is wider than the mirror 103 to produce sidewall protection of the mirror 103 during later processing steps. The resist 502 may, for example, include any of the resists 302 or the resist 501 described herein. The second resist 502 may be formed by a block photolithography process, for example, spinning on the resist, baking, exposing with a pattern, and developing the area to remove the resist at areas where no input coupler is present on the waveguide.

At operation 407, as shown in FIG. 5F, the remaining packaging portion of the packaging layer 104 is removed, wherein the output coupler 105 of the waveguide 100 is exposed. For example, the etching process at operation 407 may include etching the chromium layer with a chromium etchant (e.g., ammonium/acetic acid) to etch the remaining portion of the packaging layer 104. The second resistor 502, which is wider than the mirror 103, allows the packaging layer 104 to remain on the side of the mirror 103 and above the mirror, as shown in FIG. 5F. This allows the mirror 103 to be protected from oxidants and potential etching complications.

At operation 408, the second resist 502 is removed from the waveguide 100, wherein the waveguide 100 has the mirror 103 only on the input coupler 102, and the encapsulation layer 104 is only on the mirror 103 or on the mirror 103 and the outer portion of the grating of the input coupler 102 surrounding the input coupler 102, as shown in FIG5G. The encapsulation layer 104 may remain on one or more sidewalls of the mirror 103. The second resist 502 is removed according to one or more etching processes. The etching process at operation 408 may include a wet etching process using tetramethylammonium or a dry etching process using _O plasma, an organic solvent such as propylene glycol methyl ether acetate (PGMEA), or an immersion exposure process followed by a tetramethylammonium hydroxide (TMAH) solvent to etch the remaining portion of the encapsulation layer 104. The etching process may remove the second resist 502 so that only the input coupler 102 includes the encapsulation layer 104 disposed on the mirror 103, thereby providing protection on the top layer of the mirror 103 and on the side walls of the mirror 103.

In summary, the methods described herein provide a waveguide having a mirror only over an input coupler, together with an encapsulation layer only over the mirror or over the mirror and an outer portion of a grating surrounding the input coupler. The mirror layer only over the input coupler with the encapsulation layer provides a barrier to the ingress of oxygen, sulfur, and moisture. The encapsulation layer protects the mirror from corrosion in the ambient atmosphere.

Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope of the same is determined by the scope of the following claims.

100: waveguide 101: substrate 101: waveguide 102: input coupler 103: mirror 103: package layer 104: package layer 104: mirror 105: output coupler 106: waveguide structure 107: anti-mirror 107: anti-reflection coating 200: method 202~206: operation 301: optical structure 302: first resistor 302: resistor 400: method 401~408: operation 501: first resistor 501: resistor 502: second resistor 502: resistor

In order to understand the manner of the above-mentioned features of the present disclosure in detail, a more specific description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the attached drawings. However, it should be noted that the attached drawings only illustrate exemplary embodiments of the present disclosure and are therefore not to be considered as limiting the scope thereof, and the present disclosure may recognize other equally effective embodiments.

FIG. 1 is a schematic diagram of a waveguide according to the disclosed aspects.

FIG. 2 is a flow chart of a method for forming a waveguide according to the disclosed embodiment.

3A-3D are schematic cross-sectional views of a substrate during a method according to aspects of the present disclosure.

FIG. 4 is a flow chart of a method for forming a waveguide according to an aspect of the present disclosure.

5A to 5G are schematic cross-sectional views of a substrate during a method according to aspects of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Waveguide

101: Substrate

101: Waveguide

102: Input coupler

103:Mirror

103: Packaging layer

104: Packaging layer

104: Mirror

105: Output coupler

106: Waveguide structure

Claims (20)

A device, comprising: a substrate, the substrate comprising: an input coupler, comprising a first arrangement of waveguide structures, the first arrangement of waveguide structures having a critical size defining one or more gaps between each waveguide structure of the first arrangement of waveguide structures; an output coupler, comprising a second arrangement of waveguide structures, the second arrangement of waveguide structures having a critical size defining one or more gaps between each waveguide structure of the second arrangement of waveguide structures; a mirror, disposed on the input coupler, the mirror disposed between the one or more gaps between each waveguide structure of the first arrangement of waveguide structures, a packaging layer, disposed on the mirror, the packaging layer having a refractive index of about 1.0 to about 1.5; and A medium, including a refractive index of approximately 1.0, is disposed on the output coupler, the medium being disposed between the one or more gaps between each waveguide structure of the second arrangement of waveguide structures. A device as described in claim 1, wherein the packaging layer is disposed only on a top side of the mirror. A device as described in claim 2, wherein the packaging layer is further disposed on one or more side walls of the mirror. A device as described in claim 1, wherein the mirror comprises a reflectivity greater than 90%. A method comprising the steps of: depositing a mirror on a waveguide having an input coupler and an output coupler; depositing a packaging layer on the mirror; forming a barrier on the input coupler, wherein a residual packaging portion of the packaging layer is exposed on a non-input coupler region; removing the residual packaging portion of the packaging layer, wherein a residual mirror portion of the mirror on the non-input coupler region is exposed; removing the residual mirror portion of the mirror of the input coupler, wherein the non-input coupler region of the waveguide is exposed; and The resistor above the input coupler is removed, and the waveguide has the mirror only above the input coupler and the encapsulation layer only above the mirror. The method as described in claim 5, wherein the step of forming the resistor on the input coupler comprises the following steps: Depositing a resistor layer on the packaging layer; and Patterning the resistor layer so that the remaining packaging portion is exposed. The method as described in claim 5, wherein the step of depositing the encapsulation layer comprises the following steps: performing one or more vapor deposition processes. The method of claim 7, wherein the step of performing one or more vapor deposition processes comprises the step of generating an oxygen plasma. The method as described in claim 5, wherein the encapsulation layer is chromium nitride or silicon nitride. The method of claim 5, wherein the mirror is silver or aluminum. The method as described in claim 5, wherein the step of removing the remaining packaging portion of the packaging layer includes the following step: using an etching process to etch the remaining portion of the packaging layer. The method as described in claim 11, wherein the etching process is a wet etching process or a dry etching process. A method comprising the steps of: Depositing a mirror on a waveguide having an input coupler and an output coupler; Forming a first resistor on the input coupler, wherein a residual mirror portion of the mirror on a non-input coupler region is exposed; Removing the residual mirror portion of the mirror on the non-input coupler region; Removing the first resistor; Depositing a packaging layer on the mirror and the non-input coupler region; Forming a second resistor on the mirror, wherein a residual packaging portion of the packaging layer on the non-input coupler region is exposed by the second resistor; Removing the residual packaging portion, wherein the non-input coupler region of the waveguide is exposed; and The second resistor is removed, the waveguide has the mirror only over the input coupler, and the encapsulation layer: only over the mirror; or over the mirror and an outer portion of a grating surrounding the input coupler. The method as described in claim 13, wherein the step of forming the resistor on the input coupler comprises the following steps: Depositing a resistor layer on the packaging layer; and Patterning the resistor layer so that the remaining packaging portion is exposed. The method of claim 14, wherein the step of depositing the encapsulation layer comprises the following steps: performing one or more vapor deposition processes. The method of claim 15, wherein the step of performing one or more vapor deposition processes comprises the step of generating an oxygen plasma. The method of claim 13, wherein the encapsulation layer is chromium nitride or silicon nitride. The method of claim 13, wherein the mirror is silver or aluminum. The method as described in claim 13, wherein the step of removing the remaining packaging portion of the packaging layer includes the following step: etching the packaging layer using an etching process. A method as described in claim 19, wherein the etching process is a wet etching process or a dry etching process.

Images