TW202436660A - A robust icefill method to provide void free trench fill for logic and memory applications - Google Patents

Abstract

Methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. The inhibition plasma increases a nucleation barrier of the deposited film. The inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill.

Description

Robust ICEFILL method for void-free trench filling for logic and memory applications

The present disclosure relates to methods and systems for filling gaps.

Many semiconductor device manufacturing processes involve the formation of films, including silicon-containing films such as silicon oxide or silicon nitride. Silicon-containing films can be deposited using plasma enhanced atomic layer deposition (PEALD). Depositing high-quality films can be particularly challenging when depositing films in gaps. Challenges can include the formation of pores and/or seams in the film.

The prior art descriptions provided herein are intended to generally present the context of the present disclosure. The achievements of the inventors named in the present case within the scope described in this prior art section, as well as the embodiments of the description that may not be qualified as prior art at the time of application, are not intended or implied to be recognized as prior art against the present disclosure.

Methods and systems for filling gaps in structures are disclosed herein. In one embodiment of the present invention, a method for filling gaps is provided, the method comprising: providing a substrate in a process chamber, the substrate having one or more structures, each structure including gaps; and performing a first set of cycles: (a) exposing the substrate to a suppression plasma to suppress deposition on a first portion of each gap, and (b) depositing a dielectric material in each gap after (a), wherein exposing the substrate to the suppression plasma occurs for a first duration during a first subset and a second subset of the first set of cycles, and modifying at least one non-duration of exposing the substrate to the suppression plasma as a base parameter during the second subset of the first set of cycles.

In some embodiments, the non-continuous time-based parameter is a flow rate of the inhibitory species, a flow rate of a dilution gas, a pressure, or a radio frequency (RF) power. In some embodiments, a first subset of the first set of cycles deposits a greater depth of the inhibitory gap in the gap than a second subset of the first set of cycles. In some embodiments, exposing the substrate to the inhibitory plasma includes flowing the inhibitory species into the process chamber, and wherein the flow rate of the inhibitory species during the second subset of the first set of cycles is lower than the first subset of the first set of cycles. In some embodiments, the difference in the flow rate of the inhibitory species between the first subset of the first set of cycles and the second subset of the first set of cycles is between about 1 seem and about 5 seem. In some embodiments, exposing the substrate to the suppression plasma comprises co-flowing a suppression species with an inert gas into a process chamber, and wherein the ratio of the suppression species to the inert gas during a second subset of a first set of cycles is higher than the first subset of the first set of cycles. In some embodiments, the suppression species comprises a nitrogen-containing species. In some embodiments, exposing the substrate to the suppression plasma comprises providing radio frequency (RF) energy to the process chamber, and wherein the RF power during the second subset of the first set of cycles is lower than the first subset of the first set of cycles. In some embodiments, the difference in RF power between the first subset of the first set of cycles and the second subset of the first set of cycles is between about 50 W and about 700 W. In some embodiments, the RF power per substrate is between about 250 W and about 1250 W. In some embodiments, each of the one or more structures has one or more recessed features. In some embodiments, at least one of the recessed features has a critical size variation of at least 10% within the substrate. In some embodiments, at least one non-continuous time is modified as a base parameter based on the critical size variation of at least one recessed feature of the one or more structures. In some embodiments, at least one of the recessed features has a depth variation of at least 10% between structures. In some embodiments, at least one non-continuous time is modified as a base parameter based on the depth variation of at least one recessed feature of the one or more structures. In some embodiments, the dielectric material is an oxide material. In some embodiments, the oxide material is silicon dioxide. In some embodiments, further comprising performing a second set of cycles: exposing the substrate to a suppression plasma to suppress deposition on a second portion of the gap, wherein exposing the substrate to the suppression plasma during the first subset and the second subset of the second set of cycles occurs for a second duration different from the first duration, and modifying at least one non-duration of suppressing the plasma during the second subset of the second set of cycles as a base parameter; and after (a), depositing a dielectric material in the gap.

In another embodiment of the present invention, a system for filling gaps is provided, the system comprising: a process chamber, and one or more memories and one or more processors, the one or more memories being configured to have computer executable instructions for controlling the one or more processors for: providing a substrate in the process chamber, the substrate having one or more structures, each structure including a gap; and performing a first set of cycles: (a) exposing the substrate to a suppression plasma to suppress deposition on a first portion of each gap, and (b) after (a), depositing a dielectric material in each gap, wherein exposing the substrate to the suppression plasma occurs for a first duration during a first subset and a second subset of the first set of cycles, and modifying at least one non-duration of the exposure of the substrate to the suppression plasma as a base parameter during the second subset of the first set of cycles.

Disclosed herein are methods and systems for filling gaps in structures at stations of a tool, wherein the tool has different fill rates between stations. In another embodiment of the embodiments herein, a system is provided, the system comprising: a process chamber comprising a plurality of stations; one or more processors and one or more memories configured for: receiving a plurality of substrates in the plurality of stations, each substrate having a structure with a gap, performing a first set of cycles in each of the stations: (a) exposing the substrate to a suppression plasma to suppress deposition on a first portion of the gap, and (b) after (a), depositing a dielectric material in the gap, and after performing the first set of cycles, performing a second set of cycles in each station of a first subset of the plurality of stations: (c) depositing a dielectric material in the gap of the substrate only in stations of the first subset of the plurality of stations.

In some embodiments, after the first set of cycles, a first substrate in a site of a first subset of the plurality of sites has a lower depth of fill of dielectric material than a second substrate in the plurality of substrates. In some embodiments, the second substrate is in a site that is not part of the first subset of the plurality of sites. In some embodiments, after the second set of cycles, the first substrate has a substantially equal depth of fill of dielectric material as the second substrate. In some embodiments, the one or more processors and the one or more memories are further configured to expose the substrate to an inhibiting plasma prior to (c) to inhibit deposition on the first portion of the gap. In some embodiments, the one or more processors and the one or more memories are further configured to not perform (c) in one or more sites that are not in the first subset of the plurality of sites. In some embodiments, the one or more processors and the one or more memories are further configured to flow one or more reactants to each of the one or more sites during the second set of cycles. In some embodiments, during the second set of cycles, the one or more reactants do not react with substrates in sites that are not in the first subset of the plurality of sites. In some embodiments, the one or more processors and the one or more memories are further configured to provide radio frequency (RF) power to the first subset of the plurality of sites during the second set of cycles, and not provide RF power to sites that are not in the first subset of the plurality of sites during the second set of cycles. In some embodiments, the one or more processors and the one or more memories are further configured to flow one or more reactants to each of the plurality of sites during the second set of cycles. In some embodiments, the one or more processors and the one or more memories are further configured to flow one or more reactants to a first subset of the plurality of stations during the second set of cycles and not flow one or more reactants to stations not in the first subset of the plurality of stations during the second set of cycles. In some embodiments, a second process chamber is further included, and wherein the first subset of the plurality of stations is a portion of the process chamber, and the stations not in the first subset of the plurality of stations are a portion of the second process chamber.

In another embodiment of the present invention, a method is provided, the method comprising: receiving a plurality of substrates in a plurality of stations, each substrate having a structure with a gap, performing a first set of cycles in each of the stations: (a) exposing the substrate to an inhibiting plasma to inhibit deposition on a first portion of the gap, and (b) after (a), depositing a dielectric material in the gap, and after performing the first set of cycles, performing a second set of cycles in each station of a first subset of the plurality of stations: (c) depositing dielectric material in the gap of the substrate only in the stations of the first subset of the plurality of stations.

In some embodiments, after the first set of cycles, a first substrate in a site of a first subset of the plurality of sites has a lower depth of fill of dielectric material than a second substrate in the plurality of substrates. In some embodiments, the second substrate is in a site that is not part of the first subset of the plurality of sites. In some embodiments, after the second set of cycles, the first substrate has a substantially equal depth of fill of dielectric material as the second substrate. In some embodiments, further including exposing the substrate to an inhibiting plasma to inhibit deposition on the first portion of the gap prior to (c). In some embodiments, further including not performing (c) in one or more sites that are not in the first subset of the plurality of sites. In some embodiments, further including flowing one or more reactants to each of the one or more sites during the second set of cycles. In some embodiments, during the second set of cycles, the one or more reactants do not react with substrates in sites that are not in the first subset of the plurality of sites. In some embodiments, further comprising providing radio frequency (RF) power to the first subset of the plurality of sites during the second set of cycles, and not providing RF power to sites that are not in the first subset of the plurality of sites during the second set of cycles. In some embodiments, further comprising flowing the one or more reactants to each of the plurality of sites during the second set of cycles. In some embodiments, further comprising flowing the one or more reactants to the first subset of the plurality of sites during the second set of cycles, and not flowing the one or more reactants to sites that are not in the first subset of the plurality of sites during the second set of cycles. In some embodiments, a second processing chamber is further included, and wherein the first subset of the plurality of stations is part of the processing chamber, and stations not in the first subset of the plurality of stations are part of the second processing chamber.

These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings.

In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be implemented without some or all of these specific details. In other respects, well-known process operations are not described in detail in order not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific implementations, it will be understood that they are not intended to limit the disclosed embodiments.

Semiconductor manufacturing processes typically include dielectric gapfill using chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) methods to fill features. Methods for filling features using dielectric materials, including but not limited to oxide films and silicon-containing films such as silicon oxide, and related systems and equipment are described herein. The methods described herein can be used to fill vertically oriented features formed in a substrate. Such features may be referred to as gaps, re-entrant features, negative features, unfilled features, or simply features. Filling such features may be referred to as gapfill. Features formed in a substrate may be characterized by one or more narrow and/or re-entrant openings, feature internal shrinkage, and high aspect ratios. In some embodiments, the features can have an aspect ratio of at least about 2:1, at least about 4:1, at least about 6:1, at least about 20:1, at least about 100:1, or more. The substrate can be a silicon wafer, such as a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer, including a wafer having one or more layers of material deposited thereon, such as a dielectric, conductive, or semiconductor material.

One embodiment of the present disclosure relates to a method of using a suppressed plasma to facilitate void-free bottom gap fill during atomic layer deposition (ALD) of a dielectric material in a gap. The suppressed plasma produces a passivated surface and increases the nucleation barrier of the deposited ALD film. When the suppressed plasma interacts with the material in the feature, the material at the bottom of the feature receives less plasma treatment than the material located closer to the top of the feature or in the field due to geometric shielding effects. Therefore, deposition at the top of the feature is selectively suppressed, while deposition in the lower portion of the feature proceeds in a less suppressed or unsuppressed manner. Therefore, a bottom-up fill is performed in the ALD process, resulting in a more favorable sloped profile that reduces seam effects and prevents void formation. Halogen-containing plasmas can be effective suppression plasmas. For example, for some applications, plasmas produced from nitrogen trifluoride (NF ₃ ) can provide suppression effects in substantially less time than plasmas produced from molecular nitrogen (N ₂ ).

FIG. 1 is a process flow diagram illustrating a method for filling a gap with a dielectric material. The method begins by providing a structure having one or more gaps to be filled (101). The structure may be formed by one or more material layers deposited on a substrate. The substrate may be a silicon or other semiconductor wafer, such as a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer, which includes a wafer having one or more material layers deposited thereon, such as a dielectric, conductive, or semiconductor material. The method may also be applied to gap filling other substrates, such as glass, plastic, etc., including applications in the manufacture of microelectromechanical (MEMS) devices.

Examples of structures include 3D NAND structures, DRAM structures, and shallow trench isolation (STI) structures. The structure includes a gap, and the gap has sidewalls of the gap formed by an etch-susceptible material. In one example, the 3D NAND structure includes an oxide-nitride-oxide-nitride (ONON) stack covered with a polysilicon layer. In another example, the structure may include a lateral/tunnel structure extending horizontally from a common vertical trench. Other examples of sidewall materials include oxides, metals, and semiconductor materials. The methods described herein are not limited to a particular type of sidewall material and can be used to inhibit any sensitive material.

A dielectric material is deposited in the gap using a suppressed plasma (105). As discussed further below, this step may involve cycles of a suppressed plasma followed by cycles of ALD of the dielectric material. The suppressed plasma process may be characterized by an inhibition effective depth (IED). The IED describes a depth above which deposition will be inhibited. The IED may be increased or decreased by varying parameters of the suppressed plasma process, including time, pressure, species, and flow rate. The IED may be affected by multiple parameters, including the specific species used, the duration of the suppressed plasma process, the plasma power, the ratio of gas flow of the suppressing species (rather than a carrier gas such as an inert gas, such as helium or argon), and the pressure. In particular, the duration of suppression may have a significant effect on the IED. For example, a plasma produced from nitrogen trifluoride (NF ₃ ) can inhibit micron-scale deep gaps in a few seconds, while smaller depths can be inhibited by exposure to the inhibiting plasma for as little as 0.1 second. For high aspect ratio and deep structures, such as at least about 100:1 and 3 µm or deeper, NF ₃ is an ideal inhibitory species to inhibit the structure sufficiently to avoid pinching, while not completely inhibiting the structure. Other species can also be used, including halogenated species such as NF ₃ and non-halogenated species such as N ₂ .

During the design of a bottom-up fill process, multiple suppression zones may be planned where the suppression plasma treatment may vary between suppression zones. For example, the suppression plasma treatment may be adjusted so that the IED is closer to the bottom of the feature, e.g., 75% of the total depth of the feature is suppressed. A cycle of the ALD process may then be performed to fill the bottom 25% of the feature. The suppression plasma parameters may then be adjusted to suppress, e.g., the top 50% of the feature (relative to the total depth, regardless of any fill), and then fill the next bottom portion of the feature.

In certain embodiments, the IED may be affected by the geometry of the feature to be filled. For example, a reentrancy feature affects the mass transport of inhibiting species in the feature. A reentrancy feature may be characterized by a narrowing of the distance between sidewalls at a depth within the gap, where the distance may be measured along an axis parallel to the top or bottom surface of the substrate, and where the distance between the sidewalls is greater above or below the reentrancy feature. Reentrancy features present challenges during deposition because the narrow portion within the gap increases the risk of void formation beneath the smaller gap. "Pinching" occurs when the gap at a reentrancy feature is filled before the deposition completely fills below the reentrancy feature, resulting in internal voids.

One method of reducing pinching and internal porosity is to inhibit deposition at and over a recessed feature until sufficient deposition has occurred beneath the recessed feature. Plasma inhibition can be adjusted to inhibit at recessed features, and inhibition can be performed until the gap has been sufficiently filled. Once the gap has been sufficiently filled, deposition can occur at and/or over the recessed feature with a reduced risk of creating internal porosity. The inhibiting plasma can then be adjusted to reduce IED so that deposition occurs at and/or over the recessed feature. It is noteworthy that the gap does not need to be completely filled beneath the recessed feature prior to deposition at the recessed feature, but only sufficiently filled to reduce the risk of pinching and porosity. Because deposition is suppressed at the recessed features that have not yet reached below the recessed features, the gaps below the recessed features can be fully filled.

Although the IED at the depth of the recessed feature may reduce or eliminate pinching, in some embodiments, the recessed feature and/or the overall gap may have within-wafer (WW) and/or between-wafer (W2W) variation. In some embodiments, this variation may cause WW or W2W variation in the corresponding IED. This is undesirable and may increase the risk of pinching when the IED is greater or less than the depth of the recessed feature for the reasons mentioned above. In some embodiments, the depth of the recessed feature may vary by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. The variation in the IED may be due to the effect of the recessed feature on the IED. For example, variations in critical dimensions throughout gaps and at recessed features affect mass transport within the feature, changing the depth at which the inhibited plasma impacts the surface, i.e., the IED. Furthermore, the depth of the recessed feature may vary such that a single IED may not inhibit at the recessed feature depth for all gaps to be filled. This may be undesirable because the gap may be inhibited too far above or below the recessed feature, causing pinching at the recessed feature and thus voids.

To account for this variation, in certain embodiments, the suppressing plasma treatment may be modified to suppress within a range at the target depth. For example, multiple suppressing plasma treatments may be tuned to have IEDs at 78%, 75%, and 72% depth instead of just 75%. This may be accomplished by performing multiple suppressing plasma treatments. Typically, multiple suppressing plasma treatments are performed for a specific target IED, such as 75%, because the suppressing effect may diminish before the gap is sufficiently filled. Once the gap has been sufficiently filled, the suppressing plasma may be modified to target a different IED, such as 50%. However, in certain embodiments, the suppressing plasma may be modified to suppress across a range that includes the target IED. In certain embodiments, ten or more suppression plasma treatments may be performed with the same parameters to target a single IED, e.g., same duration, plasma power, gas flow, etc., and vice versa, the suppression plasma treatment may be modified to suppress a range including a single IED.

Thus, in certain embodiments, the suppression plasma treatment may be modulated such that the suppression plasma treatment suppresses slightly more and/or less than the average depth of the recessed features. Such modulation may be advantageous when the depth of the recessed features varies by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%, or when the critical size of the recessed features varies by at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. In certain embodiments, the non-duration time between suppression plasma treatments may be varied as a base parameter. The non-duration time as a base parameter may be any parameter other than the time allocated to, for example, the operation of the suppression plasma treatment (i.e., its duration). Duration may have the greatest impact on the IED of a suppressed plasma process, such that changing the duration may significantly increase or decrease the IED, which is undesirable. The desired IED change may be less than about 3%, less than about 5%, less than about 10%, or less than about 20%, such that changing the duration may change the IED more than desired. In certain embodiments, the least sensitive parameter of a suppressed plasma process may be modified. In certain embodiments, the plasma power of a suppressed plasma process may be the least sensitive parameter. For example, a 10% increase in HF power may change the IED by 3% less than a 10% change in duration that causes an IED change of more than 4.5%.

Figures 2A-2D illustrate gap filling where the gap has a variable recessed feature. Figures 2A-2B present structures that illustrate what may occur when there is variation in the recessed feature using a suppressed plasma process under a single IED. In Figure 2A, an exemplary structure 200a is presented during various stages of a gap filling method described herein. At 201, structure 200a is shown as having a gap 206 to be filled with a dielectric material. In the example of Figure 2A, gap 206 is formed between structures that may include dielectric, conductive, or semiconductor materials. In some embodiments, structure 200 is a low aspect ratio structure. In some embodiments, a low aspect ratio structure may be a structure having an aspect ratio between about 3:1 and about 7:1. In some embodiments, the low aspect ratio structure may have a depth of at least about 1 µm. In some embodiments, structure 200 is a high aspect ratio structure. In some embodiments, a conformal layer (not shown) is provided, which may be a liner deposited prior to deposition using an inhibiting plasma. The conformal layer may protect underlying layers from unwanted etching during a subsequent inhibiting plasma treatment. In some embodiments, the conformal layer is a silicon nitride layer. In some embodiments, the conformal layer is a silicon oxide layer. In some embodiments, the conformal layer is a metal oxide layer, such as titanium oxide, zirconium oxide, tin oxide, barium oxide, or a combination thereof. In some embodiments, the conformal layer is a silicon layer, such as polysilicon. In some embodiments, there is no conformal layer.

2A, gap 206 may be represented by concave features 208a-208b. As indicated by the vertical lines, concave feature 208a is smaller than concave feature 208b, where the size may be based on the difference between the critical dimension at the narrowest portion of the concave feature and the critical dimension at the widest portion.

In some embodiments, there may be variations in the depth of the recessed feature, the critical dimension at any point in the gap, and the difference between the critical dimension at the recessed feature and the critical dimension above/below the recessed feature. Each of these variations may affect the IED and/or mass transport within the feature and thus affect deposition.

At 201, structure 200a may also be characterized by inhibition effective depth (IED) lines 204a-1 to 204a-2. IED lines 204a-1 to 204a-2 represent the inhibition depth resulting from the plasma inhibition process. It is noteworthy that IED line 204a-1 at recessed feature 208a is lower than recessed feature 208a, while IED line 204a-2 at recessed feature 208b is higher than recessed feature 208b. This IED difference may occur despite each gap being exposed to the same inhibiting plasma. The difference in IED is caused by the size difference between recessed features 208a and 208b. Since the concave feature 208b is larger than the concave feature 208a, the mass flow of the inhibiting species in the gap having the concave feature 208b is smaller, resulting in a corresponding reduction in the IED.

At 203, gap 206 is filled with dielectric material 210a in a bottom-up manner. At 203, the gap with recessed feature 208b has a void 202. This void is caused by too shallow IED line 204a-2, i.e., insufficient suppression. Because the suppression effect is not deep enough, deposition occurs at the recessed feature, causing a pinching effect that leads to void 202.

Similarly, FIG. 2B illustrates another example of how voids may occur due to variations in recessed features. At 205, structure 200b has gap 206 with recessed features 208c and 208d. Recessed feature 208d is at a greater depth within the gap than recessed feature 208c. After the suppression plasma treatment, the IED lines 204b of both gaps are identical, however, the features are suppressed deeper than (i.e., at a greater depth) recessed feature 208c. At 207, gap 206 is filled with dielectric material 210b in a bottom-up manner such that there is relatively little or no deposition on the sidewalls above the fill line. However, void 202 is formed in dielectric material 210b. Even though the IED is the correct depth for recessed feature 208d, an IED deeper than recessed feature 208c may still result in this void.

2C-2D present structures illustrating methods for improving uniformity and reducing voids caused by variations in recessed structures.

FIG. 2C shows a structure 200c having a gap 206 and recessed features 208a-208b. Structure 200c may be the same structure as structure 200a. At 211, structure 200c has two sets of IED lines. IED lines 204a-1 and 204a-2 may be the same as shown in FIG. 2A. Additionally, IED lines 204c-1 to 204c-2 are shown and may result from different suppressed plasma treatments. IED lines 204c-1 and 204c-2 have different depths based on the difference between recessed features 208a and 208b. IED lines 204c-1 and 204c-2 are slightly deeper in gap 206. Thus, IED line 204c-1 may be of an appropriate depth for suppression of recessed feature 208a, and IED line 204c-2 may be of an appropriate depth for suppression of recessed feature 208b.

In some embodiments, the variation in the critical dimension within the gap and the variation in the recessed feature dimension may be at least about 5%, at least about 10%, at least about 15%, or between about 10% and about 20%. In some embodiments, the variation in the critical dimension or recessed feature dimension may have a greater impact on the IED than the variation in the recessed feature depth. For example, a 10% variation in the recessed feature depth may affect the required IED by 10%, while a 10% variation in the critical dimension or recessed feature dimension may affect the required IED by more than 15%. Thus, in various embodiments, parameters of the suppression plasma process may be varied to target the IED lines 204a-1, 204a-2, 204c-1, and 204c-2 based on variations in critical size, recessed feature size, and recessed feature depth.

At 213, gap 206 is filled in a bottom-up manner using dielectric material 210c. In particular, dielectric material 210c has no pores. This result results from filling the gap using a suppressed plasma treatment resulting in IED lines 204c-1 and 204c-2, followed by an additional gap fill resulting in a suppressed plasma treatment resulting in IED lines 204a-1 and 204a-2. It is noted that although both IED lines 204a-1 to 204a-2 and IED lines 204c-1 to 204c-2 are shown at 211, it should be understood that they correspond to different suppressed plasma treatments (given that these lines show the depth of suppression of the upper sidewall, IED line 204c-1 may have suggested suppression at line 204a-1). Gap filling may be initially performed using a suppressed plasma process resulting in IED lines 204c-1 and 204c-2. The suppressed plasma process may then be modified to result in IED lines 204a-1 and 204a-2 and gap filling may be continued until gaps above recessed features 208a and 208b are filled.

FIG2D shows a structure 200d having a gap 206 and recessed features 208c-208d, similar to FIG2B. At 215, structure 200d has two sets of IED lines. IED line 204b may be the same as that shown in FIG2B, but may result from a different suppressed plasma treatment to IED line 204d. It is noteworthy that when IED line 204b is at the correct depth of recessed feature 208d, IED line 204d is at the correct depth of recessed feature 208c.

At 217, gap 206 is filled in a bottom-up manner using dielectric material 210d. Dielectric material 210d does not have pores. This result results from filling the gap using a suppressed plasma treatment that results in IED line 204b, followed by additional gap filling using a suppressed plasma treatment that results in IED line 204d. It is worth noting that although both IED lines 204b and 204d are shown at 215, it should be understood that they correspond to different suppressed plasma treatments. The gap filling can be initially performed using the suppressed plasma treatment that results in IED line 204b. The suppressed plasma treatment can then be modified to result in IED line 204d and gap filling continued until the gaps above the recessed features 208c and 208d are filled.

FIG3 shows an example of a process sequence that may be used in accordance with the disclosed embodiments. The process sequence of FIG3 includes treating a substrate using a suppressed plasma. Other operations (e.g., soak, passivation) may be omitted in certain embodiments and operations may be added in certain embodiments. In the exemplary process sequence of FIG3, one or more wafers undergo gap filling. The process may begin with a soak (302) after provision to a deposition chamber. This may be beneficial, for example, for particle removal or other pre-processing. Then, an n1 cycle of ALD deposition of a liner is performed (304). Further details of liner ALD are discussed below.

In the operation showing the first suppression block ( n =1), n suppression blocks are performed after depositing the optional liner. The first operation is a suppression plasma (308) for surface treatment. As discussed above, the plasma may include halogen species containing anion and radical species, such as F- ^, Cl- ^, I- ^, Br- ^, fluorine radicals, etc. Other suppression plasmas may be used. In some embodiments, the suppression plasma is generated from non-halogenated species, including nitrogen-containing species and nitrogen-containing non-halogenated species. For example, a plasma generated from molecular nitrogen ( _N2 ), molecular hydrogen ( _H2 ), ammonia ( _NH3 ), amines, diols, diamines, amine alcohols, thiols, halides, halides, HF, fluorine-containing species, chlorine-containing species, iodine-containing species, or a combination thereof can be used as the suppressed plasma. In certain embodiments, the suppressed plasma treatment is performed at high pressure as described herein.

When the plasma is inhibited from interacting with the material in the feature, due to geometric shielding effects, the material at the bottom of the feature receives less plasma treatment than the material located closer to the top of the feature or in the field area. Therefore, deposition at the top of the feature is selectively inhibited, while deposition in the lower portion of the feature proceeds with less inhibition or no inhibition. In Figure 3, the next operation in the inhibition block is an n2 cycle of ALD fill (310). Dielectric material is selectively deposited at the bottom of the feature. The plasma inhibition and n2 cycles of ALD fill together constitute a growth cycle. This cycle can be repeated n3 times to continue filling the feature with intermittent inhibition operations as the inhibition effect weakens. The number of growth cycles in the inhibition block may depend on the concavity of the feature, i.e., whether it narrows at one or more points from the bottom to the top of the feature. Features that exhibit more concavity may use longer inhibition times or multiple inhibition blocks. In certain embodiments, the n2 cycles of ALD fill may include at least one ALD cycle, at least about 10 ALD cycles, or between 1 and about 15 ALD cycles. The plasma is suppressed and the n2 cycles of ALD fill together constitute a growth cycle. This cycle may be repeated n3 times to continue filling the feature with intermittent suppression operations as the suppression effect weakens.

In some embodiments, the non-duration of the suppressed plasma may be varied as a base parameter (311) between growth cycles. For example, the plasma power or the inhibitor species flow rate may be varied. In some embodiments, the non-duration may be varied as a base parameter to reduce the IED of the suppressed plasma process. In some embodiments, the duration of the suppressed plasma process is the primary parameter adjusted to vary the IED because the IED is highly sensitive to the duration of exposure to the suppressed plasma. However, varying the duration may vary the IED more than variations in the recessed features may vary the IED, so that porosity may still occur due to over- or under-suppression. By changing a parameter to which the IED is less sensitive, such as plasma power, the IED can similarly be slightly reduced to appropriately suppress variations between recessed features. In certain embodiments, the least sensitive parameter for suppressing the plasma can be changed, where the least sensitive parameter can be selected from the group consisting of suppression species flow rate, dilution gas flow rate (e.g., _N2 or Ar), and plasma power.

Thus, in certain embodiments, during a first growth cycle, the plasma may be suppressed to a first IED, and one or more cycles of ALD fill may be performed. During a subsequent second growth cycle, the non-duration of suppressing the plasma is modified as a base parameter to reduce the IED (notably, the duration of suppressing the plasma may be the same during the first growth cycle and the second growth cycle). Additional cycles of ALD fill may be performed. This modification may be performed multiple times depending on the variation of the recessed feature, for example, more modifications to suppressing the plasma within a single suppression block may be performed for larger variations in the critical size of the recessed feature.

In the example of Figure 3, the inhibition block ends with an optional passivation operation (312). This is a surface treatment that removes residual inhibitor and may also densify the deposited film. In some embodiments, an oxygen plasma is used.

One or more additional inhibition blocks including growth cycles and passivation may be performed for a total of n inhibition blocks (314). The number of inhibition blocks depends on how much material is used to fill the feature. The inhibition plasma, ALD, and passivation conditions may be varied between inhibition blocks used to fill the feature and inhibition blocks. For example, the inhibition plasma duration may be 20 seconds until the bottom quarter of the feature is filled (inhibition block 1), then changed to 5 seconds for the middle 50% of the structure (inhibition block 2), and so on. Each inhibition block may have a different IED, where the process parameters of the inhibition plasma treatment for the inhibition block are varied to target the different IEDs. Each inhibition block may fill a portion of the feature below the IED of that inhibition block.

In some embodiments, a change in the non-continuation time as a parameter may change the IED by less than about 3%, less than about 5%, less than about 10%, or less than about 20%. In some embodiments, a change in the non-continuation time as a parameter may change the IED by less than about 100 nm, less than about 200 nm, less than about 300 nm, less than about 400 nm, or less than about 700 nm. This may be contrasted to changes in the suppressed plasma between suppression blocks where the suppressed plasma may be modified to change the IED by more than about 10% or more than about 20%. For example, in some embodiments, a gap fill process may have four suppression blocks where the parameters for suppressing the plasma between the suppression blocks may be set to suppress at 8 um, 4 um, 2 um, and 1 um. Changes to the suppressed plasma within a suppression block may be performed to appropriately suppress the concave features of WW or W2W variations. In some embodiments, such concave feature variations may result in much smaller IED changes than IED changes between suppression blocks. In some embodiments, the target IED change between suppression blocks is maximized to effectively fill the features without voids. Because the IED is highly sensitive to the duration of the suppressed plasma treatment, the duration is typically modified between suppression blocks. In contrast, changes to the suppressed plasma within a suppression block may be much smaller, making the duration too sensitive to be changed for variations in the concave features. As mentioned above, small changes in suppression plasma treatment duration can have significantly larger effects on IEDs than similar small changes in RF power or suppression species flow.

In various embodiments, parameters of the non-continuous time between suppression plasma treatments may be varied to target a range of IEDs as discussed above. Reducing the flow rate of the suppression species (e.g., as a percentage of the total flow rate), reducing the RF power, and/or reducing the pressure may reduce the IED. In certain embodiments, the flow rate of the suppression species may be varied between about 1 sccm and about 5 sccm between a first suppression plasma treatment and a second suppression plasma treatment. In certain embodiments, the RF power may be varied between about 50 W and about 700 W between a first suppression plasma treatment and a second suppression plasma treatment.

When the feature is nearly full, inhibition may no longer be required and the fill may be completed using an n4 cycle of ALD fill (316). In some embodiments, an optional capping or blanketing layer of dielectric may then be deposited (318). Plasma enhanced chemical vapor deposition (PECVD) may be used at this stage for rapid deposition.

Another embodiment of the present disclosure is directed to the process shown in FIG. 1. In some embodiments, the process shown in FIG. 1 can be performed simultaneously in multiple stations of a process chamber or tool. As further described below with respect to FIGS. 5-8, a process chamber or tool can have multiple stations, each of which can be configured to receive a substrate having a structure with a gap to be filled. The gap fill process described herein can be performed simultaneously at each station to fill the gap in each substrate, each of which can share or be connected to a central reactant delivery system or radio frequency (RF) power supply.

In some embodiments, gap filling may be performed at different rates between stations on a single tool or between stations across multiple tools. Such differences in film growth rates between stations may be caused by a number of imbalances. For example, the fluid dynamics of reactant flow to each station or the RF generator at each station may be performed differently, causing variation in processing between stations. Suppressed plasma processes such as described herein may be particularly sensitive to such variations. In some embodiments, _NF3 suppressed plasma processing may be performed for as little as 0.1 seconds, so that variations in plasma or flow characteristics between stations can affect the suppressed plasma, causing corresponding changes in growth rate due to under-suppression or over-suppression. Unlike other ALD processes that may rely on saturation, the substrate may be exposed to the suppressed plasma for a sufficiently short duration to preferentially suppress the upper portion of the gap to promote bottom-up fill. Thus, site-to-site variations, such as hardware variations, may cause some sites to fill at a slower rate than other sites, which is undesirable.

4A and 4B present a drawing of a 4-station process chamber (also referred to as a 4-station tool) according to many embodiments herein. In FIG. 4A , four stations 402a-d are presented, each with a corresponding showerhead 406a-d and showerhead inlet valve 405a-d. Each showerhead may be fluidly connected to a reactant delivery system 401. In certain embodiments, each showerhead may include an RF generator to which RF power may be provided in order to generate a plasma (a fill pattern indicating the flow of RF power to the showerhead). In FIG. 4A , a gap fill process has been performed simultaneously in each of the stations 402a-d. In stations 402a-b, dielectric material 407a-b has been deposited to a target fill depth 411, while stations 402c-d are filled with dielectric material 407c-d below the target fill depth 411. This fill difference may be consistent between stations 402a-b and stations 402c-d, i.e., stations 402c-d consistently underfill over repeated runs across different substrates, indicating that the fill variation is not related to any wafer-to-wafer variation.

FIG. 4B illustrates a method of correcting this fill difference by performing additional deposition in stations 402c-d but not in stations 402a-b. In stations 402c-d, RF power is still provided to generate plasma (as illustrated by the dot pattern on showerheads 406c-d), while RF power is not provided to stations 402a-b. Similarly, reactant flow to stations 402c-d may be maintained, but reactant does not flow to stations 402a-b (as illustrated by the gaps in the fill pattern below showerhead inlet valves 405a-b). Showerhead inlet valves 405a-b may be closed to inhibit the flow of gas to stations 402a-b. As reactant flow and plasma power are provided to stations 402c-d but not to stations 402a-b, additional dielectric material is deposited on the substrate in stations 402c-d, resulting in deposition of dielectric material 409c-d deposited to a target fill depth 411, matching the depth of the fill and dielectric material 407a-b in stations 402a-b. In some embodiments, additional growth cycles are performed in stations 402c-d but not in stations 402a-b. For example, in FIG. 4B, 50 growth cycles may be performed in stations 402a-b and 60 growth cycles may be performed in stations 402c-d, wherein despite the difference in the total number of growth cycles, the same total depth of dielectric fill is exhibited in the substrate at all stations. During the 10 additional growth cycles performed in stations 402c-d, no deposition occurred in stations 402a-b.

In some embodiments, both RF power and reactant flow may not be provided to stations 402a-b. In other embodiments, only RF power or only reactant flow to certain stations may be stopped. In some embodiments, the deposition process is a plasma enhanced process such that in the absence of plasma, the reactants will not deposit or interact meaningfully with the substrate in the chamber. Thus, even if the reactants are flowing, the lack of plasma still results in no deposition, inhibition, or etching process. In some embodiments, not providing RF power to the stations may be preferred to stopping reactant flow because stopping the flow of reactants to one or more stations may affect the flow of reactants to other stations, which is undesirable.

Alternatively, in certain embodiments, the flow of reactants to one or more stations may be stopped. This may be performed in embodiments where deposition may occur without plasma, such as a thermal deposition process. In certain embodiments, the stations may not be able to sufficiently cool below the thermal deposition temperature without expensive or time consuming processes. In the absence of reactants, deposition from such reactants will not occur.

In embodiments where RF power and/or reactant flow to one or more stations is stopped, the RF power and/or reactant flow may be appropriately adjusted to account for the remaining stations where deposition processes may still be performed. For example, in certain embodiments, the RF power for a four-station chamber such as that shown in FIG. 4A may be approximately 7000 W, with each station receiving approximately 1250 W. In FIG. 4B , the RF power may be adjusted to 2700 W, with each station still receiving approximately 1250 W, taking into account that RF power is only provided to two stations. Similar changes may be made to reactant flow to maintain similar per-station flow rates when performing deposition in two stations as when depositing in four stations.

FIG5 shows an example of a process sequence that may be used in accordance with the disclosed embodiments. FIG5 may disclose operations having the same reference numbers as disclosed above with respect to FIG3. When the same reference numbers are used, the same or similar operations may be performed.

The process sequence of FIG. 5 includes treating a substrate using a suppressed plasma. Other operations (e.g., soaking) may be omitted in certain embodiments and operations may be added in certain embodiments. In the exemplary process sequence of FIG. 5, one or more wafers undergo gapfill. The process may begin with a soak (302) after being provided to a deposition chamber. This may be beneficial, for example, for particle removal or other pre-processing. Then, an n1 cycle of ALD deposition of a liner is performed (304). Further details of liner ALD are discussed below.

In the operation showing the first suppression block ( n =1), n suppression blocks are performed after depositing the optional liner. The first operation is a suppression plasma (308) for surface treatment. As discussed above, the plasma may include halogen species containing anion and radical species, such as F- ^, Cl- ^, I- ^, Br- ^, fluorine radicals, etc. Other suppression plasmas may be used. In some embodiments, the suppression plasma is generated from a non-halogenated species, including a nitrogen-containing non-halogenated species. For example, plasma generated from molecular nitrogen ( _N2 ), molecular hydrogen ( _H2 ), ammonia ( _NH3 ), amines, diols, diamines, amine alcohols, thiols, halides, halides, HF, fluorine-containing species, chlorine-containing species, iodine-containing species, or combinations thereof can be used as the suppression plasma.

When the plasma is inhibited from interacting with the material in the feature, due to geometric shielding effects, the material at the bottom of the feature receives less plasma treatment than the material located closer to the top of the feature or in the field area. Therefore, deposition at the top of the feature is selectively inhibited, while deposition in the lower portion of the feature proceeds in a less inhibited or uninhibited manner. In Figure 5, the next operation in the inhibit block is an n2 cycle of ALD fill (310). Dielectric material is selectively deposited at the bottom of the feature. In some embodiments, the n2 cycle of ALD fill may include at least one ALD cycle, at least about 10 ALD cycles, or between 1 and about 15 ALD cycles. The n2 cycles of suppressing the plasma and ALD fill together form the growth cycle. This cycle can be repeated n3 times to continue filling the feature with intermittent suppression as the suppression effect wears off.

In certain embodiments, additional growth cycles may be performed on a subset of sites in a tool (313). As described above, one or more sites in a tool may have a lower deposition rate causing features of a substrate in that site to be underfilled relative to other sites. Such a substrate may have gaps with a lower fill depth of dielectric material than substrates in different sites. Additional growth cycles may be performed in such underfilled sites. This may be accomplished by suppressing RF power or reactant flow to other sites so that only the subset of sites will be filled with additional dielectric material during a subsequent growth cycle. Additional growth cycles do not result in additional dielectric material deposition in sites not included in the subset of sites.

In some embodiments, an additional n2 cycles of ALD fill are performed in a subset of the sites. For example, n2 cycles of ALD fill can be performed in all sites during 310, and an additional number of ALD cycles can be performed in a subset of the sites.

In certain embodiments, additional growth cycles may be performed for a subset of sites during each inhibition block. As mentioned above, each inhibition block may be characterized by an IED, which is the depth above which deposition is inhibited. If the gap is not fully filled before the end of an inhibition block, voids may form during a subsequent inhibition block due to pinching effects. This may occur when the subsequent inhibition block will have a higher IED, so that deposition in the gap may occur higher. Because deposition will proceed from the side walls toward the center of the feature, reactants may not be able to diffuse to the bottom of the feature to be completely filled with dielectric material due to film growth at higher depths within the feature.

To avoid such clamping, in some embodiments, additional ALD cycles or growth cycles may be performed in each inhibiting block in a subset of sites. In some embodiments, each site may have substantially the same fill depth of the substrate between inhibiting blocks. Thus, in some embodiments, additional n2 cycles may be performed in a subset of sites, such as additional ALD cycles. In some embodiments, additional n3 cycles may be performed in a subset of sites, such as additional inhibiting plasma treatments and ALD cycles.

In many embodiments, the subset of sites may be one, two, or three sites in a four-site tool. A tool may also have more or fewer than four sites; in some embodiments, a tool has at least two sites, with additional growth cycles performed in only one site. Additional growth cycles may be performed until the fill depth in the subset of sites is substantially similar to the fill depth in sites that are not part of the subset of sites.

In the example of FIG. 5 , the inhibition block ends with a passivation operation ( 312 ). In some embodiments, a passivation operation may not be performed in each inhibition block. Passivation is a surface treatment that removes residual inhibitors and may also densify the deposited film. In some embodiments, hydrogen and/or oxygen plasma is used.

One or more additional inhibition blocks including growth cycles and passivation may be performed for a total of n inhibition blocks (314). The number of inhibition blocks depends on how much material is used to fill the feature. The inhibition plasma, ALD, and passivation conditions may be varied between inhibition blocks used to fill the feature and inhibition blocks. For example, the inhibition plasma duration may be 20 seconds until the bottom quarter of the feature is filled (inhibition block 1), then changed to 5 seconds for the middle 50% of the structure (inhibition block 2), and so on. Each inhibition block may have a different IED, where the process parameters of the inhibition plasma treatment for the inhibition block are varied to target the different IEDs. Each inhibition block may fill a portion of the feature below the IED of that inhibition block.

In some embodiments, additional inhibit blocks may be performed on a subset of sites. Similar to operation 311 above, additional inhibit blocks may be performed on a subset of sites, including inhibiting plasma, ALD gap fill, and passivation. Additional inhibit blocks are not performed on sites that are not part of the subset of sites, such that additional inhibit blocks are performed only on the subset of sites.

When the feature is nearly full, inhibition may no longer be required and the fill may be completed using an n4 cycle of ALD fill (316). In some embodiments, an optional capping or blanketing layer of dielectric may then be deposited (318). Plasma enhanced chemical vapor deposition (PECVD) may be used at this stage for rapid deposition.

ALD is a technique for sequentially depositing thin layers of material. The ALD process uses surface-mediated deposition reactions to cyclically deposit films on a layer-by-layer basis. The concept of an ALD "cycle" is relevant to the discussion of many embodiments herein. Typically, a cycle is a minimum set of operations used to perform a surface deposition reaction. The result of a cycle is the production of at least a partial silicon-containing film layer on the substrate surface. Typically, an ALD cycle includes the operation of transporting and adsorbing at least one reactant to the substrate surface, and then reacting the adsorbed reactant with one or more reactants to form a partial film layer. The cycle may include certain auxiliary operations, such as cleaning one of the reactants or byproducts and/or treating a portion of the film that has just been deposited. Typically, a cycle includes an instance of a specific sequence of operations.

As an example, an ALD cycle may include the following operations: (i) delivery/adsorption of precursors, (ii) purging of the chamber from precursors, (iii) delivery of a second reactant and optional plasma ignition, and (iv) purging of the chamber from byproducts. The reaction between the second reactant and the adsorbed precursor to form a film on the surface of the substrate affects the film composition and properties, such as non-uniformity, stress, wet etch rate, dry etch rate, electrical properties (such as breakdown voltage and leakage current), etc.

In one example of an ALD process, a substrate surface including a group of surface active sites is exposed to a vapor phase distribution of a first precursor, such as a silicon-containing precursor, in a dose supplied to a chamber containing the substrate. Molecules of the first precursor are adsorbed onto the substrate surface, including chemically adsorbed species and/or physically adsorbed molecules of the first precursor. When a compound is adsorbed onto the substrate surface as described herein, the adsorption layer may include the compound and derivatives of the compound. For example, the adsorption layer of the silicon-containing precursor may include the silicon-containing precursor and derivatives of the silicon-containing precursor. After the first precursor dose, the chamber is then evacuated to remove most or all of the first precursor that is still in the vapor phase, so that most or only the adsorbed species remain. In some embodiments, the chamber may not be completely evacuated. For example, the reactor can be evacuated so that the partial pressure of the first precursor in the gas phase is low enough to reduce the reaction. A second reactant, such as an oxygen-containing gas or a nitrogen-containing gas, is introduced into the chamber so that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed first precursor. In other embodiments, the second reactant reacts only when an activation source, such as a plasma, is applied temporarily. The chamber is then evacuated again to remove unbound second reactant molecules. As described above, in some embodiments, the chamber may not be completely evacuated. Additional ALD cycles may be used to build film thickness.

FIG. 6 presents a process flow diagram for a single plasma enhanced ALD cycle, which may be implemented as part of operations 304, 310, and/or 316 shown in FIG. 3. In operation 602, a substrate is exposed to a silicon-containing precursor to adsorb the precursor onto a surface of a feature. This operation may be self-limiting. In certain embodiments, the precursor adsorbs at least at all active sites on the surface of the feature. In operation 604, the process chamber is optionally purged to remove any unadsorbed silicon-containing precursor. In operation 606, the substrate is exposed to a plasma produced from a co-reactant. Examples include O ₂ and/or N ₂ O to form a silicon oxide layer or a silicon oxynitride layer, N ₂ or NH ₃ to form a silicon nitride layer, methane (CH ₄ ) to produce a silicon carbide layer, etc. In operation 608 , the process chamber is optionally purged to remove byproducts from the reaction between the silicon-containing precursor and the oxidant. Operations 602 to 608 are repeated for multiple cycles to deposit the silicon-containing layer in the feature to a desired thickness.

It should be noted that the processes described herein are not limited to a particular reaction mechanism. Thus, the process described with respect to FIG. 4 includes all deposition processes that use sequential exposure to a silicon-containing reactant and a conversion plasma, including those that are not strictly self-limiting. The process includes a sequence in which one or more gases used to generate the plasma are continuously flowed throughout the process with intermittent plasma ignition.

In certain embodiments, the suppressed plasma treatment may be performed at a pressure greater than about 1 Torr, at least about 10 Torr, at least about 15 Torr, at least about 20 Torr, between about 10 Torr and about 30 Torr, or between about 15 Torr and 30 Torr.

The duration of the suppressed plasma treatment may be between about 0.3 seconds and about 60 seconds, between about 0.3 seconds and about 30 seconds, at least about 0.3 seconds, at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 20 seconds, or at least about 30 seconds. Suppressed plasma treatments using halogen-containing species may generally be performed for shorter durations than halogen-free species because halogen-containing species may passivate the surface more efficiently than halogen-free species.

The suppressed plasma treatment may be used for a variety of aspect ratios and structure depths. In certain embodiments, the suppressed plasma treatment may be used for low aspect ratio structures. The low aspect ratio structures may have an aspect ratio of between about 3:1 and about 7:1, less than about 10:1, between about 3:1 and about 10:1, between about 3:1 and about 15:1, or less than about 15:1. The low aspect ratio structures may have a depth of at least about 100 nm, at least about 1 µm, at least about 2 µm, or at least about 3 µm.

In some embodiments, the IED may be characterized as a percentage, for example, 30% IED means an inhibition effective depth of 30% of the total depth of the feature. Thus, if a feature has a depth of 1 µm, 30% IED means that deposition is inhibited along the sidewall surface of the feature within 300 nm from the top of the feature, and is not inhibited for the rest of the depth. In some embodiments, the IED for inhibiting plasma treatment according to embodiments described herein may be about 20%, about 30%, about 40%, about 50%, about 60%, or about 70%.

In some embodiments, the structure can have variable concave features. In some embodiments, the critical size within the gap at any particular depth can vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%. In some embodiments, the size of the concave feature can vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%, where the size can be based on the difference between the critical size at the narrowest portion of the concave feature and the critical size at the widest portion. In some embodiments, the depth of the concave feature can vary by at least about 5%, at least about 10%, at least about 15%, at least about 20%, or between about 10% and about 20%.

In some embodiments, the ratio of the inhibiting species to the inert gas may be about 1:5, about 1:10, between about 1:10 and about 1:20, between about 1:100 and about 1:700, or between about 1:5 and about 1:7000. In general, increasing the proportion of the gas flow of the inhibiting species, such as _NF3, increases the inhibitory effect of exposing the substrate to the inhibiting plasma. Similarly, decreasing the proportion of the gas flow of the inhibiting species by modifying the flow of either the inhibiting species or the inert gas will reduce the inhibitory effect. In some embodiments, the flow of the non-halogenated species, such as _N2, may be between 10 slm and about 100 slm. In some embodiments, the inert gas may be co-flowed with the inhibiting species. The inert gas may include helium, argon, xenon, or other gases that do not react with other species in the gas or substrate surface. When an inert gas is used, its flow rate may be between about 3.5 and about 15 slm or between about 10 slm and about 40 slm. In some embodiments, an oxygen-containing or hydrogen-containing species may be co-flowed with the species used for inhibition. If the species used for inhibition includes nitrogen atoms, the nitrogen atoms may react with the silicon-containing precursor or the silicon film to form silicon nitride. The addition of oxygen-containing or hydrogen-containing species may inhibit the conversion of silicon oxide or silicon to silicon nitride, respectively. In some embodiments, the co-flow rate of oxygen-containing or hydrogen-containing species may be at least about 100 sccm, or between about 0 and about 5 slm.

In many embodiments, the plasma is an in-situ plasma such that the plasma is formed directly above the surface of the substrate in the station. In some embodiments, an exemplary power per substrate area for the in-situ plasma is between about 0.2122 W/cm ² and about 2.122 W/cm ^2. For example, for a chamber processing four 300 mm wafers, the power may range from about 1000 W to about 8000 W. In some embodiments, for four 300 mm wafers, the power may be between about 2700 W and about 8000 W. The plasma for the ALD process may be generated by applying a radio frequency (RF) field to the gas using two capacitively coupled plates. The plasma is ignited between the two plates by ionization of the gas by the RF field, and free electrons are generated in the plasma discharge region. These electrons are accelerated by the RF field and can collide with gas phase reactant molecules. The collisions of these electrons with reactant molecules can form free radical species that participate in the deposition process. It should be understood that the RF field can be coupled via any suitable electrodes. Non-limiting examples of electrodes include process gas distribution showerheads and substrate support pedestals. It should be understood that the plasma used in the ALD process can be formed by one or more suitable methods other than capacitive coupling of the RF field to the gas. In some embodiments, the plasma is a remote plasma, so that the second reactant is ignited in a remote plasma generator upstream of the station and then transported to the station where the substrate is located.

To deposit the silicon-containing film, one or more silicon-containing precursors may be used. In some examples, the silicon-containing precursors may include silanes (e.g., SiH ₄ ), polysilanes where n ≥ 1 (H ₃ Si-(SiH ₂ ) _n -SiH ₃ ), organic silanes, halogenated silanes, amino silanes, alkoxy silanes, and the like. Examples of organic silanes include methylsilane, ethylsilane, isopropylsilane, tertiary butylsilane, dimethylsilane, diethylsilane, bis-tertiary butylsilane, acrylsilane, dibutylsilane, tert-hexylsilane, isopentylsilane, tertiary butyldisilane, bis-tertiary butyldisilane, and the like.

Halogenated silanes include at least one halogen group and may or may not include hydrogen and/or carbon groups. Examples of halogenated silanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tributylchlorosilane, bis-tributylchlorosilane, chloroisopropylsilane, chloro-dibutylsilane, tributyldimethylchlorosilane, tert-hexyldimethylchlorosilane, and the like.

Aminosilanes include at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilanes ( _H3Si ( _NH2 ), _H2Si ( _NH2 ) ₂ , HSi( _NH2 ) ₃ and Si( _NH2 ) ₄ , respectively), and substituted mono-, di-, tri- and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane ( _SiH2 (NHC( _CH3 ) ₃ ) ₂ ) (BTBAS), tert-butylsilylcarbamate, SiH( _CH3 )-(N( _CH3 ) ₂ ) ₂ , SiHCl-(N( _CH3 ) ₂ ) ₂ , (Si( _CH3 ) _2NH ) ₃ , di(isopropylamido)silane (DIPAS), di(dibutylamido)silane (DSBAS), SiH ₂ [N(CH ₂ CH ₃ ) ₂ ] ₂ (BDEAS), etc. A further example of an aminosilane is trisilylamine (N(SiH ₃ )). In certain embodiments, aminosilanes having two or more amine groups attached to the central silicon atom may be used. These aminosilanes may cause less damage than those having only a single amine group attached.

Further examples of silicon-containing precursors include trimethylsilane (3MS); ethylsilane; butasilane; pentasilane; octasilane; heptasilane; hexasilane; cyclobutasilane; cycloheptasilane; cyclohexasilane; cyclooctasilane; cyclopentasilane; 1,4-dioxa-2,3,5,6-tetrasilacyclohexane; diethoxymethylsilane (DEMS); diethoxysilane (DES) ; dimethoxymethylsilane; dimethoxysilane (DMOS); methyldiethoxysilane (MDES); methyldimethoxysilane (MDMS); octamethoxydodecylsiloxane (OMODDS); tert-butoxydisilane; tetramethylcyclotetrasiloxane (TMCTS); tetramethylcyclotetrasiloxane (TOMCTS); triethoxysilane (TES); triethoxysiloxane (TRIES); and trimethoxysilane (TMS or TriMOS).

In some embodiments, the silicon-containing prodrug may include siloxane or amino-containing siloxane. In some embodiments, the siloxane used herein has the general formula of X(R ¹ ) _a Si—O—Si(R ² ) _b Y, wherein a and b are integers from 0 to 2, and X and Y may be independently H or NR ³ R ⁴ , wherein each of R1, R2, R3 and R4 is hydrogen, an unbranched alkyl group, a branched alkyl group, a saturated heterocyclic group, an unsaturated heterocyclic group, or a combination thereof. In some embodiments, when at least one of X or Y is NR ³ R ⁴ , R3 and R4 and the atoms to which they are attached may form a saturated heterocyclic compound together. In certain embodiments, the silicon-containing precursor is a pentamethylated amine-containing siloxane or a dimethylated amine-containing siloxane. Examples of amino-containing siloxanes include: 1-diethylamino-1,1,3,3,3-pentamethyldisiloxane, 1-diisopropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-dipropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-n-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-sec-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylethylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylpropylamino-1,1,3,3,3-pentamethyldisiloxane, 1 N-Methylbutylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-tert-butylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-piperidinyl-1,1,3,3,3,-pentamethyldisiloxane, 1-dimethylamino-1,1-dimethyldisiloxane, 1-diethylamino-1,1-dimethyldisiloxane, 1-diisopropylamino-1,1-dimethyldisiloxane, 1-dipropylamino-1,1-dimethyldisiloxane, 1-di-n-butylamino-1,1-dimethyldisiloxane, 1-di-sec-butylamino-1,1-dimethyldisiloxane, 1-N-methylethylamino-1,1-dimethyldisiloxane, 1-N Methylpropylamino-1,1-dimethyldisiloxane, 1-N-methylbutylamino-1,1-dimethyldisiloxane, 1-piperidinyl-1,1-dimethyldisiloxane, 1-tert-butylamino-1,1-dimethyldisiloxane, 1-dimethylamino-disiloxane, 1-diethylamino-disiloxane, 1-diisopropylamino-disiloxane, 1-dipropylamino-disiloxane, 1-di-n-butylamino-disiloxane, 1-di-sec-butylamino-disiloxane, 1-N- Methylethylamino-disiloxane, 1-N-methylpropylamino-disiloxane, 1-N-methylbutylamino-disiloxane, 1-piperidinyl-disiloxane, 1-tert-butylamino-disiloxane, and 1-dimethylamino-1,1,5,5,5,-pentamethyldisiloxane.

In the case where the deposited film includes oxygen, an oxygen-containing reactant may be used. Examples of oxygen-containing reactants include, but are not limited to, oxygen (O ₂ ), ozone (O ₃ ), nitrous oxide (N ₂ O), nitric oxide (NO), nitrogen dioxide (NO ₂ ), nitrogen trioxide (N ₂ O ₃ ), nitrogen tetroxide (N ₂ O ₄ ), nitrogen pentoxide (N ₂ O ₅ ), carbon monoxide (CO), carbon dioxide (CO ₂ ), sulfur oxides (SO), sulfur dioxide (SO ₂ ), oxygen-containing hydrocarbons (C _x H _y O _z ), water (H ₂ O), formaldehyde (CH ₂ O), carbonyl sulfide (COS), mixtures thereof, and the like.

In cases where the deposited film includes nitrogen, nitrogen-containing reactants may be used. The nitrogen-containing reactant comprises at least one nitrogen, for example, nitrogen _{( N2} ), ammonia (NH3), hydrazine ( _N2H4 ), an amine (e.g., an amine _with carbon) such as _methylamine ( _CH5N ), _{dimethylamine} (( _CH3 ) _2NH ), _ethylamine (C2H5NH2), isopropylamine (C3H9N), _tert -butylamine (C4H11N), _{di - tert} -butylamine (C8H19N), _{cyclopropylamine} (C3H5NH2), sec-butylamine ( _{C4H11N )} , _{cyclobutylamine} (C4H7NH2), isoamylamine ( _C5H13N ) _{, 2 - methylbutan - 2} - _amine ( _{C5H13N )} , _{trimethylamine} (C3H9N), _{diisopropylamine} ( _C6H15N ) _, N), diethylisopropylamine (C ₇ H ₁₇ N), di-tert-butylhydrazine (C ₈ H ₂₀ N ₂ ), and aromatic amines such as aniline, pyridine, and benzylamine. The amines can be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). The nitrogen-containing reactant can contain impurities other than nitrogen. For example, hydroxylamine, tert-butyloxycarbonylamine, and N-tert-butylhydroxylamine are nitrogen-containing reactants. Other examples include N _x O _y compounds such as nitrous oxide (N ₂ O), nitric oxide (NO), nitrogen dioxide (NO ₂ ), nitrogen trioxide (N ₂ O ₃ ), nitrogen tetroxide (N ₂ O ₄ ) and/or nitrogen pentoxide (N ₂ O ₅ ). Equipment

FIG. 7 schematically illustrates an embodiment of a process station 700 that may be used to deposit materials using atomic layer deposition (ALD) and/or chemical vapor deposition (CVD), either of which may be plasma enhanced. For simplicity, process station 700 is depicted as a stand-alone process station having a process chamber body 702 for maintaining a low pressure environment. However, it should be understood that a plurality of process stations 700 may be included in a common process tool environment. Furthermore, it should be understood that in certain embodiments, one or more hardware parameters of process station 700, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers 750.

The process station 700 is in fluid communication with a reactant delivery system 701 for delivering process gases to a distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 for mixing and/or conditioning process gases for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 may control the introduction of process gases to the mixing vessel 704. Similarly, a showerhead inlet valve 705 may control the introduction of process gases to the showerhead 706. In certain embodiments, suppressants or other gases may be delivered directly to the chamber body 702. One or more mixing vessel inlet valves 720 may control the introduction of process gases to the mixing vessel 704. These valves may be controlled depending on whether process gases, suppressant gases, or carrier gases may be opened during various operations. In certain embodiments, the inhibition gas may be produced by using an inhibition liquid and vaporization using a heated vaporizer.

As an example, the embodiment of Figure 7 includes a vaporization point 703, which is used to vaporize liquid reactants to be supplied to a mixing vessel 704. In some embodiments, the vaporization point 703 may be a heated vaporizer. The reactant vapors produced by such a vaporizer may condense in the downstream delivery line. Exposure of incompatible gases to the condensed reactants may produce small particles. These small particles may block the pipeline, interfere with valve operation, contaminate the substrate, etc. Some methods for dealing with these problems involve purging and/or evacuating the delivery line to remove residual reactants. However, purifying the delivery line may increase the process station cycle time and reduce the process station throughput. Therefore, in some embodiments, the delivery line downstream of the vaporization point 703 may be heat traced. In some examples, the mixing vessel 704 may also be heat traced. In one non-limiting example, the piping downstream of the vaporization point 703 has a gradual temperature profile extending from about 100°C to about 150°C at the mixing vessel 704.

In certain embodiments, the reactant liquid may be vaporized at the liquid injector. For example, the liquid injector may inject a pulse of the liquid reactant into a carrier gas stream upstream of the mixing vessel. In one scenario, the liquid injector may vaporize the reactant by rapidly moving the liquid from a higher pressure to a lower pressure. In another scenario, the liquid injector may atomize the liquid into dispersed droplets that are then vaporized in a heated transport line. It should be understood that smaller droplets may vaporize faster than larger droplets, shortening the delay between liquid injection and complete vaporization. Faster vaporization may reduce the length of the pipeline downstream of the vaporization point 703. In one scenario, the liquid injector may be mounted directly to the mixing vessel 704. In another scenario, the liquid injector can be mounted directly to the showerhead 706.

In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 703 to control the mass flow rate of the liquid used for vaporization and delivery to the process station 700. For example, the liquid flow controller may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller electrically connected to the MFM. However, using feedback control may take a second or more for the liquid flow to stabilize. This may extend the time taken to inject the liquid reactant. Therefore, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this may be done by dynamically switching the LFC from a feedback control mode to a direct control mode by deactivating the sensing tube and PID controller of the LFC.

The showerhead 706 distributes process gases toward a substrate 712. In the embodiment shown in FIG7 , the substrate 712 is located below the showerhead 706 and is shown as being disposed on a pedestal 708. It should be understood that the showerhead 706 may have any suitable shape and may have any suitable number and configuration of ports for distributing process gases to the substrate 712.

In some embodiments, microvolume 707 is located below showerhead 706. Performing ALD and/or CVD in a microvolume of a process station rather than in the entire volume can reduce reactant exposure and purge time, reduce time used to change process conditions (e.g., pressure, temperature, etc.), limit exposure of process station robots to process gases, etc. Exemplary microvolume sizes include, but are not limited to, volumes between 0.1 liters and 2 liters. This microvolume also affects production throughput. Although the deposition rate per cycle is reduced, the cycle time is also reduced simultaneously. In some cases, the latter effect is significant enough to improve the overall throughput of the module for a given target film thickness.

In some embodiments, the pedestal 708 may be raised or lowered to expose the substrate 712 to the microvolume 707 and/or to change the volume of the microvolume 707. For example, during a substrate transfer phase, the pedestal 708 may be lowered to allow the substrate 712 to be loaded onto the pedestal 708. During a deposition process phase, the pedestal 708 may be raised to position the substrate 712 within the microvolume 707. In some embodiments, the microvolume 707 may completely surround the substrate 712 and a portion of the pedestal 708 to create a region of high flow impedance during the deposition process.

Optionally, the pedestal 708 may be lowered and/or raised during portions of the deposition process to adjust process pressure, reactant concentration, etc. within the microvolume 707. In a scenario where the process chamber body 702 is maintained at a base pressure during the deposition process, lowering the pedestal 708 may allow the microvolume 707 to be evacuated. Exemplary ratios of microvolume to process chamber volume include, but are not limited to, volume ratios between 1:700 and 1:10. It should be understood that in certain embodiments, the pedestal height may be programmatically adjusted by a suitable computer controller.

In another scenario, adjusting the height of the pedestal 708 may allow the plasma density to be varied during plasma activation and/or treatment cycles included in a deposition process. At the end of a deposition process phase, the pedestal 708 may be lowered during another substrate transfer phase to allow removal of the substrate 712 from the pedestal 708.

Although the exemplary micro-volume variations described herein refer to a height-adjustable pedestal 708, it should be understood that in some embodiments, the position of the showerhead 706 relative to the pedestal 708 can be adjusted to vary the volume of the micro-volume 707. Furthermore, it should be understood that the vertical position of the pedestal 708 and/or showerhead 706 can be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 can include a rotation axis for rotating the orientation of the substrate 712. It should be understood that in some embodiments, one or more of these exemplary adjustments can be programmatically performed by one or more suitable computer controllers.

Returning to the embodiment shown in FIG. 7 , the showerhead 706 and the pedestal 708 are in electrical communication with an RF power source 714 and a matching network 716 for supplying energy to the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse time. For example, the RF power source 714 and the matching network 716 may be operated at any suitable power to form a plasma having a desired composition of free radical species. Examples of suitable powers are included above. Similarly, the RF power source 714 may provide RF power at any suitable frequency. In some embodiments, the RF power source 714 may be configured to control high frequency and low frequency RF power sources independently of each other. Exemplary low frequency RF frequencies may include, but are not limited to, frequencies between 50 kHz and 700 kHz. Exemplary high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It should be understood that any suitable parameter may be modulated discretely or continuously to provide plasma energy for surface reactions. In a non-limiting example, the plasma power may be intermittently pulsed to reduce ion bombardment of the substrate surface relative to a continuously powered plasma.

In some embodiments, the plasma may be monitored in situ by one or more plasma monitors. In one scenario, the plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, the plasma density and/or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of the plasma power. It should be understood that in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

In some embodiments, the plasma may be controlled via input/output control (IOC) sequence instructions. In one example, instructions for setting plasma conditions for a plasma process phase may be included in a corresponding plasma activation recipe phase of a deposition process recipe. In some cases, the process recipe phases may be configured sequentially so that all instructions for a deposition process phase are executed synchronously with that process phase. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe phase prior to the plasma process phase. For example, a first recipe phase may include instructions for setting the flow rate of an inert and/or reactant gas, instructions for setting a plasma generator to a power set point, and time delay instructions for the first recipe phase. The subsequent second recipe phase may include instructions for executing the plasma generator and time delay instructions for the second recipe phase. The third recipe phase may include instructions for deactivating the plasma generator and time delay instructions for the third recipe phase. It should be understood that these recipe phases may be further divided and/or iterated in any suitable manner within the scope of the present disclosure.

In some deposition processes, the plasma impulse lasts for a duration of about a few seconds or longer. In some embodiments, much shorter plasma impulses may be used. These times may be from 10 milliseconds to 1 second, typically about 20 to 80 milliseconds, and a specific example is 50 milliseconds. Such very short RF plasma impulses require extremely fast plasma stabilization. To achieve this goal, the plasma generator can be configured so that the impedance match is preset to a specific voltage, while the frequency is allowed to float. Known high frequency plasmas are generated at an RF frequency of about 13.56 MHz. In many embodiments disclosed herein, the frequency is allowed to float to values different from this standard value. By allowing the frequency to float while fixing the impedance match to a predetermined voltage, the plasma can settle more quickly, a result that can be important when using very short plasma bursts associated with certain types of deposition cycles.

In some embodiments, the temperature of the table 708 can be controlled via a heater 710. Furthermore, in some embodiments, pressure control of the deposition process station 700 can be provided by a butterfly valve 718. As shown in the embodiment of FIG. 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 700 can also be adjusted by varying the flow rate of one or more gases introduced into the process station 700.

FIG8 is a block diagram of a processing system suitable for performing thin film deposition processes according to certain embodiments. System 800 includes a transport module 803. Transport module 803 provides a clean, pressurized environment to minimize the risk of contamination of substrates being processed as they are moved between multiple reactor modules. Mounted on transport module 803 are two multi-station reactors 809 and 810, each of which is capable of performing atomic layer deposition (ALD) and/or chemical vapor deposition (CVD) according to certain embodiments. Reactors 809 and 810 may include multiple stations 811, 813, 815, and 817 that may perform operations sequentially or non-sequentially according to the disclosed embodiments. These stations may include a heated pedestal or substrate support, one or more gas inlets or showerheads, or a dispersion plate.

Also mounted on the transport module 803 may be one or more single or multi-station modules 807 capable of performing plasma or chemical (non-plasma) pre-clean, or any other process described with respect to the disclosed method. Module 807 may in some cases be used for a number of processes to, for example, prepare a substrate for a deposition process. Module 807 may also be designed/configured to perform a number of other processes, such as etching or polishing. The system 800 also includes one or more wafer source modules 801, which are storage locations for wafers before and after processing. An atmosphere robot (not shown) in an atmosphere transport chamber 819 may first move the wafers out of the source module 801 into a load lock 821. The wafer transfer device (usually a robot arm unit) in the transfer module 803 moves the wafer from the load lock 821 to a module mounted on the transfer module 803 .

In many embodiments, a system controller 829 is used to control process conditions during deposition. The controller 829 typically includes one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.

The controller 829 controls all activities of the deposition equipment. The system controller 829 executes system control software, including a set of instructions for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or stage position, and other parameters of a particular process. Other computer programs stored on a memory device associated with the controller 829 may be used in some embodiments.

There is typically a user interface associated with the controller 829. The user interface may include a display screen, a graphical software display of equipment and/or process conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, etc.

The system control logic may be configured in any suitable manner. In general, the logic may be designed or configured in hardware and/or software. Instructions for controlling the drive circuits may be hard-coded or provided as software. Instructions may be provided by "programming." Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices having specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general purpose processor. The system control software may be coded in any suitable computer readable programming language.

Computer program code for controlling the inhibitory species flow, RF power, hydrogen flow, oxygen flow, and silicon-containing precursor flow, as well as other processes in a process sequence, may be written in any known computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or other programming languages. The compiled object code or script is executed by a processor to perform the tasks identified in the program. As also indicated, the program code may be hard-coded.

Controller parameters are related to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of recipes and can be input using a user interface. Signals for monitoring the process can be provided via analog and/or digital input connections of the system controller 829. Signals for controlling the process are output on analog and digital output connections of the deposition apparatus 800.

System software may be designed or configured in many different ways. For example, a number of chamber component subroutines or control objects may be written to control the operation of chamber components required to perform deposition processes (and in some cases other processes) in accordance with the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

In some embodiments, a controller, such as controller 750 or 829, is part of a system, which may be part of the examples described above. Such a system may include a semiconductor processing apparatus that includes one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer pedestals, gas flow systems, etc.). Such systems may be integrated with electronic components to control their operation before, during, and after processing of semiconductor wafers or substrates. The electronic components may be referred to as "controllers" and may control many components or sub-components of one or more systems. Depending on the processing conditions and/or type of system, the controller 829 can be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in certain systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and/or load locks connected to or interfaced with a particular system.

Broadly speaking, a controller may be defined as an electronic component having integrated circuits, logic, memory, and/or software that receives commands, issues commands, controls operations, performs cleaning operations, performs end-point measurements, and so forth. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions that are sent to the controller in the form of individual settings (or program files) that define operating parameters for executing a particular process on a semiconductor wafer or to a semiconductor wafer or to a system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to perform one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or die of a wafer.

In some embodiments, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be located in the "cloud" or in all or part of a factory host computer system to allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance indicators from multiple manufacturing operations to change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local area network or the Internet. The remote computer may include a user interface that implements the input or programming of parameters and/or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that are used to specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more distributed controllers that are networked together and operate toward a common purpose such as the processes and controls described herein. An example of a distributed controller used for such purposes may be one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., on a stage level or as part of a remote computer) and that combine to control the processes on the chamber.

Without limitation, exemplary systems may include plasma etching chambers or modules, deposition chambers or films, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and/or production of semiconductor wafers.

As mentioned above, depending on the one or more process steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used for material transfer to bring containers of wafers into or out of tool locations and/or load ports in a semiconductor manufacturing facility.

It will be appreciated that a plurality of process stations may be included in a multi-station processing tool environment, such as shown in FIG. 9 , which depicts a schematic diagram of the environment of a multi-station processing tool. Processing equipment 900 employs an integrated circuit fabrication chamber 963 including a plurality of fabrication process stations, each of which may be used to perform processing operations on a substrate held in a wafer holder of a particular process station, such as a pedestal. In the embodiment of FIG. 9 , the integrated circuit fabrication chamber 963 is shown as having four process stations 951, 952, 953, and 954. Other similar multi-station processing equipment may have more or fewer process stations depending on the implementation, and, for example, depending on the level of parallel wafer processing desired, size/space constraints, cost constraints, etc. Also shown in FIG. 9 is a substrate handling robot 975 operable under the control of a system controller 990, which is configured to move a substrate from a wafer cassette (not shown in FIG. 9 ) in a loading port 980 into an integrated circuit fabrication chamber 963 and to one of the process stations 951, 952, 953, and 954.

9 also depicts an embodiment of a system controller 990 for controlling process conditions and hardware states of the processing apparatus 900. The system controller 990 may include one or more memory devices, one or more mass storage devices, and one or more processors as described herein.

The RF subsystem 995 may generate and deliver RF power to the integrated circuit fabrication chamber 963 via the RF input port 967. In a particular embodiment, the integrated circuit fabrication chamber 963 may include input ports in addition to the RF input port 967 (the additional input ports are not shown in FIG. 9 ). Accordingly, the integrated circuit fabrication chamber 963 may utilize eight RF input ports. In a particular embodiment, the process stations 951 to 954 of the integrated circuit fabrication chamber 963 may each utilize a first and a second input port, wherein the first input port may deliver a signal having a first frequency and wherein the second input port may deliver a signal having a second frequency. The use of dual frequencies may produce enhanced plasma characteristics.

As described above, one or more process stations may be included in a multi-station processing tool. FIG. 10 shows a schematic diagram of an embodiment of a multi-station processing tool 1000 having an inbound load lock 1002 and an outbound load lock 1004, one or both of which may include a remote plasma source. A robot 1006 under atmospheric pressure is configured to move substrates or wafers from a cassette loaded through a chamber 1008 into the inbound load lock 1002 through an atmospheric port. The substrate is placed on a pedestal 1012 in the inbound load lock 1002 by the robot 1006, the atmospheric port is closed, and the load lock is pumped back. In the case where the inbound load lock 1002 includes a remote plasma source, the substrate may be exposed to remote plasma treatment in the load lock prior to introduction into the processing chamber 1014. Further, the substrate may also be heated in the inbound load lock 1002, for example to remove moisture and adsorbed gases. Next, a chamber transfer port 1016 leading to the processing chamber 1014 is opened, and another robot 1090 places the substrate into the reactor, placing it on a pedestal at the first station shown in the reactor for processing. Although the embodiment depicted in FIG. 9 includes a load lock, it will be understood that in some embodiments, direct access of the substrate into the process station may be provided. In many embodiments, when the substrate is placed on the pedestal 1012 by the robot 1006, an immersion gas is introduced into the station.

The depicted processing chamber 1014 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 10 . Each station has a heating pedestal (shown as 1018 at station 1), and a gas line inlet. It will be appreciated that in certain embodiments, each process station may have different or multiple purposes. For example, in certain embodiments, a process station may be switchable between suppressed plasma, passivating plasma, ALD, and/or PEALD process modes. Additionally or alternatively, in certain embodiments, the processing chamber 1014 may include one or more matched pairs of ALD and plasma enhanced ALD process stations. Although the depicted processing chamber 1014 includes four stations, it will be appreciated that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

FIG. 10 depicts an embodiment of a wafer handling system 1090 for transferring substrates within a processing chamber 1014. In some embodiments, the wafer handling system 1090 may transfer substrates between multiple process stations and/or between a process station and a load lock. It will be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer turntable and a wafer handling robot. FIG. 10 also depicts an embodiment of a system controller 1050 for controlling process conditions and hardware states of the processing tool 1000. The system controller 1050 may include one or more memory devices 1056, one or more mass storage devices 1054, and one or more processors 1052. The processor 1052 may include a CPU or computer, analog and/or digital input/output connections, a stepper motor controller board, etc. In some embodiments, the system controller 1050 includes machine-readable instructions for performing operations such as those described herein.

In certain embodiments, a system controller 1050 controls the activities of the processing tool 1000. The system controller 1050 executes system control software 1058 stored in a mass storage device 1054, loaded into a memory device 1056, and executed on a processor 1052. Alternatively, the control logic may be hard-coded in the controller 1050. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally comparable hard-coded logic may be used in its place. The system control software 1058 may include instructions for controlling the timing, gas mixtures, gas flow rates, chamber and/or station pressures, chamber and/or station temperatures, substrate temperatures, target power levels, RF power levels, substrate stages, chuck and/or carrier positions, and other parameters of a particular process performed by the processing tool 1000. The system control software 1058 may be configured in any suitable manner. For example, a plurality of process tool component subroutines or control objects may be written to control the operation of process tool components used to perform a plurality of processing tool processes. The system control software 1058 may be coded in any suitable computer readable programming language. Conclusion

Although certain details of the foregoing embodiments have been described for the purpose of clarity of understanding, it will be apparent that certain variations and modifications may be practiced within the scope of the accompanying claims. The embodiments disclosed herein may be practiced without some or all of these specific details. In other cases, well-known process operations are not described in detail to avoid unnecessary confusion with the disclosed embodiments. Furthermore, although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

101,105: Steps 200a,200b,200c,200d: Structures 201,203,205,207,211,213,215,217: Stages 202: Apertures 204a-1,204a-2,204b,204c-1,204c-2,204d: Inhibition Effective Depth (IED) Lines 206: Gap 208a,208b,208c,208d: Recessed Features 210a,210b,210c,210d: Dielectric Materials 302,304,308,310,311,312,313,314,316,318: Operations 401: Reactant delivery system 402a,402b,402c,402d: Station 405a,405b,405c,405d: Shower head inlet valve 406a,406b,406c,406d: Shower head 407a,407b,407c,407d,409c,409d: Dielectric material 411: Target fill depth 700: Process station 701: Reactant delivery system 702: Process chamber body 703: Vaporization point 704: Mixing vessel 705: Shower head inlet valve 706: Shower head 707: Micro volume 708: Base 710: Heater 712: Substrate 714: RF power source 716: Matching network 718: Butterfly valve 720: Mixing container inlet valve 750: Computer controller 800: System 801: Wafer source module 803: Transfer module 807: Single or multi-station module 809,810: Multi-station reactor 811,813,815,817: Station 819: Atmosphere transfer chamber 821: Load lock 829: System controller 900: Processing equipment 951,952,953,954: Processing station 963: IC manufacturing chamber 967: RF input port 975: Substrate handling robot 980: Loading port 990: System controller 995: RF subsystem 1000: Multi-station processing tool 1002: Inbound load lock 1004: Outbound load lock 1006: Robot 1008: Chamber 1012: Pedestal 1014: Processing chamber 1016: Chamber transfer port 1018: Heating pedestal 1050: System controller 1052: Processor 1054: Mass storage device 1056: Memory device 1058: System control software 1090: Wafer handling system (robot)

FIG. 1 presents a flow chart of the operation for an exemplary embodiment.

2A-2D present drawings of exemplary embodiments for reducing void formation in features.

FIG3 presents a flow chart of the operation for an exemplary embodiment.

4A-4B present exemplary graphs of gap fill variation between chambers according to various embodiments herein.

FIG. 5 presents a flow chart of operations for an atomic layer deposition process.

FIG. 6 presents a flow chart of the operation for an exemplary embodiment.

7-10 are schematic diagrams of examples of processing chambers for performing methods according to disclosed embodiments.

200a:Structure

201,203: Stage

202: Porosity

204a-1,204a-2: Inhibition Effective Depth (IED) Line

206: Gap

208a, 208b: Concave feature part

210a: Dielectric materials

Claims (21)

A method for filling gaps, comprising: providing a substrate in a process chamber, the substrate having one or more structures, each structure comprising a gap; and performing a first set of cycles: (a) exposing the substrate to a suppression plasma to suppress deposition on a first portion of each gap, and (b) after (a), depositing a dielectric material in each gap, wherein during a first subset and a second subset of the first set of cycles, exposing the substrate to the suppression plasma is performed for a first duration, and during the second subset of the first set of cycles, at least one non-duration of exposure of the substrate to the suppression plasma is modified as a base parameter. The method of claim 1, wherein the non-continuous time-based parameter is a flow rate of the suppression species, a flow rate of a dilution gas, a pressure, or a radio frequency (RF) power. The method of claim 1, wherein the first subset of the first set of cycles suppresses deposition in the gaps to a greater depth in the gaps than the second subset of the first set of cycles. The method of claim 1, wherein exposing the substrate to the suppressing plasma comprises flowing an suppressing species into the processing chamber, and wherein a flow rate of the suppressing species during the second subset of the first set of cycles is lower than the first subset of the first set of cycles. The method of claim 4, wherein a flow rate difference of the inhibitory species between the first subset of the first set of cycles and the second subset of the first set of cycles is between about 1 sccm and about 5 sccm. The method of claim 1, wherein exposing the substrate to the suppressing plasma comprises co-flowing an suppressing species and an inert gas into the processing chamber, and wherein a ratio of the suppressing species to the inert gas during the second subset of the first set of cycles is higher than the first subset of the first set of cycles. The method of claim 4, wherein the inhibitory species comprises a nitrogen-containing species. The method of claim 1, wherein exposing the substrate to the suppressed plasma comprises providing radio frequency (RF) energy to the processing chamber, and wherein an RF power during the second subset of the first set of cycles is lower than the first subset of the first set of cycles. The method of claim 8, wherein a RF power difference between the first subset of the first set of cycles and the second subset of the first set of cycles is between about 50 W and about 700 W. The method of claim 8, wherein the RF power per substrate is between about 250W and about 1250W. A method as claimed in claim 1, wherein each of the one or more structures has one or more recessed features. A method as claimed in claim 11, wherein at least one of the recessed features in the substrate has a critical dimensional variation of at least 10%. The method of claim 12, wherein the at least one non-continuous time base parameter is modified based on the critical size variation of the at least one recessed feature of the one or more structures. A method as claimed in claim 11, wherein at least one of the recessed features has a depth variation of at least 10% between structures. The method of claim 14, wherein the at least one non-continuous time base parameter is modified based on the depth variation of the at least one recessed feature of the one or more structures. A method as claimed in claim 1, wherein the dielectric material is an oxide material. The method of claim 16, wherein the oxide material is silicon dioxide. The method of claim 1, further comprising performing a second set of cycles: (a) exposing the substrate to the suppression plasma to suppress deposition on a second portion of the gaps, wherein, during a first subset and a second subset of the second set of cycles, exposing the substrate to the suppression plasma is performed for a second duration different from the first duration, and during the second subset of the second set of cycles, modifying the at least one non-duration of the suppression plasma as a base parameter; and (b) after (a), depositing a dielectric material in the gaps. A system for filling gaps, comprising: a process chamber, and one or more memories and one or more processors, the one or more memories being configured to have computer executable instructions for controlling the one or more processors to perform the following operations: providing a substrate in the process chamber, the substrate having one or more structures, each structure including a gap; and performing a first set of cycles: (a) exposing the substrate to a suppression plasma to suppress deposition on a first portion of each gap, and (b) After (a), a dielectric material is deposited in each gap, wherein during a first subset and a second subset of the first set of cycles, the substrate is exposed to the suppression plasma for a first duration, and during the second subset of the first set of cycles, at least one non-duration of exposure of the substrate to the suppression plasma is modified as a base parameter. A system for filling gaps, comprising: a process chamber including a plurality of stations; one or more processors and one or more memories configured to: receive a plurality of substrates in the plurality of stations, each substrate having a structure including a gap, perform a first set of cycles in each of the plurality of stations: (a) expose a substrate to a suppression plasma to suppress deposition on a first portion of the gaps, and (b) after (a), deposit a dielectric material in the gaps, and after performing the first set of cycles, perform a second set of cycles in each station of a first subset of the plurality of stations: (c) deposit dielectric material only in the gaps of the substrates in the stations of the first subset of the plurality of stations. A method for filling gaps, comprising: receiving a plurality of substrates in a plurality of stations, each substrate having a structure including a gap, performing a first set of cycles in each of the stations: (a) exposing a substrate to a suppression plasma to suppress deposition on a first portion of the gaps, and (b) after (a), depositing a dielectric material in the gaps, and performing a second set of cycles in each station of a first subset of the plurality of stations after performing the first set of cycles: (c) depositing dielectric material only in the gaps of the substrates in the stations of the first subset of the plurality of stations.

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