TW202321535A - Method of forming porous iii-nitride material - Google Patents

Abstract

A method for forming porous III-nitride material comprises the steps of exposing a III-nitride material to a gas, coupling the III-nitride material to one terminal of a power supply, and coupling an electrode to another terminal of the power supply, and via the gas forming a circuit. The method comprises the step of energising the circuit to etch a plurality of pores in the III-nitride material and thereby form a porous III-nitride material. Pores are preferably formed in III-nitride material having a charge carrier density of greater than 1x10<SP>17</SP> cm<SP>-3</SP>. A semiconductor structure, a template for semiconductor overgrowth, and a semiconductor device comprising porous III-nitride material formed by the method are also provided.

Description

Method of forming porous III-nitride materials

The present invention relates to a method for forming porous III-nitride materials, and to porous III-nitride materials and semiconductor devices made therefrom.

Background of the invention

"Group III-V" semiconductors comprise binary, ternary, and quaternary alloys of Group III elements such as Ga, Al, and In with Group V elements such as N, P, As, and Sb, and are essential for many applications involving optoelectronic engineering. application is of great interest.

Group III-V semiconductor materials are of particular interest for semiconductor device design, especially the family of Group III nitride semiconductor materials.

"Group III-V" semiconductors comprise binary, ternary, and quaternary alloys of Group III elements such as Ga, Al, and In with Group V elements such as N, P, As, and Sb, and are essential for many applications involving optoelectronic engineering. application is of great interest.

Of particular interest is the class of semiconductor materials known as "III-nitride" materials, which includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), along with their ternary and quaternary alloys (Al,In)GaN. Different crystal orientations can be used in the present invention, such as polar c-plane, non-polar and semi-polar orientations. There are two main non-polar orientations, a-plane (11-20) and m-plane (1-100). Regarding semipolarity, there are (11-22), {2021} which are a family of crystal planes. Group III nitride materials not only achieve commercial success in solid-state lighting and power electronics, but also show special advantages for quantum light sources and light-matter interactions.

While various III-nitride materials are of commercial interest, gallium nitride (GaN) is widely regarded as one of the most important new semiconductor materials and is of particular interest for many applications .

It is known that the introduction of holes into bulk Ill-nitrides such as GaN can profoundly affect their material properties (optical, mechanical, electrical and thermal, etc.). The possibility to tune a wide range of material properties of GaN and III-nitride semiconductors by varying its porosity thus makes porous GaN of great interest for optoelectronic engineering applications.

Prior art methods for forming porous III-nitride materials have focused on electrochemical (EC) etching in liquid electrolytes such as oxalic acid, and photoelectrochemical (PEC) etching, in which case the III-nitride material During the electrochemical etching, ultraviolet light is used for irradiation. Examples of such techniques for porous Ill-nitride materials are disclosed in, for example, US 9,206,524 B2 and International Patent Applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

Summary of the invention

The present invention provides a method for forming a porous Ill-nitride material, as defined in the accompanying independent claims to which reference is now made. Preferred or advantageous features of the invention are set forth in the appended sub-clause.

According to a first aspect of the present invention, there is provided a method for forming a porous Ill-nitride material. The method includes the steps of exposing a III-nitride material to a gas, coupling the III-nitride material to a terminal of a power supply, and coupling an electrode to another terminal of the power supply. terminals. A circuit is formed between the III-nitride material and the electrode via the gas, and the circuit is energized to etch pores in the III-nitride material thereby forming a porous III-nitride Material.

The Ill-nitride material is preferably a non-porous Ill-nitride material before the circuit is energized, and thus the method may alternatively be referred to as a method for porosifying a Ill-nitride material.

Energizing the circuit preferably creates a gas plasma (composed of a gas of ions) through which current can flow between the Ill-nitride material and the electrode to complete the circuit.

The holes can be etched in the Ill-nitride material by plasma electrolytic etching. The pores can be etched in the Ill-nitride material by plasma electrolytic oxidation or reduction (or redox reaction).

The method may include the steps of exposing a semiconductor structure including a first region of III-nitride material to a gas, coupling the semiconductor structure to a terminal of a power supply, and coupling an electrode to The other terminal of the power supply. A circuit is formed between the first region of III-nitride material and the electrode via the gas, and the circuit is energized to etch holes in the first region of III-nitride material by This forms a porous region of Ill-nitride material.

The first region of III-nitride material may preferably have a charge carrier density greater than 1×10 ¹⁷ cm ⁻³ . The first region may be formed from a doped Group III nitride semiconductor material having a charge carrier density greater than 5x10 ¹⁷ cm ^-3 or 1x10 ¹⁸ cm ^-3 or 5x10 ¹⁸ cm ^-3 or 1x10 ¹⁹ cm ^-3 form.

When the circuit is energized, holes are selectively formed in regions of the semiconductor structure having a charge carrier density above a threshold. For example, holes can be selectively formed in regions of the semiconductor structure having a charge carrier density above a threshold of 1×10 ¹⁷ cm ⁻³ . Since the first region of III-nitride preferably has a charge carrier density greater than 1×10 ¹⁷ cm ⁻³ , holes are formed in the first region.

Unlike the prior art methods for forming porous Ill-nitride materials, in the method of the present invention, the Ill-nitride material is not exposed to an electrolyte. In the prior art, a liquid electrolyte has been a key component for photoelectrochemical etching, but in the method of the present invention, the Ill-nitride material does not contact a liquid electrolyte.

Because no liquid electrolyte is used in the plasma electrolytic etching process of the present invention, the present invention advantageously eliminates the requirement for costly, time-consuming and contaminating cleaning steps after porosification. The gas-based method of the present invention may also be significantly better than the liquid electrolyte method for the purpose of mass production of porous wafers and integration with automated wafer handling equipment.

The gas may be a pure gas, or the gas may be a mixture of one or more gases of one or more elements or compounds.

In a preferred specific example, the gas may contain H ₂ , O ₂ , N ₂ , Ar, CO ₂ , CH ₄ , H ₂ O, H ₂ O ₂ , O ₃ , CO, SO ₂ , SO ₃ , NO ₂ , NO, H ₂ S, NH ₃ , Cl ₂ , Br ₂ , F ₂ , I ₂ , HCl, HBr or HF, or H ₂ , O ₂ , N ₂ , Ar, CO ₂ , CH ₄ , H ₂ O, H ₂ O ₂ , O ₃ , CO, SO ₂ , SO ₃ , NO ₂ , NO, H ₂ S, NH ₃ , Cl ₂ , Br ₂ , F ₂ , I ₂ , HCl, HBr or HF A mixture of two or more of them. The gas can be air.

The composition of the gas may remain constant throughout the etch process. Optionally, the composition of the gas may be varied during etching of the holes in the Ill-nitride material.

The method may further comprise the step of varying the composition of the gas. The method may include the step of varying the composition of the gas as a function of time to create a porosity profile in the Ill-nitride material. The porosity distribution can include variations in pore morphology, pore size, and percent porosity.

The method may include the step of varying the composition of the gas while the circuit is energized, or alternatively the steps of de-energizing the circuit, altering the composition of the gas, and re-energizing the circuit.

Preferably the method is carried out using the Ill-nitride material and the electrode in a chamber in which a gas can be sealed or through which a gas can be pumped. The gas can be continuously pumped through the chamber. The composition of the gas can thus be altered at any point in the etching process by changing the composition of the gas fed into the vessel.

The gas may contain a vapor of one or more inorganic salts. For example, the gas may comprise a vapor containing one or more of the following: LiF, NaF, NaCl, LiCl, KCl, LiBr, _LiNO3 , _NaNO3 , _KNO3 , _CaCl2 , _SnCl2 , _ZnCl2 , ZnBr ₂ , CuCl ₂ , AlCl ₃ , FeCl ₃ , TiCl ₄ , ZrCl ₄ , PCl ₃ , PCl ₅ , NH ₄ Cl, NH ₄ NO ₃ .

The gas may contain a vapor of one or more metals. For example, the gas may comprise a vapor comprising one or more of: Li, Na, K, Hg, Ga, In, Al or Pb.

The gas may contain a vapor of one or more acids, preferably one or more acids with a low boiling point (eg < 350° C. at 1 atm). For example, the gas may comprise a vapor comprising one or more of: formic acid, acetic acid, propionic acid, butyric acid, citric acid, oxalic acid, _HPO3 .

In addition to, or in place of, the gases and gas mixtures described above, the vapor of the one or more inorganic salts and/or the vapor of the one or more metals and/or the one or more Vapors of various acids can be introduced into the gas. For example, at a predetermined time, and/or over a predetermined duration, the vapor of the one or more inorganic salts and/or the vapor of the one or more metals and/or the one or more Vapors of acids may be introduced into the gas during the porosification process.

The method may comprise the step of exposing the III-nitride material to a vapor of one or more inorganic salts and/or a vapor of one or more metals and/or a vapor of one or more acids , in order to generate a porosity distribution. During the etching of the holes, the vapor of the one or more inorganic salts and/or the vapor of the one or more metals and/or the vapor of the one or more acids may be introduced into the gas through A predetermined period of time, so that the composition of the gas is altered to contain these components during the predetermined period of time. Introducing certain components into the gas during the process advantageously allows the porosity distribution of the Ill-nitride material to be controlled as the process of etching the pores proceeds.

The method may comprise the step of applying a voltage ranging between 0.1 V and 500 kV, or between 0.1 V and 250 kV, or between 0.1 V and 150 kV. To complete the electrical circuit, the voltage is applied between the electrode and the III-nitride material such that the electrical circuit is completed by ions in the gas flowing between the electrode and the III-nitride material .

The method may comprise the step of applying a voltage ranging between 0.1 V and 10000 V, or between 0.5 V and 5000 V, or between 1 V and 1000 V. To complete the electrical circuit, the voltage is applied between the electrode and the III-nitride material such that the electrical circuit is completed by ions in the gas flowing between the electrode and the III-nitride material .

The method may include the step of varying the voltage as a function of time. Varying the voltage across the circuit during the process may advantageously allow the porosity distribution of the Ill-nitride material to be controlled as the process of etching the pores proceeds.

In some embodiments, the etching may include: applying a first voltage V ₁ for a first duration t _V1 ; and applying a second voltage V ₂ for a second duration t _V2 .

Optionally, the voltage may be swept between a first voltage V ₁ and a second voltage V ₂ for a predetermined period of time. For example, the voltage can be ramped from the first voltage to the second voltage.

The amplitude of the voltage may in some embodiments increase from about 1 volt to a maximum value of up to 500,000 volts, preferably from about 1 volt to a maximum value of up to 250,000 volts within the predetermined period of time The maximum value either increases from about 1 volt up to a maximum value of 150,000 volts or 125,000 volts.

The amplitude of the voltage may in some embodiments increase from about 1 volt to a maximum value of up to 10,000 volts, preferably from about 1 volt to a maximum value of up to 2000 volts or From about 1 volt up to a maximum of 1000 volts or 500 volts.

The method may include the step of applying a voltage exceeding a first breakdown voltage. The first breakdown voltage may typically be lower than 10 kV, or lower than 5 kV, or preferably lower than 1 kV.

When the voltage between the electrode and the Ill-nitride material is greater than the first breakdown voltage, the gas decomposes to form a conductive ion plasma.

The method may include the step of applying a voltage exceeding a second breakdown voltage. The second breakdown voltage may typically be greater than 10 kV, or greater than 50 kV, or greater than 75 kV, or greater than 100 kV.

When the voltage between the electrode and the Ill-nitride material exceeds the second breakdown voltage, the Ill-nitride material begins to decompose and the porosification process occurs.

The voltage may be applied in a series of voltage pulses, optionally a series of voltage pulses of alternating polarity, for a predetermined period of time. In some preferred embodiments, the voltage pulses have a pulse repetition frequency between 0.1 and 20 KHz, preferably between 1.5 and 15 KHz, or between 2 and 10 KHz.

The Ill-nitride material can be coupled to a negative terminal or a positive terminal of the power supply.

The method may optionally include the step of varying the pressure of the gas while the pores are being etched. Preferably, the pressure of the gas can be varied while the circuit is energized. Varying the gas pressure during the process advantageously allows the porosity distribution of the Ill-nitride material to be controlled as the process of etching the pores proceeds.

The method may comprise sweeping the pressure of the gas from a first gas pressure P ₁ to a second gas pressure P ₂ pressure. For example, the pressure of the gas may be between 0 bar and 20 bar, or between 1 bar and 15 bar, or between 1 bar and 10 bar, when the circuit is energized is scanned or ramped up.

The method may comprise the steps of: applying a first gas pressure P ₁ for a first duration t _P1 ; and applying a second gas pressure P ₂ for a second duration t _P2 .

The method optionally may include the step of varying a temperature of the gas and/or the Ill-nitride material. The temperature may preferably be varied while the circuit is energized. Varying the temperature as a function of time during the process advantageously allows the porosity distribution of the Ill-nitride material to be controlled as the process of etching the pores proceeds.

The method may comprise the steps of: applying a first gas temperature T ₁ for a first duration t _T1 ; and applying a second gas pressure T ₂ for a second duration t _P2 .

Optionally, the temperature of the gas is swept between a first temperature _T1 and a second temperature _T2 over a predetermined period of time.

The method may comprise the step of: at a temperature ranging between -50°C and 1100°C, or between 0°C and 1000°C, or between 50°C and 800°C, or between 100°C and 500°C , exposing the III-nitride material to the gas.

The method may comprise the step of varying the temperature of one of the gas and the Ill-nitride material between a first temperature _T1 and a second temperature _T2 while the circuit is energized.

The method may include the step of varying the separation or distance between the Ill-nitride material (or the semiconductor structure) and the electrode while the circuit is energized. When the circuit is energized, the distance between the III-nitride material (or the semiconductor structure) and the electrode may be zero (so that the electrode is in contact with the semiconductor structure being porosified), Or it can be greater than zero (so that there is a separation between the electrode and the semiconductor structure being porosified).

The method may include the step of forming a non-uniform porosity distribution in the III-nitride material by varying or adjusting one or more of: the composition of the gas; the gas applied to the electrode and the voltage across the Ill-nitride material; the temperature of the gas; and the pressure of the gas. These parameters can be changed while the circuit is powered on, or the circuit can be temporarily powered down and then powered back on after the parameters have been adjusted.

The porosity distribution can include variations in pore morphology, pore size, and percent porosity. By varying or adjusting the composition of the gas, the voltage applied between the electrode and the III-nitride material, the distance between the electrode and the III-nitride material, the temperature of the gas, and the gas The formation of pores in the porous III-nitride material advantageously can be controlled to give a desired porosity in the formed porous III-nitride material by one or more of the pressures degree distribution.

The III-nitride material is preferably selected from the list consisting of GaN, AlGaN, InGaN, InAlN, AlInGaN and AlN.

The Ill-nitride material may preferably be disposed on a substrate comprising _sapphire , silicon, silicon carbide, β- _Ga2O3 or bulk GaN. The III-nitride material to be porosified is preferably provided on the substrate as a layer of crystalline semiconductor material or at least a region of a layer of crystalline semiconductor material. The substrate prevents one side of the Ill-nitride material from coming into contact with the gas.

The at least one first region of the Ill-nitride material is preferably composed of n-type, preferably doped with one or more of silicon (Si), germanium (Ge), and oxygen (O). Doped III-nitride materials.

The plurality of holes can be etched in a first region of the Ill-nitride material. The first region of III-nitride material has a charge carrier density greater than 1×10 ¹⁷ cm ⁻³ . The first region may be formed from a doped group III nitride semiconductor material with a charge carrier density greater than 5x10 ¹⁷ cm ^-3 , or 1x10 ¹⁸ cm ^-3 , or 5x10 ¹⁸ cm ^-3 , or 1x10 ¹⁹ cm ^-3 be formed.

Holes are selectively formed in doped portions of the Ill-nitride material, typically in doped portions of the Ill-nitride material having a charge carrier concentration greater than 1×10 ¹⁷ cm ⁻³ .

The Ill-nitride material may additionally include a second portion having a charge carrier density lower than 1×10 ¹⁷ cm ⁻³ , no holes are formed in the second portion when the circuit is energized.

When the circuit is energized, pores are formed in the first region of the Ill-nitride material such that the first region of the Ill-nitride material becomes a porous region of the Ill-nitride material. The first region may have a thickness of at least 1 nm (preferably at least 10 nm, particularly preferably at least 50 nm). For example, the first region may have a thickness between 1 nm and 10000 nm.

The Ill-nitride material to be made porous may be part of a semiconductor structure. For example, the semiconductor structure may include multiple layers of Ill-nitride material, including a first region of Ill-nitride material that will be porous when the circuit is energized. first area

The first region of the Ill-nitride material may be a first layer such that after the porosification process has occurred, the semiconductor structure includes a porous layer of Ill-nitride material. Preferably, the first region may be a layer of doped III-nitride material having a uniform charge carrier density such that porosification of the first region becomes, for example, from a porous III-nitride A continuous porous layer formed from a continuous layer of compound material.

The semiconductor structure can include a plurality of first regions having a charge carrier density high enough to be porosified, and a plurality of second regions having a charge carrier density low enough not to be porosified. In a preferred embodiment, for example, the semiconductor structure may include a plurality of first layers having a charge carrier density greater than 1×10 ¹⁷ cm ⁻³ , and a plurality of second layers having a charge carrier density lower than 1×10 ¹⁷ cm ⁻³ such that after porosification, the semiconductor structure comprises porous layers formed from the first layers and nonporous second layers.

In a particularly preferred embodiment, the semiconductor structure comprises a layer consisting of alternating first layers having a charge carrier density greater than 1x10 ¹⁷ cm ^-3 and layers having a charge carrier density lower than 1x10 ¹⁷ cm ^-3 The second layer of stacking. After the circuit has been energized and holes have been formed in the first layers, the semiconductor structure thus comprises a stack of alternating porous and non-porous layers.

In some embodiments, the semiconductor structure includes multiple first regions, and holes are formed in the first regions when the circuit is energized. Thus, rather than being a single porous layer of Ill-nitride material, the porous semiconductor structure may comprise multiple porous regions, for example, a stack of Ill-nitride material layers in which the Ill-nitride material At least some of the layers are porous. The stack of porous layers may preferably be a stack of alternating porous and non-porous layers.

Optionally, after the porosification process, the semiconductor structure may comprise a layer of III-nitride material comprising one or more porous regions formed from the porous first region, for example, in an additional One or more porous regions in the non-porous layer of III-nitride material. In other words, the porous region need not be a continuous layer of porous material.

In preferred embodiments, the porous region or layer may have a lateral dimension (width or length) equal to that of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes may have various dimensions, such as 1 cm ² or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches or 16 inches in diameter. However, by patterning one or more layers and/or depositing regions with different charge carrier concentrations on the same layer, smaller porous regions that do not span the entire substrate can be formed. The lateral dimension of the porous layer or region can thus vary from roughly 1/10 of a pixel (eg 0.1 μm) up to as high as the lateral dimension of the substrate itself.

The III-nitride material can preferably be provided as a 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm), or Wafers with a diameter of 16 inches or larger.

Preferably, the method can generate in the first region having an average pore size greater than 1 nm, or 2 nm, or 10 nm, or 20 nm and/or less than 50 nm, or 60 nm, or 70 nm. hole.

The pore size and morphology of the first region and the resulting percent porosity can advantageously be controlled by controlling the charge carrier concentration of the first region and during porosification including voltage amplitude, voltage control scheme, gas composition, gas The parameters of pressure and temperature are controlled.

Preferably, the method porosifies the first region such that it is microporous. That is, it has an average pore size below 2 nm. Optionally, the method may porosify the first region such that it is mesoporous. That is, it has an average pore size between 2 nm and 50 nm. Optionally, the method may porosify the first region such that it is macroporous. That is, it has an average pore size greater than 50 nm.

The method may include the steps of: forming an n-type layer, a p-type layer, and an InGaN/GaN active layer between the n-type layer and the p-type layer on the porous III-nitride material to form A Light Emitting Diode (LED). The LED can be formed on top of the porous Ill-nitride material according to known semiconductor device fabrication techniques.

In some embodiments, the doped first region may be a surface layer of the semiconductor structure such that when the circuit is energized, the doped first region of III-nitride material is directly exposed to this gas. A hole may be formed in the surface layer of the semiconductor structure.

In alternative embodiments, the doped first region of Ill-nitride material may be a subsurface first region that is not directly exposed to the gas when the circuit is energized. In such embodiments, the semiconductor structure may include an electrically insulating surface layer covering the first region. Subsurface First Region

In addition to the doped first region, the semiconductor structure may comprise a non-porous surface layer of III-nitride material disposed over the porous region such that the surface layer covers the first region and prevents It comes into contact with the gas. The first region may thus be a "subsurface" first region. The surface layer may preferably be a non-porous layer through which plasma electrolytic etching of the porous regions occurs. The surface layer may preferably have a charge carrier density below 1×10 ¹⁷ cm ⁻³ such that no pores are formed in the surface layer when the circuit is energized.

The semiconductor structure preferably comprises a surface layer of electrically insulating material, which may be referred to as a capping layer, disposed on or over the first region of III-nitride material. In preferred embodiments, the capping layer may be a layer of undoped Ill-nitride material such as undoped GaN. Since the capping layer is undoped, it has a charge carrier density below 1x10 ¹⁷ cm ^-3 , so that no holes are formed in this layer when the circuit is energized.

The first region of Ill-nitride material is preferably configured or disposed between a substrate and an electrically insulating capping layer covering the top surface of the first region.

As described in International Patent Application PCT/GB2017/052895 (published as WO 2019/063957), etching can advantageously proceed through the undoped surface layer without damaging the surface layer or forming hole. Thus, the first region of Ill-nitride material can be porous even though the first region is a subsurface and is not in direct contact with the gas. In a similar manner, multiple subsurface doped first regions or layers can be porosified using the method of the present invention.

The step of exposing the Ill-nitride material to the gas may include exposing the surface layer of the Ill-nitride material to the gas, or optionally contacting the surface layer with a gas. Preferably, the upper surface, top surface or outermost surface of the surface layer is exposed to the gas. Particularly preferably, only the surface layer is exposed to the gas.

The surface layer may cover only the surface above the subsurface first region of the Ill-nitride material. In other words, the subsurface first region may be disposed below or below the surface layer, or the surface layer may be disposed above the subsurface first region of Ill-nitride material. The sidewalls or edges of the subsurface first region of Ill-nitride material may be exposed, i.e. not covered by the surface layer, or alternatively, the sidewalls or edges of the subsurface first region of Ill-nitride material may be exposed. The edges may be covered such that the sidewalls are not exposed to the gas.

By controlling the charge carrier density of the surface layer and also the charge carrier density of the subsurface first region of Ill-nitride material, the subsurface first region of Ill-nitride material can advantageously be permeable to the surface layer Porosified without the surface layer itself being porous. Particularly advantageously, during the etching process, the subsurface first region of the Ill-nitride material may be electrochemically porous without the surface layer being damaged or roughened. Thus, the method of the present invention may advantageously allow the selective porosification of a complex (e.g. multi-layered) III-nitride structure without the need to apply a protective conductive layer (e.g. SiO ₂ ) to the surface layer above. This can eliminate the need for time-consuming and costly additional processing steps of applying and subsequently removing a protective top layer required by certain prior art methods.

The surface layer may have a charge carrier density of at least 5x10 ¹⁴ cm ^-3 , or 1x10 ¹⁵ cm ^-3 , or 5x10 ¹⁵ cm ^-3 , and/or below 7x10 ¹⁵ cm ^-3 , or 1x10 ¹⁶ cm ^-3 , or 5x10 ¹⁶ cm ^-3 , or 8x10 ¹⁶ cm ^-3 , so that the surface layer is not porosified during etching.

The non-porous surface layer may preferably be one of GaN, InGaN, AlGaN, AlInGaN or AlN.

By controlling the charge carrier density of the layers and/or regions of the Ill-nitride material and the charge carrier density contrast between adjacent layers, it is possible to predetermine the porosity to be made by plasma electrolytic etching. The region of the semiconducting structure that has been optimized.

The subsurface structure may have a charge carrier density of at least 5x10 ¹⁷ cm ^-3 , or at least 1x10 ¹⁸ cm ^-3 , or at least 5x10 ¹⁸ cm ^-3 , or at least 1x10 ¹⁹ cm ^-3 , or at least 5x10 ¹⁹ cm ^-3 , Or at least 1x10 ²⁰ cm ^-3 , and/or less than 1x10 ²¹ cm ^-3 , or 5x10 ²¹ cm ^-3 , or 1x10 ²² cm ^-3 , if it is to be porous.

Preferably, the surface layer and the subsurface first region comprise a III-nitride material selected from the list consisting of GaN, AlGaN, InGaN, InAlN and AlInGaN. The surface layer and the subsurface first region may be formed from the same Ill-nitride material but each having a different charge carrier density, or the layers/regions may be formed from different Ill-nitride materials to be formed.

Suitable Ill-nitride materials can have any polar or non-polar crystal orientation, for example. Suitable Ill-nitride materials may have any crystal structure [eg, a wurtzite or cubic structure and any crystal orientation. Suitable Ill-nitride materials may include polar c-plane, non-polar a-plane, or even cubic Ill-nitride materials, for example.

The surface layer is preferably a continuous layer of Ill-nitride material. That is, the surface layer is preferably substantially free of holes or large area defects.

The thickness of the surface layer is preferably at least 1 nm, or 10 nm, or 100 nm, and/or below 1 µm, or 5 µm, or 10 µm.

The thickness of the subsurface first region or subsurface first layer is preferably at least 1 nm, or 10 nm, or 100 nm, and/or below 1 µm, or 5 µm, or 10 µm.

In a particularly preferred embodiment, the surface layer is composed of GaN having a charge carrier density between 1×10 ¹⁴ cm ⁻³ and 1×10 ¹⁷ cm ⁻³ , and the subsurface first region is composed of a It is composed of n-type doped GaN with a charge carrier density greater than 5x10 ¹⁷ cm ^-3 .

Preferably, the charge carrier density in the first region of the subsurface is at least 5 times, or 10 times, or 100 times, or 1000 times, or 10,000 times higher than the charge carrier density in the surface layer, or 100,000 times, or 1,000,000 times. An increased difference between the charge carrier densities of different layers (which can be considered a "contrast" of increased charge carrier density) can advantageously increase the selectivity of the etch process.

Preferably, the threading dislocation density in both the surface layer and the subsurface first region is between 1×10 ⁴ cm ⁻² and 1×10 ¹⁰ cm ⁻² . Particularly preferably, the through dislocation densities in both the surface layer and the subsurface first region are substantially equal. Preferably, the penetrating dislocation density in both the surface layer and the subsurface first region is at least 1x10 ⁴ cm ^-2 , 1x10 ⁵ cm ^-2 , 1x10 ⁶ cm ^-2 , 1x10 ⁷ cm ^-2 or 1x10 ⁸ cm ^-2 and/or below 1x10 ⁹ cm ^-2 or 1x10 ¹⁰ cm ^-2 . Typically, growers of semiconductor materials seek to minimize the threading dislocation density of the material in order to improve material quality. However, in the present invention, a sufficient threading dislocation density may be required between the surface layer and the subsurface first region to allow etching to occur below the undoped surface layer. This may be due to enhanced charge carrier transport to the first region of the subsurface.

In order to avoid damage to the "undoped" surface layer, many authors of prior art EC porosification methods have found it necessary to apply a protective dielectric layer to the top surface of their samples.

Those skilled in the art will appreciate that in semiconductor technology, the term "undoped" is relatively imprecise, since virtually all semiconductor materials contain inherent impurities which may be considered "dopant" atoms. Different semiconductor growth methods can generate different levels of impurities and thus different intrinsic charge carrier concentrations. Where the impurity level is high, the formed semiconductor material may have a charge carrier density higher than ^{1x1017cm -3} even though the layer has not been intentionally doped.

The charge carrier density of a given layer is readily measurable by those skilled in the art, for example, by capacitance-voltage profiling or calibrated scanning capacitance microscopy. A depth profiling Hall effect technique may also be suitable. Charge carrier density may alternatively be referred to as carrier density or carrier concentration. The charge carrier density mentioned herein refers to the charge carrier density at room temperature.

The surface layer and/or the first region can be formed by epitaxial growth. The surface layer and/or the first region can be formed by molecular beam epitaxy (MBE), metal organic chemical vapor deposition (metalorganic chemical vapor deposition, MOCVD) (also known as For metal organic vapor phase epitaxy (metalorganic vapor phase epitaxy, MOVPE)), hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), ammonothermal processes (ammonothermal processes) or other suitable for growth have the necessary Traditional approach to charge carrier concentration in III-nitride materials.

The surface layer and/or the first region may be grown on an electrically insulating base layer or substrate. Preferably, the base layer is configured to form the bottom of a multilayer structure, the surface layer forms the top of the multilayer structure, with the subsurface first region disposed between the surface layer and the base layer. Preferably, the electrically insulating substrate may include sapphire, silicon, silicon carbide, LiAlO ₃ , glass or bulk GaN.

Particularly advantageously, the method of the invention does not require the sample to be pre-prepared by creating grooves in the layers, since no access to the layer edges is required. The present invention thus may require fewer processing steps and allows for the porosification of large, continuous semiconductor layers without the need for the use of conventional trenches to separate the layers.

By controlling the charge carrier density of each region of the semiconductor structure, it is possible to control which regions are made porous by the plasma electrolytic etching process. Thus, various multilayer structures can be grown in order to achieve different porosity characteristics in pre-prepared regions and/or layers.

The method of the invention thus allows selective subsurface porosification of multiple subsurface first regions according to their charge carrier density, by penetrating the surface layer and having a charge carrier density below 1×10 ¹⁷ cm ⁻³ Etching of any further subsurface regions. Particularly advantageously, the method porosifies those subsurface regions having a charge carrier density greater than 1×10 ¹⁷ cm ⁻³ without damaging, roughening or porosifying those having a charge carrier density below 1×10 ¹⁷ cm ⁻³ layer.

Since the present method provides plasma electrolytic etching through layers having a charge carrier density below 1×10 ¹⁷ cm ⁻³ , it is possible to etch holes in a region of one of the subsurface structures away from any sidewall or edge of the semiconductor structure .

Thus, the present method advantageously etches one of the subsurface structures at least 300 µm, or 500 µm, or 750 µm, or 1 mm, or 1 cm, or 5 cm apart from the closest sidewall or edge of the semiconductor structure. first area. This would not have been possible with prior art level electrochemical etching techniques, which were limited to distances where it was possible to etch from a layer edge to tens or at most hundreds of microns.

Particularly preferably, the method is carried out without providing grooves in the surface layer and the subsurface structure.

Preferably, the surface layer is not coated with an electrically insulating layer during electrochemical etching.

Preferably, the sample is not irradiated with UV radiation during electrochemical etching.

According to a second aspect of the present invention there is provided a semiconductor structure comprising porous III-nitride material formed by the method described above in relation to the first aspect of the present invention .

According to a third aspect of the present invention there is provided a template for semiconductor overgrowth comprising the method as described above in relation to the first aspect of the present invention To be formed porous III-nitride material. Preferably, further Ill-nitride epitaxial layers and device structures can be deposited directly on the template by techniques such as MBE, MOCVD or HVPE. After this isomorphic derivation, high-performance optoelectronic components can be fabricated on top of these structures. Suitable elements may include, for example, light emitting diodes (LEDs), laser diodes (LDs), high electron mobility transistors (HEMTs), solar cells, and semiconductor-based sensing elements.

According to a fourth aspect of the present invention there is provided a semiconductor element comprising porous III-nitride material formed by the method described above in relation to the first aspect of the present invention . The semiconductor element can be, for example, a light emitting diode (LED), a laser diode (LD), a high electron mobility transistor (HEMT), a solar cell or a semiconductor-based sensing element.

As shown in FIG. 1 , a chamber 100 is provided with a gas inlet 110 and a gas outlet 120 such that a gas can be continuously pumped through the chamber using a pump (not shown).

A GaN semiconductor wafer 130 is placed roughly in the center of the chamber 100 . At least one first region of the semiconductor wafer 130 has a nitrogen-doped charge carrier concentration of at least 1×10 ¹⁷ cm ⁻³ . The GaN semiconductor wafer 130 is connected to the positive terminal of a variable voltage power supply (not shown).

Also disposed in the chamber 100 is an electrode 140 which is connected to the negative terminal of the power supply.

When the semiconductor wafer to be porosified comprises an electrically insulating surface layer overlying the first region of doped III-nitride material, the electrically insulating surface layer is disposed over the first region of III-nitride material and between the electrodes 140 .

The first region of the semiconductor wafer 130 is preferably formed on a substrate that prevents the gas from contacting the bottom surface of the first region.

The gas supply is configured such that the composition of the gas as well as the gas pressure can be adjusted during operation. The temperature of the vessel may also be externally controllable using heating and cooling elements (not shown).

The power supply is controllable during operation to provide a voltage of up to 10,000 V between the GaN wafer and the electrode and can vary the voltage. The power supply can apply constant voltage, pulse voltage or sweep voltage. The power supply may preferably be an alternating current (AC) power supply.

In use, gas is pumped through the chamber 100 from the inlet 110 to the outlet 120 and a voltage is applied between the GaN wafer 130 and the electrode 140 . The voltage applied between the wafer and the electrode creates a conductive gas plasma through which current can flow between the wafer 130 and the electrode 140 .

In an exemplary method according to the present invention, the gas may be a mixture of one of _NH3 , _CH4 and _H2O . In another exemplary method, the gas may be air.

Once current is flowed through the plasma, holes are selectively etched in the first region of the GaN wafer 130 by plasma electrolytic etching, so that the first region becomes a porous region of GaN. The mechanism of porosification is considered to be substantially similar to that previously observed in EC etching. However, because no liquid electrolyte is used in the plasma electrolytic etching process of the present invention, the present invention eliminates the requirement for costly, time-consuming, and contaminating cleaning steps after porosification.

Figure 2 illustrates the same device as Figure 1, with the GaN semiconductor wafer 130 and the electrode 140 connected to the opposite terminal of the cell. The GaN semiconductor wafer 130 is connected to the negative terminal of a variable voltage power supply (not shown), and the electrode 140 is connected to the negative terminal of the power supply. The device advantageously operates with the semiconductor wafer and the electrodes connected to either terminal of the power supply.

FIG. 3 illustrates an I-V curve for plasma electrolytic etching of a nitrogen-doped GaN wafer 130 .

When the circuit is energized at a low voltage, the voltage between the electrode 140 and the semiconductor wafer 130 is gradually ramped up. When the voltage between the electrode 100 and the GaN wafer 130 exceeds the first breakdown voltage, conductive channels are formed in the GaN wafer. The first breakdown voltage may vary depending on the gas used, but is typically between 100 V and 1 kV or between 500 V and 5 kV or between 750 V and 10 kV.

While the voltage is ramped up, the separation between the GaN wafer and the (counter) electrode 140 can be varied, and the pressure and composition of the gas in the chamber 100 can be varied.

The voltage between the electrode 140 and the semiconductor wafer 130 is increased until it exceeds a second breakdown voltage at which holes are formed in the nitrogen-doped region of the GaN wafer . The second breakdown voltage may typically be between 10 kV and 500 kV or between 50 kV and 300 kV or between 75 kV and 200 kV. Typically, the second breakdown voltage is greater than 100 kV.

When the voltage between the electrode 140 and the GaN wafer exceeds the second breakdown voltage, the nitrogen-doped GaN material within the wafer begins to decompose, in the doped regions of the wafer Holes are formed in.

The voltage is maintained above the second breakdown voltage for a desired period to allow porosification of the n-doped Ill-nitride material to occur to a desired extent. The voltage across the circuit is then reduced and the circuit is powered down.

100: chamber 110: gas inlet 120: Gas outlet 130: GaN semiconductor wafer 140: electrode

Certain embodiments of the invention will now be described with reference to the drawings, in which: Figure 1 shows a schematic illustration of an experimental setup for plasma electrolytic etching; Figure 2 shows a schematic illustration of an experimental setup for plasma electrolytic etching, with the polarity of the power supply being reversed; and Figure 3 illustrates an exemplary I-V curve representative of the conditions applied between electrodes during plasma electrolytic etching.

100: chamber

110: gas inlet

120: Gas outlet

130: GaN semiconductor wafer

140: electrode

Claims (46)

A method for forming a porous III-nitride material comprising: exposing a III-nitride material to a gas, coupling the III-nitride material to one terminal of a power supply, and coupling an electrode to the other terminal of the power supply, and forming an electrical circuit through the gas; and The circuit is energized to etch holes in the Ill-nitride material and thereby form a porous Ill-nitride material. The method of claim 1, wherein energizing the circuit creates a gas plasma. The method of claim 1 or 2, wherein the holes are etched in the III-nitride material by plasma electrolytic etching. The method of any one of the preceding claims, wherein the Ill-nitride material is not exposed to an electrolyte. The method of any one of the preceding claims, wherein the gas is a gas mixture. The method according to any one of the preceding claims, wherein the gas contains H ₂ , O ₂ , N ₂ , Ar, CO ₂ , CH ₄ , H ₂ O, H ₂ O ₂ , O ₃ , CO, SO ₂ , SO ₃ , NO ₂ , NO, H ₂ S, NH ₃ , Cl ₂ , Br ₂ , F ₂ , I ₂ , HCl, HBr or HF, or H ₂ , O ₂ , N ₂ , Ar, CO ₂ , CH _4. H ₂ O, H ₂ O ₂ , O ₃ , CO, SO ₂ , SO ₃ , NO ₂ , NO, H ₂ S, NH ₃ , Cl ₂ , Br ₂ , F ₂ , I ₂ , HCl, HBr or A mixture of two or more of HF, or where the gas is air. A method as in any one of the preceding claims, wherein the gas comprises a vapor of one or more inorganic salts. The method of claim 7, wherein the gas contains LiF, NaF, NaCl, LiCl, KCl, LiBr, LiNO ₃ , NaNO 3 , KNO ₃ , CaCl ₂ , SnCl ₂ , ZnCl ₂ , ZnBr _{2 ,} CuCl ₂ , AlCl ₃ , FeCl ₃ , TiCl ₄ , ZrCl ₄ , PCl ₃ , PCl ₅ , NH ₄ Cl, NH ₄ NO ₃ or one or more vapors. The method of any one of the preceding claims, wherein the gas comprises a vapor of one or more metals. The method according to claim 9, wherein the gas contains a vapor of one or more of Li, Na, K, Hg, Ga, In, Al or Pb. A method as in any one of the preceding claims, wherein the gas comprises a vapor of one or more acids, preferably one or more of which has a low boiling point (e.g., boiling point < 350°C at 1 atm) ) acid. The method of claim 11, wherein the gas comprises one or more vapors of formic acid, acetic acid, propionic acid, butyric acid, citric acid, oxalic acid or HPO ₃ :. The method of any one of the preceding claims, further comprising the step of varying the composition of the gas. The method of claim 13, comprising the step of varying the composition of the gas as a function of time to generate a porosity profile. 13. The method of claim 13, comprising the step of varying the composition of the gas while the circuit is energized, or comprising the steps of de-energizing the circuit, changing the composition of the gas, and re-energizing the circuit. A method according to any one of the preceding claims, comprising the step of exposing the III-nitride material to a vapor of one or more inorganic salts and/or one of one or more metals as a function of time steam to create a porosity distribution. The method of any one of the preceding claims, further comprising the step of applying a voltage ranging between 0.1 V and 500,000 V, or between 0.5 V and 250,000 V, or between 1 V and 150,000 V. The method of any one of the preceding claims, further comprising the step of varying the voltage as a function of time. The method of any one of the preceding claims, wherein the etching comprises: applying a first voltage V ₁ for a first duration t _V1 ; and applying a second voltage V ₂ for a second duration t _V2 . The method of any one of the preceding claims, wherein the voltage is swept between a first voltage _V1 and a second voltage _V2 for a predetermined period of time. The method of any one of the preceding claims, wherein the amplitude of the voltage increases from about 1 volt to a maximum value of up to 500,000 volts, preferably from about 1 volt to a maximum value of up to 250,000 volts within the predetermined period of time or from about 1 volt up to a maximum of 150,000 volts or 100,000 volts. The method of any one of the preceding claims, further comprising the step of applying a series of voltage pulses, optionally a series of voltage pulses of alternating polarity, for a predetermined period of time. The method of claim 22, wherein the voltage pulses have a pulse repetition frequency between 0.1 and 20 KHz, preferably between 1.5 and 15 KHz, or between 2 and 10 KHz. The method of any one of the preceding claims, wherein the Ill-nitride material is coupled to a negative terminal or a positive terminal of the power supply. A method as in any one of the preceding claims, including the step of varying the pressure of the gas while the circuit is energized. The method of claim 25, comprising scanning the circuit between 0 bar and 20 bar, or between 1 bar and 15 bar, or between 1 bar and 10 bar, when the circuit is energized. The steps of the pressure of the gas. The method of claim 25, comprising the steps of: applying a first gas pressure P ₁ for a first duration t _P1 ; and applying a second gas pressure P ₂ for a second duration t _P2 . The method of any one of the preceding claims, further comprising the step of varying the temperature of one of the gas and the Ill-nitride material, preferably while the circuit is energized. The method of claim 28, comprising the steps of: applying a first gas temperature T ₁ for a first duration t _P1 ; and applying a second gas temperature T ₂ for a second duration t _P2 . The method of any one of the preceding claims, wherein the temperature of the gas is swept between a first temperature _T1 and a second temperature _T2 over a predetermined period of time. The method according to any one of claims 28 to 30, which includes falling in a range between -50°C and 1100°C, or between 0°C and 1000°C, or between 50°C and 800°C, or 100°C The step of exposing the III-nitride material to the gas at a temperature between and 500°C. The method of any one of claims 28 to 31, comprising varying the gas and the III-nitride material between a first temperature _T1 and a second temperature _T2 while the circuit is energized One temperature step. The method of any one of the preceding claims, further comprising the step of varying a distance between the electrode and the Ill-nitride material, preferably while the circuit is energized. The method of any one of the preceding claims, comprising the step of forming an inhomogeneous porosity distribution in the III-nitride material by varying one or more of: the composition of the gas ; the voltage applied between the electrode and the III-nitride material; the distance between the electrode and the III-nitride material; the temperature of the gas; and the pressure of the gas. The method of any one of the preceding claims, wherein the III-nitride material has a charge carrier concentration greater than 1×10 ¹⁷ cm ⁻³ . The method of any one of the preceding claims, wherein the at least one first region of the III-nitride material is made of preferably doped with silicon (Si), germanium (Ge) and oxygen (O) One or more n-type doped III-nitride materials. The method of any one of the preceding claims, wherein the plurality of holes are etched in a first region of the III-nitride material, and wherein the first region of the III-nitride material has a charge carrier density Greater than 1x10 ¹⁷ cm ^-3 . The method of claim 35 or 36, wherein the III-nitride material additionally comprises a second portion having a charge carrier density lower than 1×10 ¹⁷ cm ⁻³ , and wherein no pores are formed in the second portion middle. The method of any one of the preceding claims, wherein the III-nitride material is a first region of III-nitride material, and wherein an undoped surface layer of III-nitride material is disposed on III group nitride material above the first region. The method of any one of the preceding claims, further comprising forming the following on the porous III-nitride material: an n-type layer, a p-type layer, and an InGaN/GaN active layer between the n-type layer and the p-type layer, To form a light emitting diode (LED). The method of any one of the preceding claims, wherein the III-nitride material is disposed on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN. The method of any one of the preceding claims, wherein the III-nitride material is selected from the list consisting of: GaN, AlGaN, InGaN, InAlN, and AlInGaN. The method of any one of the preceding claims, wherein the III-nitride material is provided as a 8 inches (20.36 cm), or a diameter of 16 inches or larger. A semiconductor structure comprising porous III-nitride material formed by a method as defined in any one of the preceding claims. A template for semiconductor overgrowth comprising porous III-nitride material formed by a method as defined in any one of claims 1 to 43. A semiconductor device comprising porous III-nitride material formed by a method as defined in any one of claims 1-43.

Images